lib/Target/ARM/ARMMCCodeEmitter.cpp

   1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the ARMMCCodeEmitter class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "arm-emitter"
  15 #include "ARM.h"
  16 #include "ARMAddressingModes.h"
  17 #include "ARMInstrInfo.h"
  18 #include "llvm/MC/MCCodeEmitter.h"
  19 #include "llvm/MC/MCExpr.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/ADT/Statistic.h"
  22 #include "llvm/Support/raw_ostream.h"
  23 using namespace llvm;
  24
  25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
  26
  27 namespace {
  28 class ARMMCCodeEmitter : public MCCodeEmitter {
  29   ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
  30   void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
  31   const TargetMachine &TM;
  32   const TargetInstrInfo &TII;
  33   MCContext &Ctx;
  34
  35 public:
  36   ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
  37     : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
  38   }
  39
  40   ~ARMMCCodeEmitter() {}
  41
  42   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
  43
  44   // getBinaryCodeForInstr - TableGen'erated function for getting the
  45   // binary encoding for an instruction.
  46   unsigned getBinaryCodeForInstr(const MCInst &MI) const;
  47
  48   /// getMachineOpValue - Return binary encoding of operand. If the machine
  49   /// operand requires relocation, record the relocation and return zero.
  50   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
  51
  52   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
  53                               unsigned &Reg, unsigned &Imm) const;
  54
  55   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
  56   /// operand.
  57   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx) const;
  58
  59   /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
  60   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx) const;
  61
  62   /// getCCOutOpValue - Return encoding of the 's' bit.
  63   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const {
  64     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
  65     // '1' respectively.
  66     return MI.getOperand(Op).getReg() == ARM::CPSR;
  67   }
  68
  69   /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
  70   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op) const {
  71     unsigned SoImm = MI.getOperand(Op).getImm();
  72     int SoImmVal = ARM_AM::getSOImmVal(SoImm);
  73     assert(SoImmVal != -1 && "Not a valid so_imm value!");
  74
  75     // Encode rotate_imm.
  76     unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
  77       << ARMII::SoRotImmShift;
  78
  79     // Encode immed_8.
  80     Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
  81     return Binary;
  82   }
  83
  84   /// getSORegOpValue - Return an encoded so_reg shifted register value.
  85   unsigned getSORegOpValue(const MCInst &MI, unsigned Op) const;
  86
  87   unsigned getRotImmOpValue(const MCInst &MI, unsigned Op) const {
  88     switch (MI.getOperand(Op).getImm()) {
  89     default: assert (0 && "Not a valid rot_imm value!");
  90     case 0:  return 0;
  91     case 8:  return 1;
  92     case 16: return 2;
  93     case 24: return 3;
  94     }
  95   }
  96
  97   unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op) const {
  98     return MI.getOperand(Op).getImm() - 1;
  99   }
 100
 101   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op) const {
 102     return 64 - MI.getOperand(Op).getImm();
 103   }
 104
 105   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
 106
 107   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
 108   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op) const;
 109   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op) const;
 110
 111   unsigned getNumFixupKinds() const {
 112     assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
 113     return 0;
 114   }
 115
 116   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
 117     static MCFixupKindInfo rtn;
 118     assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented.");
 119     return rtn;
 120   }
 121
 122   void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
 123     OS << (char)C;
 124     ++CurByte;
 125   }
 126
 127   void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
 128                     raw_ostream &OS) const {
 129     // Output the constant in little endian byte order.
 130     for (unsigned i = 0; i != Size; ++i) {
 131       EmitByte(Val & 255, CurByte, OS);
 132       Val >>= 8;
 133     }
 134   }
 135
 136   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
 137                          SmallVectorImpl<MCFixup> &Fixups) const;
 138 };
 139
 140 } // end anonymous namespace
 141
 142 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
 143                                             MCContext &Ctx) {
 144   return new ARMMCCodeEmitter(TM, Ctx);
 145 }
 146
 147 /// getMachineOpValue - Return binary encoding of operand. If the machine
 148 /// operand requires relocation, record the relocation and return zero.
 149 unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI,
 150                                              const MCOperand &MO) const {
 151   if (MO.isReg()) {
 152     unsigned Reg = MO.getReg();
 153     unsigned RegNo = getARMRegisterNumbering(Reg);
 154
 155     // Q registers are encodes as 2x their register number.
 156     switch (Reg) {
 157     default:
 158       return RegNo;
 159     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
 160     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
 161     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
 162     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
 163       return 2 * RegNo;
 164     }
 165   } else if (MO.isImm()) {
 166     return static_cast<unsigned>(MO.getImm());
 167   } else if (MO.isFPImm()) {
 168     return static_cast<unsigned>(APFloat(MO.getFPImm())
 169                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
 170   }
 171
 172 #ifndef NDEBUG
 173   errs() << MO;
 174 #endif
 175   llvm_unreachable(0);
 176   return 0;
 177 }
 178
 179 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
 180 bool ARMMCCodeEmitter::EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
 181                                               unsigned &Reg,
 182                                               unsigned &Imm) const {
 183   const MCOperand &MO  = MI.getOperand(OpIdx);
 184   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
 185
 186   // If The first operand isn't a register, we have a label reference.
 187   if (!MO.isReg()) {
 188     Reg = ARM::PC;              // Rn is PC.
 189     Imm = 0;
 190     // FIXME: Add a fixup referencing the label.
 191     return true;
 192   }
 193
 194   Reg = getARMRegisterNumbering(MO.getReg());
 195
 196   int32_t SImm = MO1.getImm();
 197   bool isAdd = true;
 198
 199   // Special value for #-0
 200   if (SImm == INT32_MIN)
 201     SImm = 0;
 202
 203   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
 204   if (SImm < 0) {
 205     SImm = -SImm;
 206     isAdd = false;
 207   }
 208
 209   Imm = SImm;
 210   return isAdd;
 211 }
 212
 213 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
 214 uint32_t ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI,
 215                                                    unsigned OpIdx) const {
 216   // {17-13} = reg
 217   // {12}    = (U)nsigned (add == '1', sub == '0')
 218   // {11-0}  = imm12
 219   unsigned Reg, Imm12;
 220   bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12);
 221
 222   if (Reg == ARM::PC)
 223     return ARM::PC << 13;       // Rn is PC;
 224
 225   uint32_t Binary = Imm12 & 0xfff;
 226   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
 227   if (isAdd)
 228     Binary |= (1 << 12);
 229   Binary |= (Reg << 13);
 230   return Binary;
 231 }
 232
 233 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
 234 uint32_t ARMMCCodeEmitter::getAddrMode5OpValue(const MCInst &MI,
 235                                                unsigned OpIdx) const {
 236   // {12-9} = reg
 237   // {8}    = (U)nsigned (add == '1', sub == '0')
 238   // {7-0}  = imm8
 239   unsigned Reg, Imm8;
 240   EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8);
 241
 242   if (Reg == ARM::PC)
 243     return ARM::PC << 9;        // Rn is PC;
 244
 245   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
 246   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
 247   if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
 248     Binary |= (1 << 8);
 249   Binary |= (Reg << 9);
 250   return Binary;
 251 }
 252
 253 unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
 254                                            unsigned OpIdx) const {
 255   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
 256   // shifted. The second is either Rs, the amount to shift by, or reg0 in which
 257   // case the imm contains the amount to shift by.
 258   //
 259   // {3-0} = Rm.
 260   // {4}   = 1 if reg shift, 0 if imm shift
 261   // {6-5} = type
 262   //    If reg shift:
 263   //      {11-8} = Rs
 264   //      {7}    = 0
 265   //    else (imm shift)
 266   //      {11-7} = imm
 267
 268   const MCOperand &MO  = MI.getOperand(OpIdx);
 269   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
 270   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
 271   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
 272
 273   // Encode Rm.
 274   unsigned Binary = getARMRegisterNumbering(MO.getReg());
 275
 276   // Encode the shift opcode.
 277   unsigned SBits = 0;
 278   unsigned Rs = MO1.getReg();
 279   if (Rs) {
 280     // Set shift operand (bit[7:4]).
 281     // LSL - 0001
 282     // LSR - 0011
 283     // ASR - 0101
 284     // ROR - 0111
 285     // RRX - 0110 and bit[11:8] clear.
 286     switch (SOpc) {
 287     default: llvm_unreachable("Unknown shift opc!");
 288     case ARM_AM::lsl: SBits = 0x1; break;
 289     case ARM_AM::lsr: SBits = 0x3; break;
 290     case ARM_AM::asr: SBits = 0x5; break;
 291     case ARM_AM::ror: SBits = 0x7; break;
 292     case ARM_AM::rrx: SBits = 0x6; break;
 293     }
 294   } else {
 295     // Set shift operand (bit[6:4]).
 296     // LSL - 000
 297     // LSR - 010
 298     // ASR - 100
 299     // ROR - 110
 300     switch (SOpc) {
 301     default: llvm_unreachable("Unknown shift opc!");
 302     case ARM_AM::lsl: SBits = 0x0; break;
 303     case ARM_AM::lsr: SBits = 0x2; break;
 304     case ARM_AM::asr: SBits = 0x4; break;
 305     case ARM_AM::ror: SBits = 0x6; break;
 306     }
 307   }
 308
 309   Binary |= SBits << 4;
 310   if (SOpc == ARM_AM::rrx)
 311     return Binary;
 312
 313   // Encode the shift operation Rs or shift_imm (except rrx).
 314   if (Rs) {
 315     // Encode Rs bit[11:8].
 316     assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
 317     return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
 318   }
 319
 320   // Encode shift_imm bit[11:7].
 321   return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
 322 }
 323
 324 unsigned ARMMCCodeEmitter::getBitfieldInvertedMaskOpValue(const MCInst &MI,
 325                                                           unsigned Op) const {
 326   // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
 327   // msb of the mask.
 328   const MCOperand &MO = MI.getOperand(Op);
 329   uint32_t v = ~MO.getImm();
 330   uint32_t lsb = CountTrailingZeros_32(v);
 331   uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
 332   assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
 333   return lsb | (msb << 5);
 334 }
 335
 336 unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI,
 337                                                   unsigned Op) const {
 338   // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
 339   // register in the list, set the corresponding bit.
 340   unsigned Binary = 0;
 341   for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
 342     unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
 343     Binary |= 1 << regno;
 344   }
 345   return Binary;
 346 }
 347
 348 unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI,
 349                                                       unsigned Op) const {
 350   const MCOperand &Reg = MI.getOperand(Op);
 351   const MCOperand &Imm = MI.getOperand(Op + 1);
 352
 353   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
 354   unsigned Align = 0;
 355
 356   switch (Imm.getImm()) {
 357   default: break;
 358   case 2:
 359   case 4:
 360   case 8:  Align = 0x01; break;
 361   case 16: Align = 0x02; break;
 362   case 32: Align = 0x03; break;
 363   }
 364
 365   return RegNo | (Align << 4);
 366 }
 367
 368 unsigned ARMMCCodeEmitter::getAddrMode6OffsetOpValue(const MCInst &MI,
 369                                                      unsigned Op) const {
 370   const MCOperand &MO = MI.getOperand(Op);
 371   if (MO.getReg() == 0) return 0x0D;
 372   return MO.getReg();
 373 }
 374
 375 void ARMMCCodeEmitter::
 376 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
 377                   SmallVectorImpl<MCFixup> &) const {
 378   // Pseudo instructions don't get encoded.
 379   const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
 380   if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
 381     return;
 382
 383   // Keep track of the current byte being emitted.
 384   unsigned CurByte = 0;
 385   EmitConstant(getBinaryCodeForInstr(MI), 4, CurByte, OS);
 386   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
 387 }
 388
 389 // FIXME: These #defines shouldn't be necessary. Instead, tblgen should
 390 // be able to generate code emitter helpers for either variant, like it
 391 // does for the AsmWriter.
 392 #define ARMCodeEmitter ARMMCCodeEmitter
 393 #define MachineInstr MCInst
 394 #include "ARMGenCodeEmitter.inc"
 395 #undef ARMCodeEmitter
 396 #undef MachineInstr