1 //===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction Itinerary classes used for ARM
13 def IIC_iALUx : InstrItinClass;
14 def IIC_iALUi : InstrItinClass;
15 def IIC_iALUr : InstrItinClass;
16 def IIC_iALUsi : InstrItinClass;
17 def IIC_iALUsir : InstrItinClass;
18 def IIC_iALUsr : InstrItinClass;
19 def IIC_iBITi : InstrItinClass;
20 def IIC_iBITr : InstrItinClass;
21 def IIC_iBITsi : InstrItinClass;
22 def IIC_iBITsr : InstrItinClass;
23 def IIC_iUNAr : InstrItinClass;
24 def IIC_iUNAsi : InstrItinClass;
25 def IIC_iEXTr : InstrItinClass;
26 def IIC_iEXTAr : InstrItinClass;
27 def IIC_iEXTAsr : InstrItinClass;
28 def IIC_iCMPi : InstrItinClass;
29 def IIC_iCMPr : InstrItinClass;
30 def IIC_iCMPsi : InstrItinClass;
31 def IIC_iCMPsr : InstrItinClass;
32 def IIC_iTSTi : InstrItinClass;
33 def IIC_iTSTr : InstrItinClass;
34 def IIC_iTSTsi : InstrItinClass;
35 def IIC_iTSTsr : InstrItinClass;
36 def IIC_iMOVi : InstrItinClass;
37 def IIC_iMOVr : InstrItinClass;
38 def IIC_iMOVsi : InstrItinClass;
39 def IIC_iMOVsr : InstrItinClass;
40 def IIC_iMOVix2 : InstrItinClass;
41 def IIC_iMVNi : InstrItinClass;
42 def IIC_iMVNr : InstrItinClass;
43 def IIC_iMVNsi : InstrItinClass;
44 def IIC_iMVNsr : InstrItinClass;
45 def IIC_iCMOVi : InstrItinClass;
46 def IIC_iCMOVr : InstrItinClass;
47 def IIC_iCMOVsi : InstrItinClass;
48 def IIC_iCMOVsr : InstrItinClass;
49 def IIC_iMUL16 : InstrItinClass;
50 def IIC_iMAC16 : InstrItinClass;
51 def IIC_iMUL32 : InstrItinClass;
52 def IIC_iMAC32 : InstrItinClass;
53 def IIC_iMUL64 : InstrItinClass;
54 def IIC_iMAC64 : InstrItinClass;
55 def IIC_iLoad_i : InstrItinClass;
56 def IIC_iLoad_r : InstrItinClass;
57 def IIC_iLoad_si : InstrItinClass;
58 def IIC_iLoad_iu : InstrItinClass;
59 def IIC_iLoad_ru : InstrItinClass;
60 def IIC_iLoad_siu : InstrItinClass;
61 def IIC_iLoad_bh_i : InstrItinClass;
62 def IIC_iLoad_bh_r : InstrItinClass;
63 def IIC_iLoad_bh_si : InstrItinClass;
64 def IIC_iLoad_bh_iu : InstrItinClass;
65 def IIC_iLoad_bh_ru : InstrItinClass;
66 def IIC_iLoad_bh_siu : InstrItinClass;
67 def IIC_iLoad_d_i : InstrItinClass;
68 def IIC_iLoad_d_r : InstrItinClass;
69 def IIC_iLoad_d_ru : InstrItinClass;
70 def IIC_iLoad_m : InstrItinClass<0>; // micro-coded
71 def IIC_iLoad_mu : InstrItinClass<0>; // micro-coded
72 def IIC_iLoad_mBr : InstrItinClass<0>; // micro-coded
73 def IIC_iPop : InstrItinClass<0>; // micro-coded
74 def IIC_iPop_Br : InstrItinClass<0>; // micro-coded
75 def IIC_iLoadiALU : InstrItinClass;
76 def IIC_iStore_i : InstrItinClass;
77 def IIC_iStore_r : InstrItinClass;
78 def IIC_iStore_si : InstrItinClass;
79 def IIC_iStore_iu : InstrItinClass;
80 def IIC_iStore_ru : InstrItinClass;
81 def IIC_iStore_siu : InstrItinClass;
82 def IIC_iStore_bh_i : InstrItinClass;
83 def IIC_iStore_bh_r : InstrItinClass;
84 def IIC_iStore_bh_si : InstrItinClass;
85 def IIC_iStore_bh_iu : InstrItinClass;
86 def IIC_iStore_bh_ru : InstrItinClass;
87 def IIC_iStore_bh_siu : InstrItinClass;
88 def IIC_iStore_d_i : InstrItinClass;
89 def IIC_iStore_d_r : InstrItinClass;
90 def IIC_iStore_d_ru : InstrItinClass;
91 def IIC_iStore_m : InstrItinClass<0>; // micro-coded
92 def IIC_iStore_mu : InstrItinClass<0>; // micro-coded
93 def IIC_Preload : InstrItinClass;
94 def IIC_Br : InstrItinClass;
95 def IIC_fpSTAT : InstrItinClass;
96 def IIC_fpUNA32 : InstrItinClass;
97 def IIC_fpUNA64 : InstrItinClass;
98 def IIC_fpCMP32 : InstrItinClass;
99 def IIC_fpCMP64 : InstrItinClass;
100 def IIC_fpCVTSD : InstrItinClass;
101 def IIC_fpCVTDS : InstrItinClass;
102 def IIC_fpCVTSH : InstrItinClass;
103 def IIC_fpCVTHS : InstrItinClass;
104 def IIC_fpCVTIS : InstrItinClass;
105 def IIC_fpCVTID : InstrItinClass;
106 def IIC_fpCVTSI : InstrItinClass;
107 def IIC_fpCVTDI : InstrItinClass;
108 def IIC_fpMOVIS : InstrItinClass;
109 def IIC_fpMOVID : InstrItinClass;
110 def IIC_fpMOVSI : InstrItinClass;
111 def IIC_fpMOVDI : InstrItinClass;
112 def IIC_fpALU32 : InstrItinClass;
113 def IIC_fpALU64 : InstrItinClass;
114 def IIC_fpMUL32 : InstrItinClass;
115 def IIC_fpMUL64 : InstrItinClass;
116 def IIC_fpMAC32 : InstrItinClass;
117 def IIC_fpMAC64 : InstrItinClass;
118 def IIC_fpDIV32 : InstrItinClass;
119 def IIC_fpDIV64 : InstrItinClass;
120 def IIC_fpSQRT32 : InstrItinClass;
121 def IIC_fpSQRT64 : InstrItinClass;
122 def IIC_fpLoad32 : InstrItinClass;
123 def IIC_fpLoad64 : InstrItinClass;
124 def IIC_fpLoad_m : InstrItinClass<0>; // micro-coded
125 def IIC_fpLoad_mu : InstrItinClass<0>; // micro-coded
126 def IIC_fpStore32 : InstrItinClass;
127 def IIC_fpStore64 : InstrItinClass;
128 def IIC_fpStore_m : InstrItinClass<0>; // micro-coded
129 def IIC_fpStore_mu : InstrItinClass<0>; // micro-coded
130 def IIC_VLD1 : InstrItinClass;
131 def IIC_VLD1x2 : InstrItinClass;
132 def IIC_VLD1x3 : InstrItinClass;
133 def IIC_VLD1x4 : InstrItinClass;
134 def IIC_VLD1u : InstrItinClass;
135 def IIC_VLD1x2u : InstrItinClass;
136 def IIC_VLD1x3u : InstrItinClass;
137 def IIC_VLD1x4u : InstrItinClass;
138 def IIC_VLD1ln : InstrItinClass;
139 def IIC_VLD1lnu : InstrItinClass;
140 def IIC_VLD2 : InstrItinClass;
141 def IIC_VLD2x2 : InstrItinClass;
142 def IIC_VLD2u : InstrItinClass;
143 def IIC_VLD2x2u : InstrItinClass;
144 def IIC_VLD2ln : InstrItinClass;
145 def IIC_VLD2lnu : InstrItinClass;
146 def IIC_VLD3 : InstrItinClass;
147 def IIC_VLD3ln : InstrItinClass;
148 def IIC_VLD3u : InstrItinClass;
149 def IIC_VLD3lnu : InstrItinClass;
150 def IIC_VLD4 : InstrItinClass;
151 def IIC_VLD4ln : InstrItinClass;
152 def IIC_VLD4u : InstrItinClass;
153 def IIC_VLD4lnu : InstrItinClass;
154 def IIC_VST1 : InstrItinClass;
155 def IIC_VST1x2 : InstrItinClass;
156 def IIC_VST1x3 : InstrItinClass;
157 def IIC_VST1x4 : InstrItinClass;
158 def IIC_VST1u : InstrItinClass;
159 def IIC_VST1x2u : InstrItinClass;
160 def IIC_VST1x3u : InstrItinClass;
161 def IIC_VST1x4u : InstrItinClass;
162 def IIC_VST1ln : InstrItinClass;
163 def IIC_VST1lnu : InstrItinClass;
164 def IIC_VST2 : InstrItinClass;
165 def IIC_VST2x2 : InstrItinClass;
166 def IIC_VST2u : InstrItinClass;
167 def IIC_VST2x2u : InstrItinClass;
168 def IIC_VST2ln : InstrItinClass;
169 def IIC_VST2lnu : InstrItinClass;
170 def IIC_VST3 : InstrItinClass;
171 def IIC_VST3u : InstrItinClass;
172 def IIC_VST3ln : InstrItinClass;
173 def IIC_VST3lnu : InstrItinClass;
174 def IIC_VST4 : InstrItinClass;
175 def IIC_VST4u : InstrItinClass;
176 def IIC_VST4ln : InstrItinClass;
177 def IIC_VST4lnu : InstrItinClass;
178 def IIC_VUNAD : InstrItinClass;
179 def IIC_VUNAQ : InstrItinClass;
180 def IIC_VBIND : InstrItinClass;
181 def IIC_VBINQ : InstrItinClass;
182 def IIC_VPBIND : InstrItinClass;
183 def IIC_VFMULD : InstrItinClass;
184 def IIC_VFMULQ : InstrItinClass;
185 def IIC_VMOV : InstrItinClass;
186 def IIC_VMOVImm : InstrItinClass;
187 def IIC_VMOVD : InstrItinClass;
188 def IIC_VMOVQ : InstrItinClass;
189 def IIC_VMOVIS : InstrItinClass;
190 def IIC_VMOVID : InstrItinClass;
191 def IIC_VMOVISL : InstrItinClass;
192 def IIC_VMOVSI : InstrItinClass;
193 def IIC_VMOVDI : InstrItinClass;
194 def IIC_VMOVN : InstrItinClass;
195 def IIC_VPERMD : InstrItinClass;
196 def IIC_VPERMQ : InstrItinClass;
197 def IIC_VPERMQ3 : InstrItinClass;
198 def IIC_VMACD : InstrItinClass;
199 def IIC_VMACQ : InstrItinClass;
200 def IIC_VRECSD : InstrItinClass;
201 def IIC_VRECSQ : InstrItinClass;
202 def IIC_VCNTiD : InstrItinClass;
203 def IIC_VCNTiQ : InstrItinClass;
204 def IIC_VUNAiD : InstrItinClass;
205 def IIC_VUNAiQ : InstrItinClass;
206 def IIC_VQUNAiD : InstrItinClass;
207 def IIC_VQUNAiQ : InstrItinClass;
208 def IIC_VBINiD : InstrItinClass;
209 def IIC_VBINiQ : InstrItinClass;
210 def IIC_VSUBiD : InstrItinClass;
211 def IIC_VSUBiQ : InstrItinClass;
212 def IIC_VBINi4D : InstrItinClass;
213 def IIC_VBINi4Q : InstrItinClass;
214 def IIC_VSUBi4D : InstrItinClass;
215 def IIC_VSUBi4Q : InstrItinClass;
216 def IIC_VABAD : InstrItinClass;
217 def IIC_VABAQ : InstrItinClass;
218 def IIC_VSHLiD : InstrItinClass;
219 def IIC_VSHLiQ : InstrItinClass;
220 def IIC_VSHLi4D : InstrItinClass;
221 def IIC_VSHLi4Q : InstrItinClass;
222 def IIC_VPALiD : InstrItinClass;
223 def IIC_VPALiQ : InstrItinClass;
224 def IIC_VMULi16D : InstrItinClass;
225 def IIC_VMULi32D : InstrItinClass;
226 def IIC_VMULi16Q : InstrItinClass;
227 def IIC_VMULi32Q : InstrItinClass;
228 def IIC_VMACi16D : InstrItinClass;
229 def IIC_VMACi32D : InstrItinClass;
230 def IIC_VMACi16Q : InstrItinClass;
231 def IIC_VMACi32Q : InstrItinClass;
232 def IIC_VEXTD : InstrItinClass;
233 def IIC_VEXTQ : InstrItinClass;
234 def IIC_VTB1 : InstrItinClass;
235 def IIC_VTB2 : InstrItinClass;
236 def IIC_VTB3 : InstrItinClass;
237 def IIC_VTB4 : InstrItinClass;
238 def IIC_VTBX1 : InstrItinClass;
239 def IIC_VTBX2 : InstrItinClass;
240 def IIC_VTBX3 : InstrItinClass;
241 def IIC_VTBX4 : InstrItinClass;
243 //===----------------------------------------------------------------------===//
244 // Processor instruction itineraries.
246 def GenericItineraries : ProcessorItineraries<[], [], []>;
248 include "ARMScheduleV6.td"
249 include "ARMScheduleA8.td"
250 include "ARMScheduleA9.td"