lib/Target/ARM/ARMTargetMachine.h

   1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file declares the ARM specific subclass of TargetMachine.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMTARGETMACHINE_H
  15 #define ARMTARGETMACHINE_H
  16
  17 #include "llvm/Target/TargetMachine.h"
  18 #include "llvm/Target/TargetData.h"
  19 #include "llvm/MC/MCStreamer.h"
  20 #include "ARMInstrInfo.h"
  21 #include "ARMELFWriterInfo.h"
  22 #include "ARMFrameInfo.h"
  23 #include "ARMJITInfo.h"
  24 #include "ARMSubtarget.h"
  25 #include "ARMISelLowering.h"
  26 #include "ARMSelectionDAGInfo.h"
  27 #include "Thumb1InstrInfo.h"
  28 #include "Thumb2InstrInfo.h"
  29 #include "llvm/ADT/OwningPtr.h"
  30
  31 namespace llvm {
  32
  33 class ARMBaseTargetMachine : public LLVMTargetMachine {
  34 protected:
  35   ARMSubtarget        Subtarget;
  36
  37 private:
  38   ARMFrameInfo        FrameInfo;
  39   ARMJITInfo          JITInfo;
  40   InstrItineraryData  InstrItins;
  41   Reloc::Model        DefRelocModel;    // Reloc model before it's overridden.
  42
  43 public:
  44   ARMBaseTargetMachine(const Target &T, const std::string &TT,
  45                        const std::string &FS, bool isThumb);
  46
  47   virtual const ARMFrameInfo     *getFrameInfo() const { return &FrameInfo; }
  48   virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
  49   virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
  50   virtual const InstrItineraryData *getInstrItineraryData() const {
  51     return &InstrItins;
  52   }
  53
  54   // Pass Pipeline Configuration
  55   virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
  56   virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
  57   virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
  58   virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
  59   virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
  60   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
  61                               JITCodeEmitter &MCE);
  62 };
  63
  64 /// ARMTargetMachine - ARM target machine.
  65 ///
  66 class ARMTargetMachine : public ARMBaseTargetMachine {
  67   ARMInstrInfo        InstrInfo;
  68   const TargetData    DataLayout;       // Calculates type size & alignment
  69   ARMELFWriterInfo    ELFWriterInfo;
  70   ARMTargetLowering   TLInfo;
  71   ARMSelectionDAGInfo TSInfo;
  72 public:
  73   ARMTargetMachine(const Target &T, const std::string &TT,
  74                    const std::string &FS);
  75
  76   virtual const ARMRegisterInfo  *getRegisterInfo() const {
  77     return &InstrInfo.getRegisterInfo();
  78   }
  79
  80   virtual const ARMTargetLowering *getTargetLowering() const {
  81     return &TLInfo;
  82   }
  83
  84   virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
  85     return &TSInfo;
  86   }
  87
  88   virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
  89   virtual const TargetData       *getTargetData() const { return &DataLayout; }
  90   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
  91     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
  92   }
  93 };
  94
  95 /// ThumbTargetMachine - Thumb target machine.
  96 /// Due to the way architectures are handled, this represents both
  97 ///   Thumb-1 and Thumb-2.
  98 ///
  99 class ThumbTargetMachine : public ARMBaseTargetMachine {
 100   // Either Thumb1InstrInfo or Thumb2InstrInfo.
 101   OwningPtr<ARMBaseInstrInfo> InstrInfo;
 102   const TargetData    DataLayout;   // Calculates type size & alignment
 103   ARMELFWriterInfo    ELFWriterInfo;
 104   ARMTargetLowering   TLInfo;
 105   ARMSelectionDAGInfo TSInfo;
 106 public:
 107   ThumbTargetMachine(const Target &T, const std::string &TT,
 108                      const std::string &FS);
 109
 110   /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
 111   virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
 112     return &InstrInfo->getRegisterInfo();
 113   }
 114
 115   virtual const ARMTargetLowering *getTargetLowering() const {
 116     return &TLInfo;
 117   }
 118
 119   virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
 120     return &TSInfo;
 121   }
 122
 123   /// returns either Thumb1InstrInfo or Thumb2InstrInfo
 124   virtual const ARMBaseInstrInfo *getInstrInfo() const {
 125     return InstrInfo.get();
 126   }
 127   virtual const TargetData       *getTargetData() const { return &DataLayout; }
 128   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
 129     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
 130   }
 131 };
 132
 133 } // end namespace llvm
 134
 135 #endif