lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

   1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This class prints an ARM MCInst to a .s file.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "asm-printer"
  15 #include "ARMBaseInfo.h"
  16 #include "ARMInstPrinter.h"
  17 #include "ARMAddressingModes.h"
  18 #include "llvm/MC/MCInst.h"
  19 #include "llvm/MC/MCAsmInfo.h"
  20 #include "llvm/MC/MCExpr.h"
  21 #include "llvm/ADT/StringExtras.h"
  22 #include "llvm/Support/raw_ostream.h"
  23 using namespace llvm;
  24
  25 #define GET_INSTRUCTION_NAME
  26 #include "ARMGenAsmWriter.inc"
  27
  28 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
  29   return getInstructionName(Opcode);
  30 }
  31
  32
  33 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
  34   // Check for MOVs and print canonical forms, instead.
  35   if (MI->getOpcode() == ARM::MOVs) {
  36     // FIXME: Thumb variants?
  37     const MCOperand &Dst = MI->getOperand(0);
  38     const MCOperand &MO1 = MI->getOperand(1);
  39     const MCOperand &MO2 = MI->getOperand(2);
  40     const MCOperand &MO3 = MI->getOperand(3);
  41
  42     O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
  43     printSBitModifierOperand(MI, 6, O);
  44     printPredicateOperand(MI, 4, O);
  45
  46     O << '\t' << getRegisterName(Dst.getReg())
  47       << ", " << getRegisterName(MO1.getReg());
  48
  49     if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
  50       return;
  51
  52     O << ", ";
  53
  54     if (MO2.getReg()) {
  55       O << getRegisterName(MO2.getReg());
  56       assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
  57     } else {
  58       O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
  59     }
  60     return;
  61   }
  62
  63   // A8.6.123 PUSH
  64   if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
  65       MI->getOperand(0).getReg() == ARM::SP) {
  66     const MCOperand &MO1 = MI->getOperand(2);
  67     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
  68       O << '\t' << "push";
  69       printPredicateOperand(MI, 3, O);
  70       O << '\t';
  71       printRegisterList(MI, 5, O);
  72       return;
  73     }
  74   }
  75
  76   // A8.6.122 POP
  77   if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
  78       MI->getOperand(0).getReg() == ARM::SP) {
  79     const MCOperand &MO1 = MI->getOperand(2);
  80     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
  81       O << '\t' << "pop";
  82       printPredicateOperand(MI, 3, O);
  83       O << '\t';
  84       printRegisterList(MI, 5, O);
  85       return;
  86     }
  87   }
  88
  89   // A8.6.355 VPUSH
  90   if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
  91       MI->getOperand(0).getReg() == ARM::SP) {
  92     const MCOperand &MO1 = MI->getOperand(2);
  93     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
  94       O << '\t' << "vpush";
  95       printPredicateOperand(MI, 3, O);
  96       O << '\t';
  97       printRegisterList(MI, 5, O);
  98       return;
  99     }
 100   }
 101
 102   // A8.6.354 VPOP
 103   if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
 104       MI->getOperand(0).getReg() == ARM::SP) {
 105     const MCOperand &MO1 = MI->getOperand(2);
 106     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
 107       O << '\t' << "vpop";
 108       printPredicateOperand(MI, 3, O);
 109       O << '\t';
 110       printRegisterList(MI, 5, O);
 111       return;
 112     }
 113   }
 114
 115   printInstruction(MI, O);
 116  }
 117
 118 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
 119                                   raw_ostream &O) {
 120   const MCOperand &Op = MI->getOperand(OpNo);
 121   if (Op.isReg()) {
 122     unsigned Reg = Op.getReg();
 123     O << getRegisterName(Reg);
 124   } else if (Op.isImm()) {
 125     O << '#' << Op.getImm();
 126   } else {
 127     assert(Op.isExpr() && "unknown operand kind in printOperand");
 128     O << *Op.getExpr();
 129   }
 130 }
 131
 132 static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
 133                        const MCAsmInfo *MAI) {
 134   // Break it up into two parts that make up a shifter immediate.
 135   V = ARM_AM::getSOImmVal(V);
 136   assert(V != -1 && "Not a valid so_imm value!");
 137
 138   unsigned Imm = ARM_AM::getSOImmValImm(V);
 139   unsigned Rot = ARM_AM::getSOImmValRot(V);
 140
 141   // Print low-level immediate formation info, per
 142   // A5.1.3: "Data-processing operands - Immediate".
 143   if (Rot) {
 144     O << "#" << Imm << ", " << Rot;
 145     // Pretty printed version.
 146     if (CommentStream)
 147       *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
 148   } else {
 149     O << "#" << Imm;
 150   }
 151 }
 152
 153
 154 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
 155 /// immediate in bits 0-7.
 156 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
 157                                        raw_ostream &O) {
 158   const MCOperand &MO = MI->getOperand(OpNum);
 159   assert(MO.isImm() && "Not a valid so_imm value!");
 160   printSOImm(O, MO.getImm(), CommentStream, &MAI);
 161 }
 162
 163 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
 164 /// followed by an 'orr' to materialize.
 165 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
 166                                             raw_ostream &O) {
 167   // FIXME: REMOVE this method.
 168   abort();
 169 }
 170
 171 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
 172 // "Addressing Mode 1 - Data-processing operands" forms.  This includes:
 173 //    REG 0   0           - e.g. R5
 174 //    REG REG 0,SH_OPC    - e.g. R5, ROR R3
 175 //    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
 176 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
 177                                        raw_ostream &O) {
 178   const MCOperand &MO1 = MI->getOperand(OpNum);
 179   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 180   const MCOperand &MO3 = MI->getOperand(OpNum+2);
 181
 182   O << getRegisterName(MO1.getReg());
 183
 184   // Print the shift opc.
 185   ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
 186   O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
 187   if (MO2.getReg()) {
 188     O << ' ' << getRegisterName(MO2.getReg());
 189     assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
 190   } else if (ShOpc != ARM_AM::rrx) {
 191     O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
 192   }
 193 }
 194
 195
 196 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
 197                                            raw_ostream &O) {
 198   const MCOperand &MO1 = MI->getOperand(Op);
 199   const MCOperand &MO2 = MI->getOperand(Op+1);
 200   const MCOperand &MO3 = MI->getOperand(Op+2);
 201
 202   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
 203     printOperand(MI, Op, O);
 204     return;
 205   }
 206
 207   O << "[" << getRegisterName(MO1.getReg());
 208
 209   if (!MO2.getReg()) {
 210     if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
 211       O << ", #"
 212         << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
 213         << ARM_AM::getAM2Offset(MO3.getImm());
 214     O << "]";
 215     return;
 216   }
 217
 218   O << ", "
 219     << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
 220     << getRegisterName(MO2.getReg());
 221
 222   if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
 223     O << ", "
 224     << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
 225     << " #" << ShImm;
 226   O << "]";
 227 }
 228
 229 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
 230                                                  unsigned OpNum,
 231                                                  raw_ostream &O) {
 232   const MCOperand &MO1 = MI->getOperand(OpNum);
 233   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 234
 235   if (!MO1.getReg()) {
 236     unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
 237     O << '#'
 238       << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
 239       << ImmOffs;
 240     return;
 241   }
 242
 243   O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
 244     << getRegisterName(MO1.getReg());
 245
 246   if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
 247     O << ", "
 248     << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
 249     << " #" << ShImm;
 250 }
 251
 252 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
 253                                            raw_ostream &O) {
 254   const MCOperand &MO1 = MI->getOperand(OpNum);
 255   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 256   const MCOperand &MO3 = MI->getOperand(OpNum+2);
 257
 258   O << '[' << getRegisterName(MO1.getReg());
 259
 260   if (MO2.getReg()) {
 261     O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
 262       << getRegisterName(MO2.getReg()) << ']';
 263     return;
 264   }
 265
 266   if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
 267     O << ", #"
 268       << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
 269       << ImmOffs;
 270   O << ']';
 271 }
 272
 273 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
 274                                                  unsigned OpNum,
 275                                                  raw_ostream &O) {
 276   const MCOperand &MO1 = MI->getOperand(OpNum);
 277   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 278
 279   if (MO1.getReg()) {
 280     O << (char)ARM_AM::getAM3Op(MO2.getImm())
 281     << getRegisterName(MO1.getReg());
 282     return;
 283   }
 284
 285   unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
 286   O << '#'
 287     << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
 288     << ImmOffs;
 289 }
 290
 291 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
 292                                            raw_ostream &O) {
 293   ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
 294                                                  .getImm());
 295   O << ARM_AM::getAMSubModeStr(Mode);
 296 }
 297
 298 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
 299                                            raw_ostream &O) {
 300   const MCOperand &MO1 = MI->getOperand(OpNum);
 301   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 302
 303   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
 304     printOperand(MI, OpNum, O);
 305     return;
 306   }
 307
 308   O << "[" << getRegisterName(MO1.getReg());
 309
 310   if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
 311     O << ", #"
 312       << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
 313       << ImmOffs * 4;
 314   }
 315   O << "]";
 316 }
 317
 318 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
 319                                            raw_ostream &O) {
 320   const MCOperand &MO1 = MI->getOperand(OpNum);
 321   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 322
 323   O << "[" << getRegisterName(MO1.getReg());
 324   if (MO2.getImm()) {
 325     // FIXME: Both darwin as and GNU as violate ARM docs here.
 326     O << ", :" << (MO2.getImm() << 3);
 327   }
 328   O << "]";
 329 }
 330
 331 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
 332                                                  unsigned OpNum,
 333                                                  raw_ostream &O) {
 334   const MCOperand &MO = MI->getOperand(OpNum);
 335   if (MO.getReg() == 0)
 336     O << "!";
 337   else
 338     O << ", " << getRegisterName(MO.getReg());
 339 }
 340
 341 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
 342                                                     unsigned OpNum,
 343                                                     raw_ostream &O) {
 344   const MCOperand &MO = MI->getOperand(OpNum);
 345   uint32_t v = ~MO.getImm();
 346   int32_t lsb = CountTrailingZeros_32(v);
 347   int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
 348   assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
 349   O << '#' << lsb << ", #" << width;
 350 }
 351
 352 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
 353                                      raw_ostream &O) {
 354   unsigned val = MI->getOperand(OpNum).getImm();
 355   O << ARM_MB::MemBOptToString(val);
 356 }
 357
 358 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
 359                                           raw_ostream &O) {
 360   unsigned ShiftOp = MI->getOperand(OpNum).getImm();
 361   ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
 362   switch (Opc) {
 363   case ARM_AM::no_shift:
 364     return;
 365   case ARM_AM::lsl:
 366     O << ", lsl #";
 367     break;
 368   case ARM_AM::asr:
 369     O << ", asr #";
 370     break;
 371   default:
 372     assert(0 && "unexpected shift opcode for shift immediate operand");
 373   }
 374   O << ARM_AM::getSORegOffset(ShiftOp);
 375 }
 376
 377 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
 378                                        raw_ostream &O) {
 379   O << "{";
 380   for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
 381     if (i != OpNum) O << ", ";
 382     O << getRegisterName(MI->getOperand(i).getReg());
 383   }
 384   O << "}";
 385 }
 386
 387 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
 388                                         raw_ostream &O) {
 389   const MCOperand &Op = MI->getOperand(OpNum);
 390   if (Op.getImm())
 391     O << "be";
 392   else
 393     O << "le";
 394 }
 395
 396 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
 397                                            raw_ostream &O) {
 398   const MCOperand &Op = MI->getOperand(OpNum);
 399   unsigned option = Op.getImm();
 400   unsigned mode = option & 31;
 401   bool changemode = option >> 5 & 1;
 402   unsigned AIF = option >> 6 & 7;
 403   unsigned imod = option >> 9 & 3;
 404   if (imod == 2)
 405     O << "ie";
 406   else if (imod == 3)
 407     O << "id";
 408   O << '\t';
 409   if (imod > 1) {
 410     if (AIF & 4) O << 'a';
 411     if (AIF & 2) O << 'i';
 412     if (AIF & 1) O << 'f';
 413     if (AIF > 0 && changemode) O << ", ";
 414   }
 415   if (changemode)
 416     O << '#' << mode;
 417 }
 418
 419 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
 420                                          raw_ostream &O) {
 421   const MCOperand &Op = MI->getOperand(OpNum);
 422   unsigned Mask = Op.getImm();
 423   if (Mask) {
 424     O << '_';
 425     if (Mask & 8) O << 'f';
 426     if (Mask & 4) O << 's';
 427     if (Mask & 2) O << 'x';
 428     if (Mask & 1) O << 'c';
 429   }
 430 }
 431
 432 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
 433                                          raw_ostream &O) {
 434   const MCOperand &Op = MI->getOperand(OpNum);
 435   O << '#';
 436   if (Op.getImm() < 0)
 437     O << '-' << (-Op.getImm() - 1);
 438   else
 439     O << Op.getImm();
 440 }
 441
 442 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
 443                                            raw_ostream &O) {
 444   ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
 445   if (CC != ARMCC::AL)
 446     O << ARMCondCodeToString(CC);
 447 }
 448
 449 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
 450                                                     unsigned OpNum,
 451                                                     raw_ostream &O) {
 452   ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
 453   O << ARMCondCodeToString(CC);
 454 }
 455
 456 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
 457                                               raw_ostream &O) {
 458   if (MI->getOperand(OpNum).getReg()) {
 459     assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
 460            "Expect ARM CPSR register!");
 461     O << 's';
 462   }
 463 }
 464
 465 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
 466                                           raw_ostream &O) {
 467   O << MI->getOperand(OpNum).getImm();
 468 }
 469
 470 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
 471                                   raw_ostream &O) {
 472   llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
 473 }
 474
 475 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
 476                                             raw_ostream &O) {
 477   O << "#" <<  MI->getOperand(OpNum).getImm() * 4;
 478 }
 479
 480 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
 481                                       raw_ostream &O) {
 482   // (3 - the number of trailing zeros) is the number of then / else.
 483   unsigned Mask = MI->getOperand(OpNum).getImm();
 484   unsigned CondBit0 = Mask >> 4 & 1;
 485   unsigned NumTZ = CountTrailingZeros_32(Mask);
 486   assert(NumTZ <= 3 && "Invalid IT mask!");
 487   for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
 488     bool T = ((Mask >> Pos) & 1) == CondBit0;
 489     if (T)
 490       O << 't';
 491     else
 492       O << 'e';
 493   }
 494 }
 495
 496 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
 497                                                  raw_ostream &O) {
 498   const MCOperand &MO1 = MI->getOperand(Op);
 499   const MCOperand &MO2 = MI->getOperand(Op+1);
 500   O << "[" << getRegisterName(MO1.getReg());
 501   O << ", " << getRegisterName(MO2.getReg()) << "]";
 502 }
 503
 504 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
 505                                                   raw_ostream &O,
 506                                                   unsigned Scale) {
 507   const MCOperand &MO1 = MI->getOperand(Op);
 508   const MCOperand &MO2 = MI->getOperand(Op+1);
 509   const MCOperand &MO3 = MI->getOperand(Op+2);
 510
 511   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
 512     printOperand(MI, Op, O);
 513     return;
 514   }
 515
 516   O << "[" << getRegisterName(MO1.getReg());
 517   if (MO3.getReg())
 518     O << ", " << getRegisterName(MO3.getReg());
 519   else if (unsigned ImmOffs = MO2.getImm())
 520     O << ", #" << ImmOffs * Scale;
 521   O << "]";
 522 }
 523
 524 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
 525                                                  raw_ostream &O) {
 526   printThumbAddrModeRI5Operand(MI, Op, O, 1);
 527 }
 528
 529 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
 530                                                  raw_ostream &O) {
 531   printThumbAddrModeRI5Operand(MI, Op, O, 2);
 532 }
 533
 534 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
 535                                                  raw_ostream &O) {
 536   printThumbAddrModeRI5Operand(MI, Op, O, 4);
 537 }
 538
 539 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
 540                                                  raw_ostream &O) {
 541   const MCOperand &MO1 = MI->getOperand(Op);
 542   const MCOperand &MO2 = MI->getOperand(Op+1);
 543   O << "[" << getRegisterName(MO1.getReg());
 544   if (unsigned ImmOffs = MO2.getImm())
 545     O << ", #" << ImmOffs*4;
 546   O << "]";
 547 }
 548
 549 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
 550                                      raw_ostream &O) {
 551   O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
 552   if (MI->getOpcode() == ARM::t2TBH)
 553     O << ", lsl #1";
 554   O << ']';
 555 }
 556
 557 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
 558 // register with shift forms.
 559 // REG 0   0           - e.g. R5
 560 // REG IMM, SH_OPC     - e.g. R5, LSL #3
 561 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
 562                                       raw_ostream &O) {
 563   const MCOperand &MO1 = MI->getOperand(OpNum);
 564   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 565
 566   unsigned Reg = MO1.getReg();
 567   O << getRegisterName(Reg);
 568
 569   // Print the shift opc.
 570   assert(MO2.isImm() && "Not a valid t2_so_reg value!");
 571   ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
 572   O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
 573   if (ShOpc != ARM_AM::rrx)
 574     O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
 575 }
 576
 577 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
 578                                                raw_ostream &O) {
 579   const MCOperand &MO1 = MI->getOperand(OpNum);
 580   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 581
 582   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
 583     printOperand(MI, OpNum, O);
 584     return;
 585   }
 586
 587   O << "[" << getRegisterName(MO1.getReg());
 588
 589   int32_t OffImm = (int32_t)MO2.getImm();
 590   bool isSub = OffImm < 0;
 591   // Special value for #-0. All others are normal.
 592   if (OffImm == INT32_MIN)
 593     OffImm = 0;
 594   if (isSub)
 595     O << ", #-" << -OffImm;
 596   else if (OffImm > 0)
 597     O << ", #" << OffImm;
 598   O << "]";
 599 }
 600
 601 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
 602                                                 unsigned OpNum,
 603                                                 raw_ostream &O) {
 604   const MCOperand &MO1 = MI->getOperand(OpNum);
 605   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 606
 607   O << "[" << getRegisterName(MO1.getReg());
 608
 609   int32_t OffImm = (int32_t)MO2.getImm();
 610   // Don't print +0.
 611   if (OffImm < 0)
 612     O << ", #-" << -OffImm;
 613   else if (OffImm > 0)
 614     O << ", #" << OffImm;
 615   O << "]";
 616 }
 617
 618 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
 619                                                   unsigned OpNum,
 620                                                   raw_ostream &O) {
 621   const MCOperand &MO1 = MI->getOperand(OpNum);
 622   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 623
 624   O << "[" << getRegisterName(MO1.getReg());
 625
 626   int32_t OffImm = (int32_t)MO2.getImm() / 4;
 627   // Don't print +0.
 628   if (OffImm < 0)
 629     O << ", #-" << -OffImm * 4;
 630   else if (OffImm > 0)
 631     O << ", #" << OffImm * 4;
 632   O << "]";
 633 }
 634
 635 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
 636                                                       unsigned OpNum,
 637                                                       raw_ostream &O) {
 638   const MCOperand &MO1 = MI->getOperand(OpNum);
 639   int32_t OffImm = (int32_t)MO1.getImm();
 640   // Don't print +0.
 641   if (OffImm < 0)
 642     O << "#-" << -OffImm;
 643   else if (OffImm > 0)
 644     O << "#" << OffImm;
 645 }
 646
 647 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
 648                                                         unsigned OpNum,
 649                                                         raw_ostream &O) {
 650   const MCOperand &MO1 = MI->getOperand(OpNum);
 651   int32_t OffImm = (int32_t)MO1.getImm() / 4;
 652   // Don't print +0.
 653   if (OffImm < 0)
 654     O << "#-" << -OffImm * 4;
 655   else if (OffImm > 0)
 656     O << "#" << OffImm * 4;
 657 }
 658
 659 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
 660                                                  unsigned OpNum,
 661                                                  raw_ostream &O) {
 662   const MCOperand &MO1 = MI->getOperand(OpNum);
 663   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 664   const MCOperand &MO3 = MI->getOperand(OpNum+2);
 665
 666   O << "[" << getRegisterName(MO1.getReg());
 667
 668   assert(MO2.getReg() && "Invalid so_reg load / store address!");
 669   O << ", " << getRegisterName(MO2.getReg());
 670
 671   unsigned ShAmt = MO3.getImm();
 672   if (ShAmt) {
 673     assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
 674     O << ", lsl #" << ShAmt;
 675   }
 676   O << "]";
 677 }
 678
 679 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
 680                                            raw_ostream &O) {
 681   O << '#' << (float)MI->getOperand(OpNum).getFPImm();
 682 }
 683
 684 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
 685                                            raw_ostream &O) {
 686   O << '#' << MI->getOperand(OpNum).getFPImm();
 687 }
 688
 689 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
 690                                             raw_ostream &O) {
 691   unsigned EncodedImm = MI->getOperand(OpNum).getImm();
 692   unsigned EltBits;
 693   uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
 694   O << "#0x" << utohexstr(Val);
 695 }