lib/Target/ARM/Thumb1InstrInfo.cpp

   1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Thumb1InstrInfo.h"
  15 #include "ARM.h"
  16 #include "ARMGenInstrInfo.inc"
  17 #include "ARMMachineFunctionInfo.h"
  18 #include "llvm/CodeGen/MachineFrameInfo.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/CodeGen/MachineMemOperand.h"
  22 #include "llvm/CodeGen/PseudoSourceValue.h"
  23 #include "llvm/ADT/SmallVector.h"
  24 #include "Thumb1InstrInfo.h"
  25
  26 using namespace llvm;
  27
  28 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
  29   : ARMBaseInstrInfo(STI), RI(*this, STI) {
  30 }
  31
  32 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
  33   return 0;
  34 }
  35
  36 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  37                                   MachineBasicBlock::iterator I, DebugLoc DL,
  38                                   unsigned DestReg, unsigned SrcReg,
  39                                   bool KillSrc) const {
  40   bool tDest = ARM::tGPRRegClass.contains(DestReg);
  41   bool tSrc  = ARM::tGPRRegClass.contains(SrcReg);
  42   unsigned Opc = ARM::tMOVgpr2gpr;
  43   if (tDest && tSrc)
  44     Opc = ARM::tMOVr;
  45   else if (tSrc)
  46     Opc = ARM::tMOVtgpr2gpr;
  47   else if (tDest)
  48     Opc = ARM::tMOVgpr2tgpr;
  49
  50   BuildMI(MBB, I, DL, get(Opc), DestReg)
  51     .addReg(SrcReg, getKillRegState(KillSrc));
  52   assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
  53          "Thumb1 can only copy GPR registers");
  54 }
  55
  56 void Thumb1InstrInfo::
  57 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  58                     unsigned SrcReg, bool isKill, int FI,
  59                     const TargetRegisterClass *RC,
  60                     const TargetRegisterInfo *TRI) const {
  61   assert((RC == ARM::tGPRRegisterClass ||
  62           (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
  63            isARMLowRegister(SrcReg))) && "Unknown regclass!");
  64
  65   if (RC == ARM::tGPRRegisterClass ||
  66       (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
  67        isARMLowRegister(SrcReg))) {
  68     DebugLoc DL;
  69     if (I != MBB.end()) DL = I->getDebugLoc();
  70
  71     MachineFunction &MF = *MBB.getParent();
  72     MachineFrameInfo &MFI = *MF.getFrameInfo();
  73     MachineMemOperand *MMO =
  74       MF.getMachineMemOperand(
  75                     MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
  76                               MachineMemOperand::MOStore,
  77                               MFI.getObjectSize(FI),
  78                               MFI.getObjectAlignment(FI));
  79     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
  80                    .addReg(SrcReg, getKillRegState(isKill))
  81                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
  82   }
  83 }
  84
  85 void Thumb1InstrInfo::
  86 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  87                      unsigned DestReg, int FI,
  88                      const TargetRegisterClass *RC,
  89                      const TargetRegisterInfo *TRI) const {
  90   assert((RC == ARM::tGPRRegisterClass ||
  91           (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
  92            isARMLowRegister(DestReg))) && "Unknown regclass!");
  93
  94   if (RC == ARM::tGPRRegisterClass ||
  95       (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
  96        isARMLowRegister(DestReg))) {
  97     DebugLoc DL;
  98     if (I != MBB.end()) DL = I->getDebugLoc();
  99
 100     MachineFunction &MF = *MBB.getParent();
 101     MachineFrameInfo &MFI = *MF.getFrameInfo();
 102     MachineMemOperand *MMO =
 103       MF.getMachineMemOperand(
 104                     MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
 105                               MachineMemOperand::MOLoad,
 106                               MFI.getObjectSize(FI),
 107                               MFI.getObjectAlignment(FI));
 108     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
 109                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
 110   }
 111 }
 112
 113 bool Thumb1InstrInfo::
 114 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
 115                           MachineBasicBlock::iterator MI,
 116                           const std::vector<CalleeSavedInfo> &CSI,
 117                           const TargetRegisterInfo *TRI) const {
 118   if (CSI.empty())
 119     return false;
 120
 121   DebugLoc DL;
 122   if (MI != MBB.end()) DL = MI->getDebugLoc();
 123
 124   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
 125   AddDefaultPred(MIB);
 126   for (unsigned i = CSI.size(); i != 0; --i) {
 127     unsigned Reg = CSI[i-1].getReg();
 128     bool isKill = true;
 129
 130     // Add the callee-saved register as live-in unless it's LR and
 131     // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
 132     // then it's already added to the function and entry block live-in sets.
 133     if (Reg == ARM::LR) {
 134       MachineFunction &MF = *MBB.getParent();
 135       if (MF.getFrameInfo()->isReturnAddressTaken() &&
 136           MF.getRegInfo().isLiveIn(Reg))
 137         isKill = false;
 138     }
 139
 140     if (isKill)
 141       MBB.addLiveIn(Reg);
 142
 143     MIB.addReg(Reg, getKillRegState(isKill));
 144   }
 145   return true;
 146 }
 147
 148 bool Thumb1InstrInfo::
 149 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
 150                             MachineBasicBlock::iterator MI,
 151                             const std::vector<CalleeSavedInfo> &CSI,
 152                             const TargetRegisterInfo *TRI) const {
 153   MachineFunction &MF = *MBB.getParent();
 154   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
 155   if (CSI.empty())
 156     return false;
 157
 158   bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
 159   DebugLoc DL = MI->getDebugLoc();
 160   MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
 161   AddDefaultPred(MIB);
 162
 163   bool NumRegs = false;
 164   for (unsigned i = CSI.size(); i != 0; --i) {
 165     unsigned Reg = CSI[i-1].getReg();
 166     if (Reg == ARM::LR) {
 167       // Special epilogue for vararg functions. See emitEpilogue
 168       if (isVarArg)
 169         continue;
 170       Reg = ARM::PC;
 171       (*MIB).setDesc(get(ARM::tPOP_RET));
 172       MI = MBB.erase(MI);
 173     }
 174     MIB.addReg(Reg, getDefRegState(true));
 175     NumRegs = true;
 176   }
 177
 178   // It's illegal to emit pop instruction without operands.
 179   if (NumRegs)
 180     MBB.insert(MI, &*MIB);
 181   else
 182     MF.DeleteMachineInstr(MIB);
 183
 184   return true;
 185 }