lib/Target/ARM/Thumb2ITBlockPass.cpp

   1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks ----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #define DEBUG_TYPE "thumb2-it"
  11 #include "ARM.h"
  12 #include "ARMMachineFunctionInfo.h"
  13 #include "Thumb2InstrInfo.h"
  14 #include "llvm/CodeGen/MachineInstr.h"
  15 #include "llvm/CodeGen/MachineInstrBuilder.h"
  16 #include "llvm/CodeGen/MachineFunctionPass.h"
  17 #include "llvm/ADT/SmallSet.h"
  18 #include "llvm/ADT/Statistic.h"
  19 using namespace llvm;
  20
  21 STATISTIC(NumITs,        "Number of IT blocks inserted");
  22 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
  23
  24 namespace {
  25   class Thumb2ITBlockPass : public MachineFunctionPass {
  26     bool PreRegAlloc;
  27
  28   public:
  29     static char ID;
  30     Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
  31
  32     const Thumb2InstrInfo *TII;
  33     const TargetRegisterInfo *TRI;
  34     ARMFunctionInfo *AFI;
  35
  36     virtual bool runOnMachineFunction(MachineFunction &Fn);
  37
  38     virtual const char *getPassName() const {
  39       return "Thumb IT blocks insertion pass";
  40     }
  41
  42   private:
  43     bool MoveCopyOutOfITBlock(MachineInstr *MI,
  44                               ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
  45                               SmallSet<unsigned, 4> &Defs,
  46                               SmallSet<unsigned, 4> &Uses);
  47     bool InsertITInstructions(MachineBasicBlock &MBB);
  48   };
  49   char Thumb2ITBlockPass::ID = 0;
  50 }
  51
  52 /// TrackDefUses - Tracking what registers are being defined and used by
  53 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
  54 /// in the IT block that are defined before the IT instruction.
  55 static void TrackDefUses(MachineInstr *MI,
  56                          SmallSet<unsigned, 4> &Defs,
  57                          SmallSet<unsigned, 4> &Uses,
  58                          const TargetRegisterInfo *TRI) {
  59   SmallVector<unsigned, 4> LocalDefs;
  60   SmallVector<unsigned, 4> LocalUses;
  61
  62   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
  63     MachineOperand &MO = MI->getOperand(i);
  64     if (!MO.isReg())
  65       continue;
  66     unsigned Reg = MO.getReg();
  67     if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
  68       continue;
  69     if (MO.isUse())
  70       LocalUses.push_back(Reg);
  71     else
  72       LocalDefs.push_back(Reg);
  73   }
  74
  75   for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
  76     unsigned Reg = LocalUses[i];
  77     Uses.insert(Reg);
  78     for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
  79          *Subreg; ++Subreg)
  80       Uses.insert(*Subreg);
  81   }
  82
  83   for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
  84     unsigned Reg = LocalDefs[i];
  85     Defs.insert(Reg);
  86     for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
  87          *Subreg; ++Subreg)
  88       Defs.insert(*Subreg);
  89     if (Reg == ARM::CPSR)
  90       continue;
  91   }
  92 }
  93
  94 static bool isCopy(MachineInstr *MI) {
  95   switch (MI->getOpcode()) {
  96   default:
  97     return false;
  98   case ARM::MOVr:
  99   case ARM::MOVr_TC:
 100   case ARM::tMOVr:
 101   case ARM::tMOVgpr2tgpr:
 102   case ARM::tMOVtgpr2gpr:
 103   case ARM::tMOVgpr2gpr:
 104   case ARM::t2MOVr:
 105     return true;
 106   }
 107 }
 108
 109 bool
 110 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
 111                                       ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
 112                                         SmallSet<unsigned, 4> &Defs,
 113                                         SmallSet<unsigned, 4> &Uses) {
 114   if (!isCopy(MI))
 115     return false;
 116   // llvm models select's as two-address instructions. That means a copy
 117   // is inserted before a t2MOVccr, etc. If the copy is scheduled in
 118   // between selects we would end up creating multiple IT blocks.
 119   assert(MI->getOperand(0).getSubReg() == 0 &&
 120          MI->getOperand(1).getSubReg() == 0 &&
 121          "Sub-register indices still around?");
 122
 123   unsigned DstReg = MI->getOperand(0).getReg();
 124   unsigned SrcReg = MI->getOperand(1).getReg();
 125
 126   // First check if it's safe to move it.
 127   if (Uses.count(DstReg) || Defs.count(SrcReg))
 128     return false;
 129
 130   // Then peek at the next instruction to see if it's predicated on CC or OCC.
 131   // If not, then there is nothing to be gained by moving the copy.
 132   MachineBasicBlock::iterator I = MI; ++I;
 133   MachineBasicBlock::iterator E = MI->getParent()->end();
 134   while (I != E && I->isDebugValue())
 135     ++I;
 136   if (I != E) {
 137     unsigned NPredReg = 0;
 138     ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg);
 139     if (NCC == CC || NCC == OCC)
 140       return true;
 141   }
 142   return false;
 143 }
 144
 145 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
 146   bool Modified = false;
 147
 148   SmallSet<unsigned, 4> Defs;
 149   SmallSet<unsigned, 4> Uses;
 150   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
 151   while (MBBI != E) {
 152     MachineInstr *MI = &*MBBI;
 153     DebugLoc dl = MI->getDebugLoc();
 154     unsigned PredReg = 0;
 155     ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
 156     if (CC == ARMCC::AL) {
 157       ++MBBI;
 158       continue;
 159     }
 160
 161     Defs.clear();
 162     Uses.clear();
 163     TrackDefUses(MI, Defs, Uses, TRI);
 164
 165     // Insert an IT instruction.
 166     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
 167       .addImm(CC);
 168
 169     // Add implicit use of ITSTATE to IT block instructions.
 170     MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
 171                                              true/*isImp*/, false/*isKill*/));
 172
 173     MachineInstr *LastITMI = MI;
 174     MachineBasicBlock::iterator InsertPos = MIB;
 175     ++MBBI;
 176
 177     // Form IT block.
 178     ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
 179     unsigned Mask = 0, Pos = 3;
 180     // Branches, including tricky ones like LDM_RET, need to end an IT
 181     // block so check the instruction we just put in the block.
 182     for (; MBBI != E && Pos &&
 183            (!MI->getDesc().isBranch() && !MI->getDesc().isReturn()) ; ++MBBI) {
 184       if (MBBI->isDebugValue())
 185         continue;
 186
 187       MachineInstr *NMI = &*MBBI;
 188       MI = NMI;
 189
 190       unsigned NPredReg = 0;
 191       ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
 192       if (NCC == CC || NCC == OCC) {
 193         Mask |= (NCC & 1) << Pos;
 194         // Add implicit use of ITSTATE.
 195         NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
 196                                                true/*isImp*/, false/*isKill*/));
 197         LastITMI = NMI;
 198       } else {
 199         if (NCC == ARMCC::AL &&
 200             MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
 201           --MBBI;
 202           MBB.remove(NMI);
 203           MBB.insert(InsertPos, NMI);
 204           ++NumMovedInsts;
 205           continue;
 206         }
 207         break;
 208       }
 209       TrackDefUses(NMI, Defs, Uses, TRI);
 210       --Pos;
 211     }
 212
 213     // Finalize IT mask.
 214     Mask |= (1 << Pos);
 215     // Tag along (firstcond[0] << 4) with the mask.
 216     Mask |= (CC & 1) << 4;
 217     MIB.addImm(Mask);
 218
 219     // Last instruction in IT block kills ITSTATE.
 220     LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
 221
 222     Modified = true;
 223     ++NumITs;
 224   }
 225
 226   return Modified;
 227 }
 228
 229 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
 230   const TargetMachine &TM = Fn.getTarget();
 231   AFI = Fn.getInfo<ARMFunctionInfo>();
 232   TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
 233   TRI = TM.getRegisterInfo();
 234
 235   if (!AFI->isThumbFunction())
 236     return false;
 237
 238   bool Modified = false;
 239   for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
 240     MachineBasicBlock &MBB = *MFI;
 241     ++MFI;
 242     Modified |= InsertITInstructions(MBB);
 243   }
 244
 245   if (Modified)
 246     AFI->setHasITBlocks(true);
 247
 248   return Modified;
 249 }
 250
 251 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
 252 /// insertion pass.
 253 FunctionPass *llvm::createThumb2ITBlockPass() {
 254   return new Thumb2ITBlockPass();
 255 }