lib/Target/ARM/Thumb2InstrInfo.cpp

   1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Thumb2InstrInfo.h"
  15 #include "ARM.h"
  16 #include "ARMConstantPoolValue.h"
  17 #include "ARMAddressingModes.h"
  18 #include "ARMGenInstrInfo.inc"
  19 #include "ARMMachineFunctionInfo.h"
  20 #include "Thumb2HazardRecognizer.h"
  21 #include "Thumb2InstrInfo.h"
  22 #include "llvm/CodeGen/MachineFrameInfo.h"
  23 #include "llvm/CodeGen/MachineInstrBuilder.h"
  24 #include "llvm/CodeGen/MachineMemOperand.h"
  25 #include "llvm/CodeGen/PseudoSourceValue.h"
  26 #include "llvm/ADT/SmallVector.h"
  27 #include "llvm/Support/CommandLine.h"
  28
  29 using namespace llvm;
  30
  31 static cl::opt<bool>
  32 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
  33            cl::desc("Use old-style Thumb2 if-conversion heuristics"),
  34            cl::init(false));
  35
  36 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
  37   : ARMBaseInstrInfo(STI), RI(*this, STI) {
  38 }
  39
  40 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
  41   // FIXME
  42   return 0;
  43 }
  44
  45 void
  46 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
  47                                          MachineBasicBlock *NewDest) const {
  48   MachineBasicBlock *MBB = Tail->getParent();
  49   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
  50   if (!AFI->hasITBlocks()) {
  51     TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
  52     return;
  53   }
  54
  55   // If the first instruction of Tail is predicated, we may have to update
  56   // the IT instruction.
  57   unsigned PredReg = 0;
  58   ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
  59   MachineBasicBlock::iterator MBBI = Tail;
  60   if (CC != ARMCC::AL)
  61     // Expecting at least the t2IT instruction before it.
  62     --MBBI;
  63
  64   // Actually replace the tail.
  65   TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
  66
  67   // Fix up IT.
  68   if (CC != ARMCC::AL) {
  69     MachineBasicBlock::iterator E = MBB->begin();
  70     unsigned Count = 4; // At most 4 instructions in an IT block.
  71     while (Count && MBBI != E) {
  72       if (MBBI->isDebugValue()) {
  73         --MBBI;
  74         continue;
  75       }
  76       if (MBBI->getOpcode() == ARM::t2IT) {
  77         unsigned Mask = MBBI->getOperand(1).getImm();
  78         if (Count == 4)
  79           MBBI->eraseFromParent();
  80         else {
  81           unsigned MaskOn = 1 << Count;
  82           unsigned MaskOff = ~(MaskOn - 1);
  83           MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
  84         }
  85         return;
  86       }
  87       --MBBI;
  88       --Count;
  89     }
  90
  91     // Ctrl flow can reach here if branch folding is run before IT block
  92     // formation pass.
  93   }
  94 }
  95
  96 bool
  97 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
  98                                      MachineBasicBlock::iterator MBBI) const {
  99   unsigned PredReg = 0;
 100   return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
 101 }
 102
 103 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 104                                   MachineBasicBlock::iterator I, DebugLoc DL,
 105                                   unsigned DestReg, unsigned SrcReg,
 106                                   bool KillSrc) const {
 107   // Handle SPR, DPR, and QPR copies.
 108   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
 109     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
 110
 111   bool tDest = ARM::tGPRRegClass.contains(DestReg);
 112   bool tSrc  = ARM::tGPRRegClass.contains(SrcReg);
 113   unsigned Opc = ARM::tMOVgpr2gpr;
 114   if (tDest && tSrc)
 115     Opc = ARM::tMOVr;
 116   else if (tSrc)
 117     Opc = ARM::tMOVtgpr2gpr;
 118   else if (tDest)
 119     Opc = ARM::tMOVgpr2tgpr;
 120
 121   BuildMI(MBB, I, DL, get(Opc), DestReg)
 122     .addReg(SrcReg, getKillRegState(KillSrc));
 123 }
 124
 125 void Thumb2InstrInfo::
 126 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 127                     unsigned SrcReg, bool isKill, int FI,
 128                     const TargetRegisterClass *RC,
 129                     const TargetRegisterInfo *TRI) const {
 130   if (RC == ARM::GPRRegisterClass   || RC == ARM::tGPRRegisterClass ||
 131       RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
 132     DebugLoc DL;
 133     if (I != MBB.end()) DL = I->getDebugLoc();
 134
 135     MachineFunction &MF = *MBB.getParent();
 136     MachineFrameInfo &MFI = *MF.getFrameInfo();
 137     MachineMemOperand *MMO =
 138       MF.getMachineMemOperand(
 139                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
 140                               MachineMemOperand::MOStore,
 141                               MFI.getObjectSize(FI),
 142                               MFI.getObjectAlignment(FI));
 143     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
 144                    .addReg(SrcReg, getKillRegState(isKill))
 145                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
 146     return;
 147   }
 148
 149   ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
 150 }
 151
 152 void Thumb2InstrInfo::
 153 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 154                      unsigned DestReg, int FI,
 155                      const TargetRegisterClass *RC,
 156                      const TargetRegisterInfo *TRI) const {
 157   if (RC == ARM::GPRRegisterClass   || RC == ARM::tGPRRegisterClass ||
 158       RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
 159     DebugLoc DL;
 160     if (I != MBB.end()) DL = I->getDebugLoc();
 161
 162     MachineFunction &MF = *MBB.getParent();
 163     MachineFrameInfo &MFI = *MF.getFrameInfo();
 164     MachineMemOperand *MMO =
 165       MF.getMachineMemOperand(
 166                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
 167                               MachineMemOperand::MOLoad,
 168                               MFI.getObjectSize(FI),
 169                               MFI.getObjectAlignment(FI));
 170     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
 171                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
 172     return;
 173   }
 174
 175   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
 176 }
 177
 178 ScheduleHazardRecognizer *Thumb2InstrInfo::
 179 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II) const {
 180   return (ScheduleHazardRecognizer *)new Thumb2HazardRecognizer(II);
 181 }
 182
 183 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
 184                                MachineBasicBlock::iterator &MBBI, DebugLoc dl,
 185                                unsigned DestReg, unsigned BaseReg, int NumBytes,
 186                                ARMCC::CondCodes Pred, unsigned PredReg,
 187                                const ARMBaseInstrInfo &TII) {
 188   bool isSub = NumBytes < 0;
 189   if (isSub) NumBytes = -NumBytes;
 190
 191   // If profitable, use a movw or movt to materialize the offset.
 192   // FIXME: Use the scavenger to grab a scratch register.
 193   if (DestReg != ARM::SP && DestReg != BaseReg &&
 194       NumBytes >= 4096 &&
 195       ARM_AM::getT2SOImmVal(NumBytes) == -1) {
 196     bool Fits = false;
 197     if (NumBytes < 65536) {
 198       // Use a movw to materialize the 16-bit constant.
 199       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
 200         .addImm(NumBytes)
 201         .addImm((unsigned)Pred).addReg(PredReg);
 202       Fits = true;
 203     } else if ((NumBytes & 0xffff) == 0) {
 204       // Use a movt to materialize the 32-bit constant.
 205       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
 206         .addReg(DestReg)
 207         .addImm(NumBytes >> 16)
 208         .addImm((unsigned)Pred).addReg(PredReg);
 209       Fits = true;
 210     }
 211
 212     if (Fits) {
 213       if (isSub) {
 214         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
 215           .addReg(BaseReg, RegState::Kill)
 216           .addReg(DestReg, RegState::Kill)
 217           .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
 218       } else {
 219         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
 220           .addReg(DestReg, RegState::Kill)
 221           .addReg(BaseReg, RegState::Kill)
 222         .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
 223       }
 224       return;
 225     }
 226   }
 227
 228   while (NumBytes) {
 229     unsigned ThisVal = NumBytes;
 230     unsigned Opc = 0;
 231     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
 232       // mov sp, rn. Note t2MOVr cannot be used.
 233       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
 234       BaseReg = ARM::SP;
 235       continue;
 236     }
 237
 238     bool HasCCOut = true;
 239     if (BaseReg == ARM::SP) {
 240       // sub sp, sp, #imm7
 241       if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
 242         assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
 243         Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
 244         // FIXME: Fix Thumb1 immediate encoding.
 245         BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
 246           .addReg(BaseReg).addImm(ThisVal/4);
 247         NumBytes = 0;
 248         continue;
 249       }
 250
 251       // sub rd, sp, so_imm
 252       Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
 253       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
 254         NumBytes = 0;
 255       } else {
 256         // FIXME: Move this to ARMAddressingModes.h?
 257         unsigned RotAmt = CountLeadingZeros_32(ThisVal);
 258         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
 259         NumBytes &= ~ThisVal;
 260         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
 261                "Bit extraction didn't work?");
 262       }
 263     } else {
 264       assert(DestReg != ARM::SP && BaseReg != ARM::SP);
 265       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
 266       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
 267         NumBytes = 0;
 268       } else if (ThisVal < 4096) {
 269         Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
 270         HasCCOut = false;
 271         NumBytes = 0;
 272       } else {
 273         // FIXME: Move this to ARMAddressingModes.h?
 274         unsigned RotAmt = CountLeadingZeros_32(ThisVal);
 275         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
 276         NumBytes &= ~ThisVal;
 277         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
 278                "Bit extraction didn't work?");
 279       }
 280     }
 281
 282     // Build the new ADD / SUB.
 283     MachineInstrBuilder MIB =
 284       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
 285                      .addReg(BaseReg, RegState::Kill)
 286                      .addImm(ThisVal));
 287     if (HasCCOut)
 288       AddDefaultCC(MIB);
 289
 290     BaseReg = DestReg;
 291   }
 292 }
 293
 294 static unsigned
 295 negativeOffsetOpcode(unsigned opcode)
 296 {
 297   switch (opcode) {
 298   case ARM::t2LDRi12:   return ARM::t2LDRi8;
 299   case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
 300   case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
 301   case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
 302   case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
 303   case ARM::t2STRi12:   return ARM::t2STRi8;
 304   case ARM::t2STRBi12:  return ARM::t2STRBi8;
 305   case ARM::t2STRHi12:  return ARM::t2STRHi8;
 306
 307   case ARM::t2LDRi8:
 308   case ARM::t2LDRHi8:
 309   case ARM::t2LDRBi8:
 310   case ARM::t2LDRSHi8:
 311   case ARM::t2LDRSBi8:
 312   case ARM::t2STRi8:
 313   case ARM::t2STRBi8:
 314   case ARM::t2STRHi8:
 315     return opcode;
 316
 317   default:
 318     break;
 319   }
 320
 321   return 0;
 322 }
 323
 324 static unsigned
 325 positiveOffsetOpcode(unsigned opcode)
 326 {
 327   switch (opcode) {
 328   case ARM::t2LDRi8:   return ARM::t2LDRi12;
 329   case ARM::t2LDRHi8:  return ARM::t2LDRHi12;
 330   case ARM::t2LDRBi8:  return ARM::t2LDRBi12;
 331   case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
 332   case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
 333   case ARM::t2STRi8:   return ARM::t2STRi12;
 334   case ARM::t2STRBi8:  return ARM::t2STRBi12;
 335   case ARM::t2STRHi8:  return ARM::t2STRHi12;
 336
 337   case ARM::t2LDRi12:
 338   case ARM::t2LDRHi12:
 339   case ARM::t2LDRBi12:
 340   case ARM::t2LDRSHi12:
 341   case ARM::t2LDRSBi12:
 342   case ARM::t2STRi12:
 343   case ARM::t2STRBi12:
 344   case ARM::t2STRHi12:
 345     return opcode;
 346
 347   default:
 348     break;
 349   }
 350
 351   return 0;
 352 }
 353
 354 static unsigned
 355 immediateOffsetOpcode(unsigned opcode)
 356 {
 357   switch (opcode) {
 358   case ARM::t2LDRs:   return ARM::t2LDRi12;
 359   case ARM::t2LDRHs:  return ARM::t2LDRHi12;
 360   case ARM::t2LDRBs:  return ARM::t2LDRBi12;
 361   case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
 362   case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
 363   case ARM::t2STRs:   return ARM::t2STRi12;
 364   case ARM::t2STRBs:  return ARM::t2STRBi12;
 365   case ARM::t2STRHs:  return ARM::t2STRHi12;
 366
 367   case ARM::t2LDRi12:
 368   case ARM::t2LDRHi12:
 369   case ARM::t2LDRBi12:
 370   case ARM::t2LDRSHi12:
 371   case ARM::t2LDRSBi12:
 372   case ARM::t2STRi12:
 373   case ARM::t2STRBi12:
 374   case ARM::t2STRHi12:
 375   case ARM::t2LDRi8:
 376   case ARM::t2LDRHi8:
 377   case ARM::t2LDRBi8:
 378   case ARM::t2LDRSHi8:
 379   case ARM::t2LDRSBi8:
 380   case ARM::t2STRi8:
 381   case ARM::t2STRBi8:
 382   case ARM::t2STRHi8:
 383     return opcode;
 384
 385   default:
 386     break;
 387   }
 388
 389   return 0;
 390 }
 391
 392 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
 393                                unsigned FrameReg, int &Offset,
 394                                const ARMBaseInstrInfo &TII) {
 395   unsigned Opcode = MI.getOpcode();
 396   const TargetInstrDesc &Desc = MI.getDesc();
 397   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
 398   bool isSub = false;
 399
 400   // Memory operands in inline assembly always use AddrModeT2_i12.
 401   if (Opcode == ARM::INLINEASM)
 402     AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
 403
 404   if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
 405     Offset += MI.getOperand(FrameRegIdx+1).getImm();
 406
 407     unsigned PredReg;
 408     if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
 409       // Turn it into a move.
 410       MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
 411       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
 412       // Remove offset and remaining explicit predicate operands.
 413       do MI.RemoveOperand(FrameRegIdx+1);
 414       while (MI.getNumOperands() > FrameRegIdx+1 &&
 415              (!MI.getOperand(FrameRegIdx+1).isReg() ||
 416               !MI.getOperand(FrameRegIdx+1).isImm()));
 417       return true;
 418     }
 419
 420     bool isSP = FrameReg == ARM::SP;
 421     bool HasCCOut = Opcode != ARM::t2ADDri12;
 422
 423     if (Offset < 0) {
 424       Offset = -Offset;
 425       isSub = true;
 426       MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
 427     } else {
 428       MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
 429     }
 430
 431     // Common case: small offset, fits into instruction.
 432     if (ARM_AM::getT2SOImmVal(Offset) != -1) {
 433       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
 434       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
 435       // Add cc_out operand if the original instruction did not have one.
 436       if (!HasCCOut)
 437         MI.addOperand(MachineOperand::CreateReg(0, false));
 438       Offset = 0;
 439       return true;
 440     }
 441     // Another common case: imm12.
 442     if (Offset < 4096 &&
 443         (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
 444       unsigned NewOpc = isSP
 445         ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
 446         : (isSub ? ARM::t2SUBri12   : ARM::t2ADDri12);
 447       MI.setDesc(TII.get(NewOpc));
 448       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
 449       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
 450       // Remove the cc_out operand.
 451       if (HasCCOut)
 452         MI.RemoveOperand(MI.getNumOperands()-1);
 453       Offset = 0;
 454       return true;
 455     }
 456
 457     // Otherwise, extract 8 adjacent bits from the immediate into this
 458     // t2ADDri/t2SUBri.
 459     unsigned RotAmt = CountLeadingZeros_32(Offset);
 460     unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
 461
 462     // We will handle these bits from offset, clear them.
 463     Offset &= ~ThisImmVal;
 464
 465     assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
 466            "Bit extraction didn't work?");
 467     MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
 468     // Add cc_out operand if the original instruction did not have one.
 469     if (!HasCCOut)
 470       MI.addOperand(MachineOperand::CreateReg(0, false));
 471
 472   } else {
 473
 474     // AddrMode4 and AddrMode6 cannot handle any offset.
 475     if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
 476       return false;
 477
 478     // AddrModeT2_so cannot handle any offset. If there is no offset
 479     // register then we change to an immediate version.
 480     unsigned NewOpc = Opcode;
 481     if (AddrMode == ARMII::AddrModeT2_so) {
 482       unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
 483       if (OffsetReg != 0) {
 484         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
 485         return Offset == 0;
 486       }
 487
 488       MI.RemoveOperand(FrameRegIdx+1);
 489       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
 490       NewOpc = immediateOffsetOpcode(Opcode);
 491       AddrMode = ARMII::AddrModeT2_i12;
 492     }
 493
 494     unsigned NumBits = 0;
 495     unsigned Scale = 1;
 496     if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
 497       // i8 supports only negative, and i12 supports only positive, so
 498       // based on Offset sign convert Opcode to the appropriate
 499       // instruction
 500       Offset += MI.getOperand(FrameRegIdx+1).getImm();
 501       if (Offset < 0) {
 502         NewOpc = negativeOffsetOpcode(Opcode);
 503         NumBits = 8;
 504         isSub = true;
 505         Offset = -Offset;
 506       } else {
 507         NewOpc = positiveOffsetOpcode(Opcode);
 508         NumBits = 12;
 509       }
 510     } else if (AddrMode == ARMII::AddrMode5) {
 511       // VFP address mode.
 512       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
 513       int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
 514       if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
 515         InstrOffs *= -1;
 516       NumBits = 8;
 517       Scale = 4;
 518       Offset += InstrOffs * 4;
 519       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
 520       if (Offset < 0) {
 521         Offset = -Offset;
 522         isSub = true;
 523       }
 524     } else {
 525       llvm_unreachable("Unsupported addressing mode!");
 526     }
 527
 528     if (NewOpc != Opcode)
 529       MI.setDesc(TII.get(NewOpc));
 530
 531     MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
 532
 533     // Attempt to fold address computation
 534     // Common case: small offset, fits into instruction.
 535     int ImmedOffset = Offset / Scale;
 536     unsigned Mask = (1 << NumBits) - 1;
 537     if ((unsigned)Offset <= Mask * Scale) {
 538       // Replace the FrameIndex with fp/sp
 539       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
 540       if (isSub) {
 541         if (AddrMode == ARMII::AddrMode5)
 542           // FIXME: Not consistent.
 543           ImmedOffset |= 1 << NumBits;
 544         else
 545           ImmedOffset = -ImmedOffset;
 546       }
 547       ImmOp.ChangeToImmediate(ImmedOffset);
 548       Offset = 0;
 549       return true;
 550     }
 551
 552     // Otherwise, offset doesn't fit. Pull in what we can to simplify
 553     ImmedOffset = ImmedOffset & Mask;
 554     if (isSub) {
 555       if (AddrMode == ARMII::AddrMode5)
 556         // FIXME: Not consistent.
 557         ImmedOffset |= 1 << NumBits;
 558       else {
 559         ImmedOffset = -ImmedOffset;
 560         if (ImmedOffset == 0)
 561           // Change the opcode back if the encoded offset is zero.
 562           MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
 563       }
 564     }
 565     ImmOp.ChangeToImmediate(ImmedOffset);
 566     Offset &= ~(Mask*Scale);
 567   }
 568
 569   Offset = (isSub) ? -Offset : Offset;
 570   return Offset == 0;
 571 }
 572
 573 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
 574 /// two-addrss instruction inserted by two-address pass.
 575 void
 576 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
 577                                        MachineInstr *UseMI,
 578                                        const TargetRegisterInfo &TRI) const {
 579   if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
 580       SrcMI->getOperand(1).isKill())
 581     return;
 582
 583   unsigned PredReg = 0;
 584   ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
 585   if (CC == ARMCC::AL || PredReg != ARM::CPSR)
 586     return;
 587
 588   // Schedule the copy so it doesn't come between previous instructions
 589   // and UseMI which can form an IT block.
 590   unsigned SrcReg = SrcMI->getOperand(1).getReg();
 591   ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
 592   MachineBasicBlock *MBB = UseMI->getParent();
 593   MachineBasicBlock::iterator MBBI = SrcMI;
 594   unsigned NumInsts = 0;
 595   while (--MBBI != MBB->begin()) {
 596     if (MBBI->isDebugValue())
 597       continue;
 598
 599     MachineInstr *NMI = &*MBBI;
 600     ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
 601     if (!(NCC == CC || NCC == OCC) ||
 602         NMI->modifiesRegister(SrcReg, &TRI) ||
 603         NMI->definesRegister(ARM::CPSR))
 604       break;
 605     if (++NumInsts == 4)
 606       // Too many in a row!
 607       return;
 608   }
 609
 610   if (NumInsts) {
 611     MBB->remove(SrcMI);
 612     MBB->insert(++MBBI, SrcMI);
 613   }
 614 }
 615
 616 ARMCC::CondCodes
 617 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
 618   unsigned Opc = MI->getOpcode();
 619   if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
 620     return ARMCC::AL;
 621   return llvm::getInstrPredicate(MI, PredReg);
 622 }