lib/Target/Blackfin/BlackfinISelLowering.cpp

   1 //===- BlackfinISelLowering.cpp - Blackfin DAG Lowering Implementation ----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the interfaces that Blackfin uses to lower LLVM code
  11 // into a selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "BlackfinISelLowering.h"
  16 #include "BlackfinTargetMachine.h"
  17 #include "llvm/Function.h"
  18 #include "llvm/Type.h"
  19 #include "llvm/CodeGen/CallingConvLower.h"
  20 #include "llvm/CodeGen/MachineFrameInfo.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/CodeGen/PseudoSourceValue.h"
  25 #include "llvm/CodeGen/SelectionDAG.h"
  26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
  27 #include "llvm/ADT/VectorExtras.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 using namespace llvm;
  31
  32 //===----------------------------------------------------------------------===//
  33 // Calling Convention Implementation
  34 //===----------------------------------------------------------------------===//
  35
  36 #include "BlackfinGenCallingConv.inc"
  37
  38 //===----------------------------------------------------------------------===//
  39 // TargetLowering Implementation
  40 //===----------------------------------------------------------------------===//
  41
  42 BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
  43   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
  44   setShiftAmountType(MVT::i16);
  45   setBooleanContents(ZeroOrOneBooleanContent);
  46   setStackPointerRegisterToSaveRestore(BF::SP);
  47   setIntDivIsCheap(false);
  48
  49   // Set up the legal register classes.
  50   addRegisterClass(MVT::i32, BF::DRegisterClass);
  51   addRegisterClass(MVT::i16, BF::D16RegisterClass);
  52
  53   computeRegisterProperties();
  54
  55   // Blackfin doesn't have i1 loads or stores
  56   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
  57   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
  58   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
  59
  60   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
  61   setOperationAction(ISD::JumpTable,     MVT::i32, Custom);
  62
  63   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
  64   setOperationAction(ISD::BR_JT,     MVT::Other, Expand);
  65   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
  66
  67   // i16 registers don't do much
  68   setOperationAction(ISD::AND,   MVT::i16, Promote);
  69   setOperationAction(ISD::OR,    MVT::i16, Promote);
  70   setOperationAction(ISD::XOR,   MVT::i16, Promote);
  71   setOperationAction(ISD::CTPOP, MVT::i16, Promote);
  72   // The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
  73   // immediately.
  74   setOperationAction(ISD::CTLZ,  MVT::i16, Promote);
  75   setOperationAction(ISD::CTTZ,  MVT::i16, Promote);
  76   setOperationAction(ISD::SETCC, MVT::i16, Promote);
  77
  78   // Blackfin has no division
  79   setOperationAction(ISD::SDIV,    MVT::i16, Expand);
  80   setOperationAction(ISD::SDIV,    MVT::i32, Expand);
  81   setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
  82   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
  83   setOperationAction(ISD::SREM,    MVT::i16, Expand);
  84   setOperationAction(ISD::SREM,    MVT::i32, Expand);
  85   setOperationAction(ISD::UDIV,    MVT::i16, Expand);
  86   setOperationAction(ISD::UDIV,    MVT::i32, Expand);
  87   setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
  88   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
  89   setOperationAction(ISD::UREM,    MVT::i16, Expand);
  90   setOperationAction(ISD::UREM,    MVT::i32, Expand);
  91
  92   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
  93   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
  94   setOperationAction(ISD::MULHU,     MVT::i32, Expand);
  95   setOperationAction(ISD::MULHS,     MVT::i32, Expand);
  96
  97   // No carry-in operations.
  98   setOperationAction(ISD::ADDE, MVT::i32, Custom);
  99   setOperationAction(ISD::SUBE, MVT::i32, Custom);
 100
 101   // Blackfin has no intrinsics for these particular operations.
 102   setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
 103   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
 104
 105   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
 106   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
 107   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
 108
 109   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 110
 111   // i32 has native CTPOP, but not CTLZ/CTTZ
 112   setOperationAction(ISD::CTLZ, MVT::i32, Expand);
 113   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
 114
 115   // READCYCLECOUNTER needs special type legalization.
 116   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
 117
 118   setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
 119
 120   // Use the default implementation.
 121   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
 122   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 123   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
 124   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
 125 }
 126
 127 const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
 128   switch (Opcode) {
 129   default: return 0;
 130   case BFISD::CALL:     return "BFISD::CALL";
 131   case BFISD::RET_FLAG: return "BFISD::RET_FLAG";
 132   case BFISD::Wrapper:  return "BFISD::Wrapper";
 133   }
 134 }
 135
 136 MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
 137   // SETCC always sets the CC register. Technically that is an i1 register, but
 138   // that type is not legal, so we treat it as an i32 register.
 139   return MVT::i32;
 140 }
 141
 142 SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
 143                                                    SelectionDAG &DAG) const {
 144   DebugLoc DL = Op.getDebugLoc();
 145   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
 146
 147   Op = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
 148   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
 149 }
 150
 151 SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op,
 152                                                SelectionDAG &DAG) const {
 153   DebugLoc DL = Op.getDebugLoc();
 154   int JTI = cast<JumpTableSDNode>(Op)->getIndex();
 155
 156   Op = DAG.getTargetJumpTable(JTI, MVT::i32);
 157   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
 158 }
 159
 160 SDValue
 161 BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
 162                                              CallingConv::ID CallConv, bool isVarArg,
 163                                             const SmallVectorImpl<ISD::InputArg>
 164                                                &Ins,
 165                                              DebugLoc dl, SelectionDAG &DAG,
 166                                              SmallVectorImpl<SDValue> &InVals)
 167                                                const {
 168
 169   MachineFunction &MF = DAG.getMachineFunction();
 170   MachineFrameInfo *MFI = MF.getFrameInfo();
 171
 172   SmallVector<CCValAssign, 16> ArgLocs;
 173   CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
 174                  ArgLocs, *DAG.getContext());
 175   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
 176   CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
 177
 178   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 179     CCValAssign &VA = ArgLocs[i];
 180
 181     if (VA.isRegLoc()) {
 182       EVT RegVT = VA.getLocVT();
 183       TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
 184         BF::PRegisterClass : BF::DRegisterClass;
 185       assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
 186       assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
 187
 188       unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
 189       MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
 190       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
 191
 192       // If this is an 8 or 16-bit value, it is really passed promoted to 32
 193       // bits.  Insert an assert[sz]ext to capture this, then truncate to the
 194       // right size.
 195       if (VA.getLocInfo() == CCValAssign::SExt)
 196         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
 197                                DAG.getValueType(VA.getValVT()));
 198       else if (VA.getLocInfo() == CCValAssign::ZExt)
 199         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
 200                                DAG.getValueType(VA.getValVT()));
 201
 202       if (VA.getLocInfo() != CCValAssign::Full)
 203         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
 204
 205       InVals.push_back(ArgValue);
 206     } else {
 207       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
 208       unsigned ObjSize = VA.getLocVT().getStoreSize();
 209       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
 210       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
 211       InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
 212                                    MachinePointerInfo(),
 213                                    false, false, 0));
 214     }
 215   }
 216
 217   return Chain;
 218 }
 219
 220 SDValue
 221 BlackfinTargetLowering::LowerReturn(SDValue Chain,
 222                                     CallingConv::ID CallConv, bool isVarArg,
 223                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
 224                                     const SmallVectorImpl<SDValue> &OutVals,
 225                                     DebugLoc dl, SelectionDAG &DAG) const {
 226
 227   // CCValAssign - represent the assignment of the return value to locations.
 228   SmallVector<CCValAssign, 16> RVLocs;
 229
 230   // CCState - Info about the registers and stack slot.
 231   CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
 232                  RVLocs, *DAG.getContext());
 233
 234   // Analize return values.
 235   CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
 236
 237   // If this is the first return lowered for this function, add the regs to the
 238   // liveout set for the function.
 239   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
 240     for (unsigned i = 0; i != RVLocs.size(); ++i)
 241       DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
 242   }
 243
 244   SDValue Flag;
 245
 246   // Copy the result values into the output registers.
 247   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 248     CCValAssign &VA = RVLocs[i];
 249     assert(VA.isRegLoc() && "Can only return in registers!");
 250     SDValue Opi = OutVals[i];
 251
 252     // Expand to i32 if necessary
 253     switch (VA.getLocInfo()) {
 254     default: llvm_unreachable("Unknown loc info!");
 255     case CCValAssign::Full: break;
 256     case CCValAssign::SExt:
 257       Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
 258       break;
 259     case CCValAssign::ZExt:
 260       Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi);
 261       break;
 262     case CCValAssign::AExt:
 263       Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
 264       break;
 265     }
 266     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
 267     // Guarantee that all emitted copies are stuck together with flags.
 268     Flag = Chain.getValue(1);
 269   }
 270
 271   if (Flag.getNode()) {
 272     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
 273   } else {
 274     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
 275   }
 276 }
 277
 278 SDValue
 279 BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
 280                                   CallingConv::ID CallConv, bool isVarArg,
 281                                   bool &isTailCall,
 282                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 283                                   const SmallVectorImpl<SDValue> &OutVals,
 284                                   const SmallVectorImpl<ISD::InputArg> &Ins,
 285                                   DebugLoc dl, SelectionDAG &DAG,
 286                                   SmallVectorImpl<SDValue> &InVals) const {
 287   // Blackfin target does not yet support tail call optimization.
 288   isTailCall = false;
 289
 290   // Analyze operands of the call, assigning locations to each operand.
 291   SmallVector<CCValAssign, 16> ArgLocs;
 292   CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
 293                  *DAG.getContext());
 294   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
 295   CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
 296
 297   // Get the size of the outgoing arguments stack space requirement.
 298   unsigned ArgsSize = CCInfo.getNextStackOffset();
 299
 300   Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
 301   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
 302   SmallVector<SDValue, 8> MemOpChains;
 303
 304   // Walk the register/memloc assignments, inserting copies/loads.
 305   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 306     CCValAssign &VA = ArgLocs[i];
 307     SDValue Arg = OutVals[i];
 308
 309     // Promote the value if needed.
 310     switch (VA.getLocInfo()) {
 311     default: llvm_unreachable("Unknown loc info!");
 312     case CCValAssign::Full: break;
 313     case CCValAssign::SExt:
 314       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
 315       break;
 316     case CCValAssign::ZExt:
 317       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
 318       break;
 319     case CCValAssign::AExt:
 320       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
 321       break;
 322     }
 323
 324     // Arguments that can be passed on register must be kept at
 325     // RegsToPass vector
 326     if (VA.isRegLoc()) {
 327       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
 328     } else {
 329       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
 330       int Offset = VA.getLocMemOffset();
 331       assert(Offset%4 == 0 && "Unaligned LocMemOffset");
 332       assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
 333       SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
 334       SDValue OffsetN = DAG.getIntPtrConstant(Offset);
 335       OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
 336       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
 337                                          MachinePointerInfo(),false, false, 0));
 338     }
 339   }
 340
 341   // Transform all store nodes into one single node because
 342   // all store nodes are independent of each other.
 343   if (!MemOpChains.empty())
 344     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
 345                         &MemOpChains[0], MemOpChains.size());
 346
 347   // Build a sequence of copy-to-reg nodes chained together with token
 348   // chain and flag operands which copy the outgoing args into registers.
 349   // The InFlag in necessary since all emited instructions must be
 350   // stuck together.
 351   SDValue InFlag;
 352   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
 353     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
 354                              RegsToPass[i].second, InFlag);
 355     InFlag = Chain.getValue(1);
 356   }
 357
 358   // If the callee is a GlobalAddress node (quite common, every direct call is)
 359   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
 360   // Likewise ExternalSymbol -> TargetExternalSymbol.
 361   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
 362     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
 363   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
 364     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
 365
 366   std::vector<EVT> NodeTys;
 367   NodeTys.push_back(MVT::Other);   // Returns a chain
 368   NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
 369   SDValue Ops[] = { Chain, Callee, InFlag };
 370   Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
 371                       InFlag.getNode() ? 3 : 2);
 372   InFlag = Chain.getValue(1);
 373
 374   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
 375                              DAG.getIntPtrConstant(0, true), InFlag);
 376   InFlag = Chain.getValue(1);
 377
 378   // Assign locations to each value returned by this call.
 379   SmallVector<CCValAssign, 16> RVLocs;
 380   CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs,
 381                  *DAG.getContext());
 382
 383   RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
 384
 385   // Copy all of the result registers out of their specified physreg.
 386   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 387     CCValAssign &RV = RVLocs[i];
 388     unsigned Reg = RV.getLocReg();
 389
 390     Chain = DAG.getCopyFromReg(Chain, dl, Reg,
 391                                RVLocs[i].getLocVT(), InFlag);
 392     SDValue Val = Chain.getValue(0);
 393     InFlag = Chain.getValue(2);
 394     Chain = Chain.getValue(1);
 395
 396     // Callee is responsible for extending any i16 return values.
 397     switch (RV.getLocInfo()) {
 398     case CCValAssign::SExt:
 399       Val = DAG.getNode(ISD::AssertSext, dl, RV.getLocVT(), Val,
 400                         DAG.getValueType(RV.getValVT()));
 401       break;
 402     case CCValAssign::ZExt:
 403       Val = DAG.getNode(ISD::AssertZext, dl, RV.getLocVT(), Val,
 404                         DAG.getValueType(RV.getValVT()));
 405       break;
 406     default:
 407       break;
 408     }
 409
 410     // Truncate to valtype
 411     if (RV.getLocInfo() != CCValAssign::Full)
 412       Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val);
 413     InVals.push_back(Val);
 414   }
 415
 416   return Chain;
 417 }
 418
 419 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
 420 // add-with-carry instructions.
 421 SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) const {
 422   // Operands: lhs, rhs, carry-in (AC0 flag)
 423   // Results: sum, carry-out (AC0 flag)
 424   DebugLoc dl = Op.getDebugLoc();
 425
 426   unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
 427
 428   // zext incoming carry flag in AC0 to 32 bits
 429   SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
 430                                        /* flag= */ Op.getOperand(2));
 431   CarryIn = DAG.getMachineNode(BF::MOVECC_zext, dl, MVT::i32,
 432                                SDValue(CarryIn, 0));
 433
 434   // Add operands, produce sum and carry flag
 435   SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
 436                                    Op.getOperand(0), Op.getOperand(1));
 437
 438   // Store intermediate carry from Sum
 439   SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
 440                                       /* flag= */ SDValue(Sum, 1));
 441
 442   // Add incoming carry, again producing an output flag
 443   Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
 444                            SDValue(Sum, 0), SDValue(CarryIn, 0));
 445
 446   // Update AC0 with the intermediate carry, producing a flag.
 447   SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Flag,
 448                                         SDValue(Carry1, 0));
 449
 450   // Compose (i32, flag) pair
 451   SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) };
 452   return DAG.getMergeValues(ops, 2, dl);
 453 }
 454
 455 SDValue BlackfinTargetLowering::LowerOperation(SDValue Op,
 456                                                SelectionDAG &DAG) const {
 457   switch (Op.getOpcode()) {
 458   default:
 459     Op.getNode()->dump();
 460     llvm_unreachable("Should not custom lower this!");
 461   case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
 462   case ISD::GlobalTLSAddress:
 463     llvm_unreachable("TLS not implemented for Blackfin.");
 464   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
 465     // Frame & Return address.  Currently unimplemented
 466   case ISD::FRAMEADDR:          return SDValue();
 467   case ISD::RETURNADDR:         return SDValue();
 468   case ISD::ADDE:
 469   case ISD::SUBE:               return LowerADDE(Op, DAG);
 470   }
 471 }
 472
 473 void
 474 BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
 475                                            SmallVectorImpl<SDValue> &Results,
 476                                            SelectionDAG &DAG) const {
 477   DebugLoc dl = N->getDebugLoc();
 478   switch (N->getOpcode()) {
 479   default:
 480     llvm_unreachable("Do not know how to custom type legalize this operation!");
 481     return;
 482   case ISD::READCYCLECOUNTER: {
 483     // The low part of the cycle counter is in CYCLES, the high part in
 484     // CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
 485     // CYCLES2 last.
 486     SDValue TheChain = N->getOperand(0);
 487     SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
 488     SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
 489     // Use a buildpair to merge the two 32-bit values into a 64-bit one.
 490     Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
 491     // Outgoing chain. If we were to use the chain from lo instead, it would be
 492     // possible to entirely eliminate the CYCLES2 read in (i32 (trunc
 493     // readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
 494     // read beyond the next CYCLES read, leading to invalid results.
 495     Results.push_back(hi.getValue(1));
 496     return;
 497   }
 498   }
 499 }
 500
 501 /// getFunctionAlignment - Return the Log2 alignment of this function.
 502 unsigned BlackfinTargetLowering::getFunctionAlignment(const Function *F) const {
 503   return 2;
 504 }
 505
 506 //===----------------------------------------------------------------------===//
 507 //                         Blackfin Inline Assembly Support
 508 //===----------------------------------------------------------------------===//
 509
 510 /// getConstraintType - Given a constraint letter, return the type of
 511 /// constraint it is for this target.
 512 BlackfinTargetLowering::ConstraintType
 513 BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const {
 514   if (Constraint.size() != 1)
 515     return TargetLowering::getConstraintType(Constraint);
 516
 517   switch (Constraint[0]) {
 518     // Standard constraints
 519   case 'r':
 520     return C_RegisterClass;
 521
 522     // Blackfin-specific constraints
 523   case 'a':
 524   case 'd':
 525   case 'z':
 526   case 'D':
 527   case 'W':
 528   case 'e':
 529   case 'b':
 530   case 'v':
 531   case 'f':
 532   case 'c':
 533   case 't':
 534   case 'u':
 535   case 'k':
 536   case 'x':
 537   case 'y':
 538   case 'w':
 539     return C_RegisterClass;
 540   case 'A':
 541   case 'B':
 542   case 'C':
 543   case 'Z':
 544   case 'Y':
 545     return C_Register;
 546   }
 547
 548   // Not implemented: q0-q7, qA. Use {R2} etc instead
 549
 550   return TargetLowering::getConstraintType(Constraint);
 551 }
 552
 553 /// Examine constraint type and operand type and determine a weight value.
 554 /// This object must already have been set up with the operand type
 555 /// and the current alternative constraint selected.
 556 TargetLowering::ConstraintWeight
 557 BlackfinTargetLowering::getSingleConstraintMatchWeight(
 558     AsmOperandInfo &info, const char *constraint) const {
 559   ConstraintWeight weight = CW_Invalid;
 560   Value *CallOperandVal = info.CallOperandVal;
 561     // If we don't have a value, we can't do a match,
 562     // but allow it at the lowest weight.
 563   if (CallOperandVal == NULL)
 564     return CW_Default;
 565   // Look at the constraint type.
 566   switch (*constraint) {
 567   default:
 568     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
 569     break;
 570
 571     // Blackfin-specific constraints
 572   case 'a':
 573   case 'd':
 574   case 'z':
 575   case 'D':
 576   case 'W':
 577   case 'e':
 578   case 'b':
 579   case 'v':
 580   case 'f':
 581   case 'c':
 582   case 't':
 583   case 'u':
 584   case 'k':
 585   case 'x':
 586   case 'y':
 587   case 'w':
 588     return CW_Register;
 589   case 'A':
 590   case 'B':
 591   case 'C':
 592   case 'Z':
 593   case 'Y':
 594     return CW_SpecificReg;
 595   }
 596   return weight;
 597 }
 598
 599 /// getRegForInlineAsmConstraint - Return register no and class for a C_Register
 600 /// constraint.
 601 std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
 602 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
 603   typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
 604   using namespace BF;
 605
 606   if (Constraint.size() != 1)
 607     return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 608
 609   switch (Constraint[0]) {
 610     // Standard constraints
 611   case 'r':
 612     return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
 613
 614     // Blackfin-specific constraints
 615   case 'a': return Pair(0U, PRegisterClass);
 616   case 'd': return Pair(0U, DRegisterClass);
 617   case 'e': return Pair(0U, AccuRegisterClass);
 618   case 'A': return Pair(A0, AccuRegisterClass);
 619   case 'B': return Pair(A1, AccuRegisterClass);
 620   case 'b': return Pair(0U, IRegisterClass);
 621   case 'v': return Pair(0U, BRegisterClass);
 622   case 'f': return Pair(0U, MRegisterClass);
 623   case 'C': return Pair(CC, JustCCRegisterClass);
 624   case 'x': return Pair(0U, GRRegisterClass);
 625   case 'w': return Pair(0U, ALLRegisterClass);
 626   case 'Z': return Pair(P3, PRegisterClass);
 627   case 'Y': return Pair(P1, PRegisterClass);
 628   }
 629
 630   // Not implemented: q0-q7, qA. Use {R2} etc instead.
 631   // Constraints z, D, W, c, t, u, k, and y use non-existing classes, defer to
 632   // getRegClassForInlineAsmConstraint()
 633
 634   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 635 }
 636
 637 std::vector<unsigned> BlackfinTargetLowering::
 638 getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
 639   using namespace BF;
 640
 641   if (Constraint.size() != 1)
 642     return std::vector<unsigned>();
 643
 644   switch (Constraint[0]) {
 645   case 'z': return make_vector<unsigned>(P0, P1, P2, 0);
 646   case 'D': return make_vector<unsigned>(R0, R2, R4, R6, 0);
 647   case 'W': return make_vector<unsigned>(R1, R3, R5, R7, 0);
 648   case 'c': return make_vector<unsigned>(I0, I1, I2, I3,
 649                                          B0, B1, B2, B3,
 650                                          L0, L1, L2, L3, 0);
 651   case 't': return make_vector<unsigned>(LT0, LT1, 0);
 652   case 'u': return make_vector<unsigned>(LB0, LB1, 0);
 653   case 'k': return make_vector<unsigned>(LC0, LC1, 0);
 654   case 'y': return make_vector<unsigned>(RETS, RETN, RETI, RETX, RETE,
 655                                          ASTAT, SEQSTAT, USP, 0);
 656   }
 657
 658   return std::vector<unsigned>();
 659 }
 660
 661 bool BlackfinTargetLowering::
 662 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
 663   // The Blackfin target isn't yet aware of offsets.
 664   return false;
 665 }