lib/Target/Blackfin/BlackfinInstrInfo.h

   1 //===- BlackfinInstrInfo.h - Blackfin Instruction Information ---*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Blackfin implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef BLACKFININSTRUCTIONINFO_H
  15 #define BLACKFININSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "BlackfinRegisterInfo.h"
  19
  20 namespace llvm {
  21
  22   class BlackfinInstrInfo : public TargetInstrInfoImpl {
  23     const BlackfinRegisterInfo RI;
  24     const BlackfinSubtarget& Subtarget;
  25   public:
  26     explicit BlackfinInstrInfo(BlackfinSubtarget &ST);
  27
  28     /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  29     /// such, whenever a client has an instance of instruction info, it should
  30     /// always be able to get register info as well (through this method).
  31     virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; }
  32
  33     virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
  34                                          int &FrameIndex) const;
  35
  36     virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
  37                                         int &FrameIndex) const;
  38
  39     virtual unsigned
  40     InsertBranch(MachineBasicBlock &MBB,
  41                  MachineBasicBlock *TBB,
  42                  MachineBasicBlock *FBB,
  43                  const SmallVectorImpl<MachineOperand> &Cond,
  44                  DebugLoc DL) const;
  45
  46     virtual void copyPhysReg(MachineBasicBlock &MBB,
  47                              MachineBasicBlock::iterator MI, DebugLoc DL,
  48                              unsigned DestReg, unsigned SrcReg,
  49                              bool KillSrc) const;
  50
  51     virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  52                                      MachineBasicBlock::iterator MBBI,
  53                                      unsigned SrcReg, bool isKill,
  54                                      int FrameIndex,
  55                                      const TargetRegisterClass *RC,
  56                                      const TargetRegisterInfo *TRI) const;
  57
  58     virtual void storeRegToAddr(MachineFunction &MF,
  59                                 unsigned SrcReg, bool isKill,
  60                                 SmallVectorImpl<MachineOperand> &Addr,
  61                                 const TargetRegisterClass *RC,
  62                                 SmallVectorImpl<MachineInstr*> &NewMIs) const;
  63
  64     virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  65                                       MachineBasicBlock::iterator MBBI,
  66                                       unsigned DestReg, int FrameIndex,
  67                                       const TargetRegisterClass *RC,
  68                                       const TargetRegisterInfo *TRI) const;
  69
  70     virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
  71                                  SmallVectorImpl<MachineOperand> &Addr,
  72                                  const TargetRegisterClass *RC,
  73                                  SmallVectorImpl<MachineInstr*> &NewMIs) const;
  74   };
  75
  76 } // end namespace llvm
  77
  78 #endif