lib/Target/CellSPU/SPUInstrInfo.cpp

   1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "SPURegisterNames.h"
  15 #include "SPUInstrInfo.h"
  16 #include "SPUInstrBuilder.h"
  17 #include "SPUTargetMachine.h"
  18 #include "SPUGenInstrInfo.inc"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/Support/raw_ostream.h"
  23
  24 using namespace llvm;
  25
  26 namespace {
  27   //! Predicate for an unconditional branch instruction
  28   inline bool isUncondBranch(const MachineInstr *I) {
  29     unsigned opc = I->getOpcode();
  30
  31     return (opc == SPU::BR
  32             || opc == SPU::BRA
  33             || opc == SPU::BI);
  34   }
  35
  36   //! Predicate for a conditional branch instruction
  37   inline bool isCondBranch(const MachineInstr *I) {
  38     unsigned opc = I->getOpcode();
  39
  40     return (opc == SPU::BRNZr32
  41             || opc == SPU::BRNZv4i32
  42             || opc == SPU::BRZr32
  43             || opc == SPU::BRZv4i32
  44             || opc == SPU::BRHNZr16
  45             || opc == SPU::BRHNZv8i16
  46             || opc == SPU::BRHZr16
  47             || opc == SPU::BRHZv8i16);
  48   }
  49 }
  50
  51 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
  52   : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
  53     TM(tm),
  54     RI(*TM.getSubtargetImpl(), *this)
  55 { /* NOP */ }
  56
  57 unsigned
  58 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
  59                                   int &FrameIndex) const {
  60   switch (MI->getOpcode()) {
  61   default: break;
  62   case SPU::LQDv16i8:
  63   case SPU::LQDv8i16:
  64   case SPU::LQDv4i32:
  65   case SPU::LQDv4f32:
  66   case SPU::LQDv2f64:
  67   case SPU::LQDr128:
  68   case SPU::LQDr64:
  69   case SPU::LQDr32:
  70   case SPU::LQDr16: {
  71     const MachineOperand MOp1 = MI->getOperand(1);
  72     const MachineOperand MOp2 = MI->getOperand(2);
  73     if (MOp1.isImm() && MOp2.isFI()) {
  74       FrameIndex = MOp2.getIndex();
  75       return MI->getOperand(0).getReg();
  76     }
  77     break;
  78   }
  79   }
  80   return 0;
  81 }
  82
  83 unsigned
  84 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
  85                                  int &FrameIndex) const {
  86   switch (MI->getOpcode()) {
  87   default: break;
  88   case SPU::STQDv16i8:
  89   case SPU::STQDv8i16:
  90   case SPU::STQDv4i32:
  91   case SPU::STQDv4f32:
  92   case SPU::STQDv2f64:
  93   case SPU::STQDr128:
  94   case SPU::STQDr64:
  95   case SPU::STQDr32:
  96   case SPU::STQDr16:
  97   case SPU::STQDr8: {
  98     const MachineOperand MOp1 = MI->getOperand(1);
  99     const MachineOperand MOp2 = MI->getOperand(2);
 100     if (MOp1.isImm() && MOp2.isFI()) {
 101       FrameIndex = MOp2.getIndex();
 102       return MI->getOperand(0).getReg();
 103     }
 104     break;
 105   }
 106   }
 107   return 0;
 108 }
 109
 110 void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 111                                MachineBasicBlock::iterator I, DebugLoc DL,
 112                                unsigned DestReg, unsigned SrcReg,
 113                                bool KillSrc) const
 114 {
 115   // We support cross register class moves for our aliases, such as R3 in any
 116   // reg class to any other reg class containing R3.  This is required because
 117   // we instruction select bitconvert i64 -> f64 as a noop for example, so our
 118   // types have no specific meaning.
 119
 120   BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
 121     .addReg(SrcReg, getKillRegState(KillSrc));
 122 }
 123
 124 void
 125 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 126                                   MachineBasicBlock::iterator MI,
 127                                   unsigned SrcReg, bool isKill, int FrameIdx,
 128                                   const TargetRegisterClass *RC,
 129                                   const TargetRegisterInfo *TRI) const
 130 {
 131   unsigned opc;
 132   bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
 133   if (RC == SPU::GPRCRegisterClass) {
 134     opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
 135   } else if (RC == SPU::R64CRegisterClass) {
 136     opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
 137   } else if (RC == SPU::R64FPRegisterClass) {
 138     opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
 139   } else if (RC == SPU::R32CRegisterClass) {
 140     opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
 141   } else if (RC == SPU::R32FPRegisterClass) {
 142     opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
 143   } else if (RC == SPU::R16CRegisterClass) {
 144     opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
 145   } else if (RC == SPU::R8CRegisterClass) {
 146     opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
 147   } else if (RC == SPU::VECREGRegisterClass) {
 148     opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
 149   } else {
 150     llvm_unreachable("Unknown regclass!");
 151   }
 152
 153   DebugLoc DL;
 154   if (MI != MBB.end()) DL = MI->getDebugLoc();
 155   addFrameReference(BuildMI(MBB, MI, DL, get(opc))
 156                     .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
 157 }
 158
 159 void
 160 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 161                                    MachineBasicBlock::iterator MI,
 162                                    unsigned DestReg, int FrameIdx,
 163                                    const TargetRegisterClass *RC,
 164                                    const TargetRegisterInfo *TRI) const
 165 {
 166   unsigned opc;
 167   bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
 168   if (RC == SPU::GPRCRegisterClass) {
 169     opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
 170   } else if (RC == SPU::R64CRegisterClass) {
 171     opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
 172   } else if (RC == SPU::R64FPRegisterClass) {
 173     opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
 174   } else if (RC == SPU::R32CRegisterClass) {
 175     opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
 176   } else if (RC == SPU::R32FPRegisterClass) {
 177     opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
 178   } else if (RC == SPU::R16CRegisterClass) {
 179     opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
 180   } else if (RC == SPU::R8CRegisterClass) {
 181     opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
 182   } else if (RC == SPU::VECREGRegisterClass) {
 183     opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
 184   } else {
 185     llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
 186   }
 187
 188   DebugLoc DL;
 189   if (MI != MBB.end()) DL = MI->getDebugLoc();
 190   addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
 191 }
 192
 193 //! Branch analysis
 194 /*!
 195   \note This code was kiped from PPC. There may be more branch analysis for
 196   CellSPU than what's currently done here.
 197  */
 198 bool
 199 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 200                             MachineBasicBlock *&FBB,
 201                             SmallVectorImpl<MachineOperand> &Cond,
 202                             bool AllowModify) const {
 203   // If the block has no terminators, it just falls into the block after it.
 204   MachineBasicBlock::iterator I = MBB.end();
 205   if (I == MBB.begin())
 206     return false;
 207   --I;
 208   while (I->isDebugValue()) {
 209     if (I == MBB.begin())
 210       return false;
 211     --I;
 212   }
 213   if (!isUnpredicatedTerminator(I))
 214     return false;
 215
 216   // Get the last instruction in the block.
 217   MachineInstr *LastInst = I;
 218
 219   // If there is only one terminator instruction, process it.
 220   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 221     if (isUncondBranch(LastInst)) {
 222       // Check for jump tables
 223       if (!LastInst->getOperand(0).isMBB())
 224         return true;
 225       TBB = LastInst->getOperand(0).getMBB();
 226       return false;
 227     } else if (isCondBranch(LastInst)) {
 228       // Block ends with fall-through condbranch.
 229       TBB = LastInst->getOperand(1).getMBB();
 230       DEBUG(errs() << "Pushing LastInst:               ");
 231       DEBUG(LastInst->dump());
 232       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
 233       Cond.push_back(LastInst->getOperand(0));
 234       return false;
 235     }
 236     // Otherwise, don't know what this is.
 237     return true;
 238   }
 239
 240   // Get the instruction before it if it's a terminator.
 241   MachineInstr *SecondLastInst = I;
 242
 243   // If there are three terminators, we don't know what sort of block this is.
 244   if (SecondLastInst && I != MBB.begin() &&
 245       isUnpredicatedTerminator(--I))
 246     return true;
 247
 248   // If the block ends with a conditional and unconditional branch, handle it.
 249   if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
 250     TBB =  SecondLastInst->getOperand(1).getMBB();
 251     DEBUG(errs() << "Pushing SecondLastInst:         ");
 252     DEBUG(SecondLastInst->dump());
 253     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
 254     Cond.push_back(SecondLastInst->getOperand(0));
 255     FBB = LastInst->getOperand(0).getMBB();
 256     return false;
 257   }
 258
 259   // If the block ends with two unconditional branches, handle it.  The second
 260   // one is not executed, so remove it.
 261   if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
 262     TBB = SecondLastInst->getOperand(0).getMBB();
 263     I = LastInst;
 264     if (AllowModify)
 265       I->eraseFromParent();
 266     return false;
 267   }
 268
 269   // Otherwise, can't handle this.
 270   return true;
 271 }
 272
 273 unsigned
 274 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 275   MachineBasicBlock::iterator I = MBB.end();
 276   if (I == MBB.begin())
 277     return 0;
 278   --I;
 279   while (I->isDebugValue()) {
 280     if (I == MBB.begin())
 281       return 0;
 282     --I;
 283   }
 284   if (!isCondBranch(I) && !isUncondBranch(I))
 285     return 0;
 286
 287   // Remove the first branch.
 288   DEBUG(errs() << "Removing branch:                ");
 289   DEBUG(I->dump());
 290   I->eraseFromParent();
 291   I = MBB.end();
 292   if (I == MBB.begin())
 293     return 1;
 294
 295   --I;
 296   if (!(isCondBranch(I) || isUncondBranch(I)))
 297     return 1;
 298
 299   // Remove the second branch.
 300   DEBUG(errs() << "Removing second branch:         ");
 301   DEBUG(I->dump());
 302   I->eraseFromParent();
 303   return 2;
 304 }
 305
 306 unsigned
 307 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 308                            MachineBasicBlock *FBB,
 309                            const SmallVectorImpl<MachineOperand> &Cond,
 310                            DebugLoc DL) const {
 311   // Shouldn't be a fall through.
 312   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 313   assert((Cond.size() == 2 || Cond.size() == 0) &&
 314          "SPU branch conditions have two components!");
 315
 316   // One-way branch.
 317   if (FBB == 0) {
 318     if (Cond.empty()) {
 319       // Unconditional branch
 320       MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(SPU::BR));
 321       MIB.addMBB(TBB);
 322
 323       DEBUG(errs() << "Inserted one-way uncond branch: ");
 324       DEBUG((*MIB).dump());
 325     } else {
 326       // Conditional branch
 327       MachineInstrBuilder  MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
 328       MIB.addReg(Cond[1].getReg()).addMBB(TBB);
 329
 330       DEBUG(errs() << "Inserted one-way cond branch:   ");
 331       DEBUG((*MIB).dump());
 332     }
 333     return 1;
 334   } else {
 335     MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
 336     MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
 337
 338     // Two-way Conditional Branch.
 339     MIB.addReg(Cond[1].getReg()).addMBB(TBB);
 340     MIB2.addMBB(FBB);
 341
 342     DEBUG(errs() << "Inserted conditional branch:    ");
 343     DEBUG((*MIB).dump());
 344     DEBUG(errs() << "part 2: ");
 345     DEBUG((*MIB2).dump());
 346    return 2;
 347   }
 348 }
 349
 350 //! Reverses a branch's condition, returning false on success.
 351 bool
 352 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
 353   const {
 354   // Pretty brainless way of inverting the condition, but it works, considering
 355   // there are only two conditions...
 356   static struct {
 357     unsigned Opc;               //! The incoming opcode
 358     unsigned RevCondOpc;        //! The reversed condition opcode
 359   } revconds[] = {
 360     { SPU::BRNZr32, SPU::BRZr32 },
 361     { SPU::BRNZv4i32, SPU::BRZv4i32 },
 362     { SPU::BRZr32, SPU::BRNZr32 },
 363     { SPU::BRZv4i32, SPU::BRNZv4i32 },
 364     { SPU::BRHNZr16, SPU::BRHZr16 },
 365     { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
 366     { SPU::BRHZr16, SPU::BRHNZr16 },
 367     { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
 368   };
 369
 370   unsigned Opc = unsigned(Cond[0].getImm());
 371   // Pretty dull mapping between the two conditions that SPU can generate:
 372   for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
 373     if (revconds[i].Opc == Opc) {
 374       Cond[0].setImm(revconds[i].RevCondOpc);
 375       return false;
 376     }
 377   }
 378
 379   return true;
 380 }