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Fixed some bugs.
[llvm/zpu.git] / lib / Target / CellSPU / SPURegisterInfo.cpp
blobcf718917a5616f1ee310f079aee6b1f4be6c4050
1 //===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Cell implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "reginfo"
15 #include "SPU.h"
16 #include "SPURegisterInfo.h"
17 #include "SPURegisterNames.h"
18 #include "SPUInstrBuilder.h"
19 #include "SPUSubtarget.h"
20 #include "SPUMachineFunction.h"
21 #include "SPUFrameInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/STLExtras.h"
44 #include <cstdlib>
45
46 using namespace llvm;
47
48 /// getRegisterNumbering - Given the enum value for some register, e.g.
49 /// PPC::F14, return the number that it corresponds to (e.g. 14).
50 unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
51 using namespace SPU;
52 switch (RegEnum) {
53 case SPU::R0: return 0;
54 case SPU::R1: return 1;
55 case SPU::R2: return 2;
56 case SPU::R3: return 3;
57 case SPU::R4: return 4;
58 case SPU::R5: return 5;
59 case SPU::R6: return 6;
60 case SPU::R7: return 7;
61 case SPU::R8: return 8;
62 case SPU::R9: return 9;
63 case SPU::R10: return 10;
64 case SPU::R11: return 11;
65 case SPU::R12: return 12;
66 case SPU::R13: return 13;
67 case SPU::R14: return 14;
68 case SPU::R15: return 15;
69 case SPU::R16: return 16;
70 case SPU::R17: return 17;
71 case SPU::R18: return 18;
72 case SPU::R19: return 19;
73 case SPU::R20: return 20;
74 case SPU::R21: return 21;
75 case SPU::R22: return 22;
76 case SPU::R23: return 23;
77 case SPU::R24: return 24;
78 case SPU::R25: return 25;
79 case SPU::R26: return 26;
80 case SPU::R27: return 27;
81 case SPU::R28: return 28;
82 case SPU::R29: return 29;
83 case SPU::R30: return 30;
84 case SPU::R31: return 31;
85 case SPU::R32: return 32;
86 case SPU::R33: return 33;
87 case SPU::R34: return 34;
88 case SPU::R35: return 35;
89 case SPU::R36: return 36;
90 case SPU::R37: return 37;
91 case SPU::R38: return 38;
92 case SPU::R39: return 39;
93 case SPU::R40: return 40;
94 case SPU::R41: return 41;
95 case SPU::R42: return 42;
96 case SPU::R43: return 43;
97 case SPU::R44: return 44;
98 case SPU::R45: return 45;
99 case SPU::R46: return 46;
100 case SPU::R47: return 47;
101 case SPU::R48: return 48;
102 case SPU::R49: return 49;
103 case SPU::R50: return 50;
104 case SPU::R51: return 51;
105 case SPU::R52: return 52;
106 case SPU::R53: return 53;
107 case SPU::R54: return 54;
108 case SPU::R55: return 55;
109 case SPU::R56: return 56;
110 case SPU::R57: return 57;
111 case SPU::R58: return 58;
112 case SPU::R59: return 59;
113 case SPU::R60: return 60;
114 case SPU::R61: return 61;
115 case SPU::R62: return 62;
116 case SPU::R63: return 63;
117 case SPU::R64: return 64;
118 case SPU::R65: return 65;
119 case SPU::R66: return 66;
120 case SPU::R67: return 67;
121 case SPU::R68: return 68;
122 case SPU::R69: return 69;
123 case SPU::R70: return 70;
124 case SPU::R71: return 71;
125 case SPU::R72: return 72;
126 case SPU::R73: return 73;
127 case SPU::R74: return 74;
128 case SPU::R75: return 75;
129 case SPU::R76: return 76;
130 case SPU::R77: return 77;
131 case SPU::R78: return 78;
132 case SPU::R79: return 79;
133 case SPU::R80: return 80;
134 case SPU::R81: return 81;
135 case SPU::R82: return 82;
136 case SPU::R83: return 83;
137 case SPU::R84: return 84;
138 case SPU::R85: return 85;
139 case SPU::R86: return 86;
140 case SPU::R87: return 87;
141 case SPU::R88: return 88;
142 case SPU::R89: return 89;
143 case SPU::R90: return 90;
144 case SPU::R91: return 91;
145 case SPU::R92: return 92;
146 case SPU::R93: return 93;
147 case SPU::R94: return 94;
148 case SPU::R95: return 95;
149 case SPU::R96: return 96;
150 case SPU::R97: return 97;
151 case SPU::R98: return 98;
152 case SPU::R99: return 99;
153 case SPU::R100: return 100;
154 case SPU::R101: return 101;
155 case SPU::R102: return 102;
156 case SPU::R103: return 103;
157 case SPU::R104: return 104;
158 case SPU::R105: return 105;
159 case SPU::R106: return 106;
160 case SPU::R107: return 107;
161 case SPU::R108: return 108;
162 case SPU::R109: return 109;
163 case SPU::R110: return 110;
164 case SPU::R111: return 111;
165 case SPU::R112: return 112;
166 case SPU::R113: return 113;
167 case SPU::R114: return 114;
168 case SPU::R115: return 115;
169 case SPU::R116: return 116;
170 case SPU::R117: return 117;
171 case SPU::R118: return 118;
172 case SPU::R119: return 119;
173 case SPU::R120: return 120;
174 case SPU::R121: return 121;
175 case SPU::R122: return 122;
176 case SPU::R123: return 123;
177 case SPU::R124: return 124;
178 case SPU::R125: return 125;
179 case SPU::R126: return 126;
180 case SPU::R127: return 127;
181 default:
182 report_fatal_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering");
183 }
184 }
185
186 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
187 const TargetInstrInfo &tii) :
188 SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
189 Subtarget(subtarget),
190 TII(tii)
191 {
192 }
193
194 /// getPointerRegClass - Return the register class to use to hold pointers.
195 /// This is used for addressing modes.
196 const TargetRegisterClass *
197 SPURegisterInfo::getPointerRegClass(unsigned Kind) const {
198 return &SPU::R32CRegClass;
199 }
200
201 const unsigned *
202 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
203 {
204 // Cell ABI calling convention
205 static const unsigned SPU_CalleeSaveRegs[] = {
206 SPU::R80, SPU::R81, SPU::R82, SPU::R83,
207 SPU::R84, SPU::R85, SPU::R86, SPU::R87,
208 SPU::R88, SPU::R89, SPU::R90, SPU::R91,
209 SPU::R92, SPU::R93, SPU::R94, SPU::R95,
210 SPU::R96, SPU::R97, SPU::R98, SPU::R99,
211 SPU::R100, SPU::R101, SPU::R102, SPU::R103,
212 SPU::R104, SPU::R105, SPU::R106, SPU::R107,
213 SPU::R108, SPU::R109, SPU::R110, SPU::R111,
214 SPU::R112, SPU::R113, SPU::R114, SPU::R115,
215 SPU::R116, SPU::R117, SPU::R118, SPU::R119,
216 SPU::R120, SPU::R121, SPU::R122, SPU::R123,
217 SPU::R124, SPU::R125, SPU::R126, SPU::R127,
218 SPU::R2, /* environment pointer */
219 SPU::R1, /* stack pointer */
220 SPU::R0, /* link register */
221 0 /* end */
222 };
223
224 return SPU_CalleeSaveRegs;
225 }
226
227 /*!
228 R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
229 generally unused) are the Cell's reserved registers
230 */
231 BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
232 BitVector Reserved(getNumRegs());
233 Reserved.set(SPU::R0); // LR
234 Reserved.set(SPU::R1); // SP
235 Reserved.set(SPU::R2); // environment pointer
236 return Reserved;
237 }
238
239 //===----------------------------------------------------------------------===//
240 // Stack Frame Processing methods
241 //===----------------------------------------------------------------------===//
242
243 // needsFP - Return true if the specified function should have a dedicated frame
244 // pointer register. This is true if the function has variable sized allocas or
245 // if frame pointer elimination is disabled.
246 //
247 static bool needsFP(const MachineFunction &MF) {
248 const MachineFrameInfo *MFI = MF.getFrameInfo();
249 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
250 }
251
252 //--------------------------------------------------------------------------
253 // hasFP - Return true if the specified function actually has a dedicated frame
254 // pointer register. This is true if the function needs a frame pointer and has
255 // a non-zero stack size.
256 bool
257 SPURegisterInfo::hasFP(const MachineFunction &MF) const {
258 const MachineFrameInfo *MFI = MF.getFrameInfo();
259 return MFI->getStackSize() && needsFP(MF);
260 }
261
262 //--------------------------------------------------------------------------
263 void
264 SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
265 MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator I)
267 const
268 {
269 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
270 MBB.erase(I);
271 }
272
273 void
274 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
275 RegScavenger *RS) const
276 {
277 unsigned i = 0;
278 MachineInstr &MI = *II;
279 MachineBasicBlock &MBB = *MI.getParent();
280 MachineFunction &MF = *MBB.getParent();
281 MachineFrameInfo *MFI = MF.getFrameInfo();
282 DebugLoc dl = II->getDebugLoc();
283
284 while (!MI.getOperand(i).isFI()) {
285 ++i;
286 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
287 }
288
289 MachineOperand &SPOp = MI.getOperand(i);
290 int FrameIndex = SPOp.getIndex();
291
292 // Now add the frame object offset to the offset from r1.
293 int Offset = MFI->getObjectOffset(FrameIndex);
294
295 // Most instructions, except for generated FrameIndex additions using AIr32
296 // and ILAr32, have the immediate in operand 1. AIr32 and ILAr32 have the
297 // immediate in operand 2.
298 unsigned OpNo = 1;
299 if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32)
300 OpNo = 2;
301
302 MachineOperand &MO = MI.getOperand(OpNo);
303
304 // Offset is biased by $lr's slot at the bottom.
305 Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
306 assert((Offset & 0xf) == 0
307 && "16-byte alignment violated in eliminateFrameIndex");
308
309 // Replace the FrameIndex with base register with $sp (aka $r1)
310 SPOp.ChangeToRegister(SPU::R1, false);
311
312 // if 'Offset' doesn't fit to the D-form instruction's
313 // immediate, convert the instruction to X-form
314 // if the instruction is not an AI (which takes a s10 immediate), assume
315 // it is a load/store that can take a s14 immediate
316 if ((MI.getOpcode() == SPU::AIr32 && !isInt<10>(Offset))
317 || !isInt<14>(Offset)) {
318 int newOpcode = convertDFormToXForm(MI.getOpcode());
319 unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
320 BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
321 .addImm(Offset);
322 BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
323 .addReg(tmpReg, RegState::Kill)
324 .addReg(SPU::R1);
325 // remove the replaced D-form instruction
326 MBB.erase(II);
327 } else {
328 MO.ChangeToImmediate(Offset);
329 }
330 }
331
332 /// determineFrameLayout - Determine the size of the frame and maximum call
333 /// frame size.
334 void
335 SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const
336 {
337 MachineFrameInfo *MFI = MF.getFrameInfo();
338
339 // Get the number of bytes to allocate from the FrameInfo
340 unsigned FrameSize = MFI->getStackSize();
341
342 // Get the alignments provided by the target, and the maximum alignment
343 // (if any) of the fixed frame objects.
344 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
345 unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
346 assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
347 unsigned AlignMask = Align - 1;
348
349 // Get the maximum call frame size of all the calls.
350 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
351
352 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
353 // that allocations will be aligned.
354 if (MFI->hasVarSizedObjects())
355 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
356
357 // Update maximum call frame size.
358 MFI->setMaxCallFrameSize(maxCallFrameSize);
359
360 // Include call frame size in total.
361 FrameSize += maxCallFrameSize;
362
363 // Make sure the frame is aligned.
364 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
365
366 // Update frame info.
367 MFI->setStackSize(FrameSize);
368 }
369
370 void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
371 RegScavenger *RS)
372 const {
373 // Mark LR and SP unused, since the prolog spills them to stack and
374 // we don't want anyone else to spill them for us.
375 //
376 // Also, unless R2 is really used someday, don't spill it automatically.
377 MF.getRegInfo().setPhysRegUnused(SPU::R0);
378 MF.getRegInfo().setPhysRegUnused(SPU::R1);
379 MF.getRegInfo().setPhysRegUnused(SPU::R2);
380
381 MachineFrameInfo *MFI = MF.getFrameInfo();
382 const TargetRegisterClass *RC = &SPU::R32CRegClass;
383 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
384 RC->getAlignment(),
385 false));
386
387
388 }
389
390 void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
391 {
392 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
393 MachineBasicBlock::iterator MBBI = MBB.begin();
394 MachineFrameInfo *MFI = MF.getFrameInfo();
395 MachineModuleInfo &MMI = MF.getMMI();
396 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
397
398 // Prepare for debug frame info.
399 bool hasDebugInfo = MMI.hasDebugInfo();
400 MCSymbol *FrameLabel = 0;
401
402 // Move MBBI back to the beginning of the function.
403 MBBI = MBB.begin();
404
405 // Work out frame sizes.
406 determineFrameLayout(MF);
407 int FrameSize = MFI->getStackSize();
408
409 assert((FrameSize & 0xf) == 0
410 && "SPURegisterInfo::emitPrologue: FrameSize not aligned");
411
412 // the "empty" frame size is 16 - just the register scavenger spill slot
413 if (FrameSize > 16 || MFI->adjustsStack()) {
414 FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
415 if (hasDebugInfo) {
416 // Mark effective beginning of when frame pointer becomes valid.
417 FrameLabel = MMI.getContext().CreateTempSymbol();
418 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
419 }
420
421 // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
422 // for the ABI
423 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
424 .addReg(SPU::R1);
425 if (isInt<10>(FrameSize)) {
426 // Spill $sp to adjusted $sp
427 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
428 .addReg(SPU::R1);
429 // Adjust $sp by required amout
430 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
431 .addImm(FrameSize);
432 } else if (isInt<16>(FrameSize)) {
433 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
434 // $r2 to adjust $sp:
435 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
436 .addImm(-16)
437 .addReg(SPU::R1);
438 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
439 .addImm(FrameSize);
440 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
441 .addReg(SPU::R2)
442 .addReg(SPU::R1);
443 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
444 .addReg(SPU::R1)
445 .addReg(SPU::R2);
446 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
447 .addReg(SPU::R2)
448 .addImm(16);
449 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
450 .addReg(SPU::R2)
451 .addReg(SPU::R1);
452 } else {
453 report_fatal_error("Unhandled frame size: " + Twine(FrameSize));
454 }
455
456 if (hasDebugInfo) {
457 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
458
459 // Show update of SP.
460 MachineLocation SPDst(MachineLocation::VirtualFP);
461 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
462 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
463
464 // Add callee saved registers to move list.
465 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
466 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
467 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
468 unsigned Reg = CSI[I].getReg();
469 if (Reg == SPU::R0) continue;
470 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
471 MachineLocation CSSrc(Reg);
472 Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc));
473 }
474
475 // Mark effective beginning of when frame pointer is ready.
476 MCSymbol *ReadyLabel = MMI.getContext().CreateTempSymbol();
477 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(ReadyLabel);
478
479 MachineLocation FPDst(SPU::R1);
480 MachineLocation FPSrc(MachineLocation::VirtualFP);
481 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
482 }
483 } else {
484 // This is a leaf function -- insert a branch hint iff there are
485 // sufficient number instructions in the basic block. Note that
486 // this is just a best guess based on the basic block's size.
487 if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
488 MachineBasicBlock::iterator MBBI = prior(MBB.end());
489 dl = MBBI->getDebugLoc();
490
491 // Insert terminator label
492 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL))
493 .addSym(MMI.getContext().CreateTempSymbol());
494 }
495 }
496 }
497
498 void
499 SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
500 {
501 MachineBasicBlock::iterator MBBI = prior(MBB.end());
502 const MachineFrameInfo *MFI = MF.getFrameInfo();
503 int FrameSize = MFI->getStackSize();
504 int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
505 DebugLoc dl = MBBI->getDebugLoc();
506
507 assert(MBBI->getOpcode() == SPU::RET &&
508 "Can only insert epilog into returning blocks");
509 assert((FrameSize & 0xf) == 0
510 && "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
511
512 // the "empty" frame size is 16 - just the register scavenger spill slot
513 if (FrameSize > 16 || MFI->adjustsStack()) {
514 FrameSize = FrameSize + SPUFrameInfo::minStackSize();
515 if (isInt<10>(FrameSize + LinkSlotOffset)) {
516 // Reload $lr, adjust $sp by required amount
517 // Note: We do this to slightly improve dual issue -- not by much, but it
518 // is an opportunity for dual issue.
519 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
520 .addImm(FrameSize + LinkSlotOffset)
521 .addReg(SPU::R1);
522 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1)
523 .addReg(SPU::R1)
524 .addImm(FrameSize);
525 } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
526 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
527 // $r2 to adjust $sp:
528 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
529 .addImm(16)
530 .addReg(SPU::R1);
531 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
532 .addImm(FrameSize);
533 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
534 .addReg(SPU::R1)
535 .addReg(SPU::R2);
536 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
537 .addImm(16)
538 .addReg(SPU::R1);
539 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2).
540 addReg(SPU::R2)
541 .addImm(16);
542 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
543 .addReg(SPU::R2)
544 .addReg(SPU::R1);
545 } else {
546 report_fatal_error("Unhandled frame size: " + Twine(FrameSize));
547 }
548 }
549 }
550
551 unsigned
552 SPURegisterInfo::getRARegister() const
553 {
554 return SPU::R0;
555 }
556
557 unsigned
558 SPURegisterInfo::getFrameRegister(const MachineFunction &MF) const
559 {
560 return SPU::R1;
561 }
562
563 void
564 SPURegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const
565 {
566 // Initial state of the frame pointer is R1.
567 MachineLocation Dst(MachineLocation::VirtualFP);
568 MachineLocation Src(SPU::R1, 0);
569 Moves.push_back(MachineMove(0, Dst, Src));
570 }
571
572
573 int
574 SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
575 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
576 return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
577 }
578
579 int
580 SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
581 {
582 switch(dFormOpcode)
583 {
584 case SPU::AIr32: return SPU::Ar32;
585 case SPU::LQDr32: return SPU::LQXr32;
586 case SPU::LQDr128: return SPU::LQXr128;
587 case SPU::LQDv16i8: return SPU::LQXv16i8;
588 case SPU::LQDv4i32: return SPU::LQXv4i32;
589 case SPU::LQDv4f32: return SPU::LQXv4f32;
590 case SPU::STQDr32: return SPU::STQXr32;
591 case SPU::STQDr128: return SPU::STQXr128;
592 case SPU::STQDv16i8: return SPU::STQXv16i8;
593 case SPU::STQDv4i32: return SPU::STQXv4i32;
594 case SPU::STQDv4f32: return SPU::STQXv4f32;
595
596 default: assert( false && "Unhandled D to X-form conversion");
597 }
598 // default will assert, but need to return something to keep the
599 // compiler happy.
600 return dFormOpcode;
601 }
602
603 // TODO this is already copied from PPC. Could this convenience function
604 // be moved to the RegScavenger class?
605 unsigned
606 SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
607 RegScavenger *RS,
608 const TargetRegisterClass *RC,
609 int SPAdj) const
610 {
611 assert(RS && "Register scavenging must be on");
612 unsigned Reg = RS->FindUnusedReg(RC);
613 if (Reg == 0)
614 Reg = RS->scavengeRegister(RC, II, SPAdj);
615 assert( Reg && "Register scavenger failed");
616 return Reg;
617 }
618
619 #include "SPUGenRegisterInfo.inc"
ZPU llvm backend wip