lib/Target/Mips/MipsISelDAGToDAG.cpp

   1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines an instruction selector for the MIPS target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "mips-isel"
  15 #include "Mips.h"
  16 #include "MipsMachineFunction.h"
  17 #include "MipsRegisterInfo.h"
  18 #include "MipsSubtarget.h"
  19 #include "MipsTargetMachine.h"
  20 #include "llvm/GlobalValue.h"
  21 #include "llvm/Instructions.h"
  22 #include "llvm/Intrinsics.h"
  23 #include "llvm/Support/CFG.h"
  24 #include "llvm/Type.h"
  25 #include "llvm/CodeGen/MachineConstantPool.h"
  26 #include "llvm/CodeGen/MachineFunction.h"
  27 #include "llvm/CodeGen/MachineFrameInfo.h"
  28 #include "llvm/CodeGen/MachineInstrBuilder.h"
  29 #include "llvm/CodeGen/MachineRegisterInfo.h"
  30 #include "llvm/CodeGen/SelectionDAGISel.h"
  31 #include "llvm/Target/TargetMachine.h"
  32 #include "llvm/Support/Debug.h"
  33 #include "llvm/Support/ErrorHandling.h"
  34 #include "llvm/Support/raw_ostream.h"
  35 using namespace llvm;
  36
  37 //===----------------------------------------------------------------------===//
  38 // Instruction Selector Implementation
  39 //===----------------------------------------------------------------------===//
  40
  41 //===----------------------------------------------------------------------===//
  42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
  43 // instructions for SelectionDAG operations.
  44 //===----------------------------------------------------------------------===//
  45 namespace {
  46
  47 class MipsDAGToDAGISel : public SelectionDAGISel {
  48
  49   /// TM - Keep a reference to MipsTargetMachine.
  50   MipsTargetMachine &TM;
  51
  52   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
  53   /// make the right decision when generating code for different targets.
  54   const MipsSubtarget &Subtarget;
  55
  56 public:
  57   explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
  58   SelectionDAGISel(tm),
  59   TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
  60
  61   // Pass Name
  62   virtual const char *getPassName() const {
  63     return "MIPS DAG->DAG Pattern Instruction Selection";
  64   }
  65
  66
  67 private:
  68   // Include the pieces autogenerated from the target description.
  69   #include "MipsGenDAGISel.inc"
  70
  71   /// getTargetMachine - Return a reference to the TargetMachine, casted
  72   /// to the target-specific type.
  73   const MipsTargetMachine &getTargetMachine() {
  74     return static_cast<const MipsTargetMachine &>(TM);
  75   }
  76
  77   /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
  78   /// to the target-specific type.
  79   const MipsInstrInfo *getInstrInfo() {
  80     return getTargetMachine().getInstrInfo();
  81   }
  82
  83   SDNode *getGlobalBaseReg();
  84   SDNode *Select(SDNode *N);
  85
  86   // Complex Pattern.
  87   bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
  88
  89   SDNode *SelectLoadFp64(SDNode *N);
  90   SDNode *SelectStoreFp64(SDNode *N);
  91
  92   // getI32Imm - Return a target constant with the specified
  93   // value, of type i32.
  94   inline SDValue getI32Imm(unsigned Imm) {
  95     return CurDAG->getTargetConstant(Imm, MVT::i32);
  96   }
  97 };
  98
  99 }
 100
 101
 102 /// getGlobalBaseReg - Output the instructions required to put the
 103 /// GOT address into a register.
 104 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
 105   unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
 106   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
 107 }
 108
 109 /// ComplexPattern used on MipsInstrInfo
 110 /// Used on Mips Load/Store instructions
 111 bool MipsDAGToDAGISel::
 112 SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
 113   // if Address is FI, get the TargetFrameIndex.
 114   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
 115     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
 116     Offset = CurDAG->getTargetConstant(0, MVT::i32);
 117     return true;
 118   }
 119
 120   // on PIC code Load GA
 121   if (TM.getRelocationModel() == Reloc::PIC_) {
 122     if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
 123         (Addr.getOpcode() == ISD::TargetConstantPool) ||
 124         (Addr.getOpcode() == ISD::TargetJumpTable)){
 125       Base   = CurDAG->getRegister(Mips::GP, MVT::i32);
 126       Offset = Addr;
 127       return true;
 128     }
 129   } else {
 130     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
 131         Addr.getOpcode() == ISD::TargetGlobalAddress))
 132       return false;
 133   }
 134
 135   // Operand is a result from an ADD.
 136   if (Addr.getOpcode() == ISD::ADD) {
 137     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
 138       if (isInt<16>(CN->getSExtValue())) {
 139
 140         // If the first operand is a FI, get the TargetFI Node
 141         if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
 142                                     (Addr.getOperand(0))) {
 143           Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
 144         } else {
 145           Base = Addr.getOperand(0);
 146         }
 147
 148         Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
 149         return true;
 150       }
 151     }
 152
 153     // When loading from constant pools, load the lower address part in
 154     // the instruction itself. Example, instead of:
 155     //  lui $2, %hi($CPI1_0)
 156     //  addiu $2, $2, %lo($CPI1_0)
 157     //  lwc1 $f0, 0($2)
 158     // Generate:
 159     //  lui $2, %hi($CPI1_0)
 160     //  lwc1 $f0, %lo($CPI1_0)($2)
 161     if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
 162          Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
 163         Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
 164       SDValue LoVal = Addr.getOperand(1);
 165       if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
 166         Base = Addr.getOperand(0);
 167         Offset = LoVal.getOperand(0);
 168         return true;
 169       }
 170     }
 171   }
 172
 173   Base   = Addr;
 174   Offset = CurDAG->getTargetConstant(0, MVT::i32);
 175   return true;
 176 }
 177
 178 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
 179   MVT::SimpleValueType NVT =
 180     N->getValueType(0).getSimpleVT().SimpleTy;
 181
 182   if (!Subtarget.isMips1() || NVT != MVT::f64)
 183     return NULL;
 184
 185   LoadSDNode *LN = cast<LoadSDNode>(N);
 186   if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
 187       LN->getAddressingMode() != ISD::UNINDEXED)
 188     return NULL;
 189
 190   SDValue Chain = N->getOperand(0);
 191   SDValue N1 = N->getOperand(1);
 192   SDValue Offset0, Offset1, Base;
 193
 194   if (!SelectAddr(N1, Offset0, Base) ||
 195       N1.getValueType() != MVT::i32)
 196     return NULL;
 197
 198   MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
 199   MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
 200   DebugLoc dl = N->getDebugLoc();
 201
 202   // The second load should start after for 4 bytes.
 203   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
 204     Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
 205   else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
 206     Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
 207                                             MVT::i32,
 208                                             CP->getAlignment(),
 209                                             CP->getOffset()+4,
 210                                             CP->getTargetFlags());
 211   else
 212     return NULL;
 213
 214   // Choose the offsets depending on the endianess
 215   if (TM.getTargetData()->isBigEndian())
 216     std::swap(Offset0, Offset1);
 217
 218   // Instead of:
 219   //    ldc $f0, X($3)
 220   // Generate:
 221   //    lwc $f0, X($3)
 222   //    lwc $f1, X+4($3)
 223   SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
 224                                     MVT::Other, Offset0, Base, Chain);
 225   SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
 226                                                  dl, NVT), 0);
 227   SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
 228                             MVT::f64, Undef, SDValue(LD0, 0));
 229
 230   SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
 231                           MVT::Other, Offset1, Base, SDValue(LD0, 1));
 232   SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
 233                             MVT::f64, I0, SDValue(LD1, 0));
 234
 235   ReplaceUses(SDValue(N, 0), I1);
 236   ReplaceUses(SDValue(N, 1), Chain);
 237   cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
 238   cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
 239   return I1.getNode();
 240 }
 241
 242 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
 243
 244   if (!Subtarget.isMips1() ||
 245       N->getOperand(1).getValueType() != MVT::f64)
 246     return NULL;
 247
 248   SDValue Chain = N->getOperand(0);
 249
 250   StoreSDNode *SN = cast<StoreSDNode>(N);
 251   if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
 252     return NULL;
 253
 254   SDValue N1 = N->getOperand(1);
 255   SDValue N2 = N->getOperand(2);
 256   SDValue Offset0, Offset1, Base;
 257
 258   if (!SelectAddr(N2, Offset0, Base) ||
 259       N1.getValueType() != MVT::f64 ||
 260       N2.getValueType() != MVT::i32)
 261     return NULL;
 262
 263   MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
 264   MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
 265   DebugLoc dl = N->getDebugLoc();
 266
 267   // Get the even and odd part from the f64 register
 268   SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
 269                                                  dl, MVT::f32, N1);
 270   SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
 271                                                  dl, MVT::f32, N1);
 272
 273   // The second store should start after for 4 bytes.
 274   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
 275     Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
 276   else
 277     return NULL;
 278
 279   // Choose the offsets depending on the endianess
 280   if (TM.getTargetData()->isBigEndian())
 281     std::swap(Offset0, Offset1);
 282
 283   // Instead of:
 284   //    sdc $f0, X($3)
 285   // Generate:
 286   //    swc $f0, X($3)
 287   //    swc $f1, X+4($3)
 288   SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
 289   Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
 290                                        MVT::Other, Ops0, 4), 0);
 291   cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
 292
 293   SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
 294   Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
 295                                        MVT::Other, Ops1, 4), 0);
 296   cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
 297
 298   ReplaceUses(SDValue(N, 0), Chain);
 299   return Chain.getNode();
 300 }
 301
 302 /// Select instructions not customized! Used for
 303 /// expanded, promoted and normal instructions
 304 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
 305   unsigned Opcode = Node->getOpcode();
 306   DebugLoc dl = Node->getDebugLoc();
 307
 308   // Dump information about the Node being selected
 309   DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
 310
 311   // If we have a custom node, we already have selected!
 312   if (Node->isMachineOpcode()) {
 313     DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
 314     return NULL;
 315   }
 316
 317   ///
 318   // Instruction Selection not handled by the auto-generated
 319   // tablegen selection should be handled here.
 320   ///
 321   switch(Opcode) {
 322
 323     default: break;
 324
 325     case ISD::SUBE:
 326     case ISD::ADDE: {
 327       SDValue InFlag = Node->getOperand(2), CmpLHS;
 328       unsigned Opc = InFlag.getOpcode(); Opc=Opc;
 329       assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
 330               (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
 331              "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
 332
 333       unsigned MOp;
 334       if (Opcode == ISD::ADDE) {
 335         CmpLHS = InFlag.getValue(0);
 336         MOp = Mips::ADDu;
 337       } else {
 338         CmpLHS = InFlag.getOperand(0);
 339         MOp = Mips::SUBu;
 340       }
 341
 342       SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
 343
 344       SDValue LHS = Node->getOperand(0);
 345       SDValue RHS = Node->getOperand(1);
 346
 347       EVT VT = LHS.getValueType();
 348       SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
 349       SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
 350                                                 SDValue(Carry,0), RHS);
 351
 352       return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Flag,
 353                                   LHS, SDValue(AddCarry,0));
 354     }
 355
 356     /// Mul/Div with two results
 357     case ISD::SDIVREM:
 358     case ISD::UDIVREM:
 359     case ISD::SMUL_LOHI:
 360     case ISD::UMUL_LOHI: {
 361       SDValue Op1 = Node->getOperand(0);
 362       SDValue Op2 = Node->getOperand(1);
 363
 364       unsigned Op;
 365       if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
 366         Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
 367       else
 368         Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
 369
 370       SDNode *MulDiv = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
 371
 372       SDValue InFlag = SDValue(MulDiv, 0);
 373       SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
 374                                           MVT::Flag, InFlag);
 375       InFlag = SDValue(Lo,1);
 376       SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
 377
 378       if (!SDValue(Node, 0).use_empty())
 379         ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
 380
 381       if (!SDValue(Node, 1).use_empty())
 382         ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
 383
 384       return NULL;
 385     }
 386
 387     /// Special Muls
 388     case ISD::MUL:
 389     case ISD::MULHS:
 390     case ISD::MULHU: {
 391       SDValue MulOp1 = Node->getOperand(0);
 392       SDValue MulOp2 = Node->getOperand(1);
 393
 394       unsigned MulOp  = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
 395       SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
 396                                                MVT::Flag, MulOp1, MulOp2);
 397
 398       SDValue InFlag = SDValue(MulNode, 0);
 399
 400       if (Opcode == ISD::MUL)
 401         return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
 402       else
 403         return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
 404     }
 405
 406     /// Div/Rem operations
 407     case ISD::SREM:
 408     case ISD::UREM:
 409     case ISD::SDIV:
 410     case ISD::UDIV: {
 411       SDValue Op1 = Node->getOperand(0);
 412       SDValue Op2 = Node->getOperand(1);
 413
 414       unsigned Op, MOp;
 415       if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
 416         Op  = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
 417         MOp = Mips::MFLO;
 418       } else {
 419         Op  = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
 420         MOp = Mips::MFHI;
 421       }
 422       SDNode *Node = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
 423
 424       SDValue InFlag = SDValue(Node, 0);
 425       return CurDAG->getMachineNode(MOp, dl, MVT::i32, InFlag);
 426     }
 427
 428     // Get target GOT address.
 429     case ISD::GLOBAL_OFFSET_TABLE:
 430       return getGlobalBaseReg();
 431
 432     case ISD::ConstantFP: {
 433       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
 434       if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
 435         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
 436                                         Mips::ZERO, MVT::i32);
 437         SDValue Undef = SDValue(
 438           CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
 439         SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
 440         SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
 441                             MVT::f64, Undef, SDValue(MTC, 0));
 442         SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
 443                             MVT::f64, I0, SDValue(MTC, 0));
 444         ReplaceUses(SDValue(Node, 0), I1);
 445         return I1.getNode();
 446       }
 447       break;
 448     }
 449
 450     case ISD::LOAD:
 451       if (SDNode *ResNode = SelectLoadFp64(Node))
 452         return ResNode;
 453       // Other cases are autogenerated.
 454       break;
 455
 456     case ISD::STORE:
 457       if (SDNode *ResNode = SelectStoreFp64(Node))
 458         return ResNode;
 459       // Other cases are autogenerated.
 460       break;
 461
 462     /// Handle direct and indirect calls when using PIC. On PIC, when
 463     /// GOT is smaller than about 64k (small code) the GA target is
 464     /// loaded with only one instruction. Otherwise GA's target must
 465     /// be loaded with 3 instructions.
 466     case MipsISD::JmpLink: {
 467       if (TM.getRelocationModel() == Reloc::PIC_) {
 468         unsigned LastOpNum = Node->getNumOperands()-1;
 469
 470         SDValue Chain  = Node->getOperand(0);
 471         SDValue Callee = Node->getOperand(1);
 472         SDValue InFlag;
 473
 474         // Skip the incomming flag if present
 475         if (Node->getOperand(LastOpNum).getValueType() == MVT::Flag)
 476           LastOpNum--;
 477
 478         if ( (isa<GlobalAddressSDNode>(Callee)) ||
 479              (isa<ExternalSymbolSDNode>(Callee)) )
 480         {
 481           /// Direct call for global addresses and external symbols
 482           SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
 483
 484           // Use load to get GOT target
 485           SDValue Ops[] = { Callee, GPReg, Chain };
 486           SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
 487                                      MVT::Other, Ops, 3), 0);
 488           Chain = Load.getValue(1);
 489
 490           // Call target must be on T9
 491           Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Load, InFlag);
 492         } else
 493           /// Indirect call
 494           Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Callee, InFlag);
 495
 496         // Map the JmpLink operands to JALR
 497         SDVTList NodeTys = CurDAG->getVTList(MVT::Other, MVT::Flag);
 498         SmallVector<SDValue, 8> Ops;
 499         Ops.push_back(CurDAG->getRegister(Mips::T9, MVT::i32));
 500
 501         for (unsigned i = 2, e = LastOpNum+1; i != e; ++i)
 502           Ops.push_back(Node->getOperand(i));
 503         Ops.push_back(Chain);
 504         Ops.push_back(Chain.getValue(1));
 505
 506         // Emit Jump and Link Register
 507         SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
 508                                   &Ops[0], Ops.size());
 509
 510         // Replace Chain and InFlag
 511         ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
 512         ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 1));
 513         return ResNode;
 514       }
 515     }
 516   }
 517
 518   // Select the default instruction
 519   SDNode *ResNode = SelectCode(Node);
 520
 521   DEBUG(errs() << "=> ");
 522   if (ResNode == NULL || ResNode == Node)
 523     DEBUG(Node->dump(CurDAG));
 524   else
 525     DEBUG(ResNode->dump(CurDAG));
 526   DEBUG(errs() << "\n");
 527   return ResNode;
 528 }
 529
 530 /// createMipsISelDag - This pass converts a legalized DAG into a
 531 /// MIPS-specific DAG, ready for instruction scheduling.
 532 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
 533   return new MipsDAGToDAGISel(TM);
 534 }