lib/Target/Mips/MipsISelLowering.h

   1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that Mips uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef MipsISELLOWERING_H
  16 #define MipsISELLOWERING_H
  17
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/Target/TargetLowering.h"
  20 #include "Mips.h"
  21 #include "MipsSubtarget.h"
  22
  23 namespace llvm {
  24   namespace MipsISD {
  25     enum NodeType {
  26       // Start the numbering from where ISD NodeType finishes.
  27       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  28
  29       // Jump and link (call)
  30       JmpLink,
  31
  32       // Get the Higher 16 bits from a 32-bit immediate
  33       // No relation with Mips Hi register
  34       Hi,
  35
  36       // Get the Lower 16 bits from a 32-bit immediate
  37       // No relation with Mips Lo register
  38       Lo,
  39
  40       // Handle gp_rel (small data/bss sections) relocation.
  41       GPRel,
  42
  43       // Conditional Move
  44       CMov,
  45
  46       // Select CC Pseudo Instruction
  47       SelectCC,
  48
  49       // Floating Point Select CC Pseudo Instruction
  50       FPSelectCC,
  51
  52       // Floating Point Branch Conditional
  53       FPBrcond,
  54
  55       // Floating Point Compare
  56       FPCmp,
  57
  58       // Floating Point Rounding
  59       FPRound,
  60
  61       // Return
  62       Ret
  63     };
  64   }
  65
  66   //===--------------------------------------------------------------------===//
  67   // TargetLowering Implementation
  68   //===--------------------------------------------------------------------===//
  69
  70   class MipsTargetLowering : public TargetLowering  {
  71   public:
  72     explicit MipsTargetLowering(MipsTargetMachine &TM);
  73
  74     /// LowerOperation - Provide custom lowering hooks for some operations.
  75     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  76
  77     /// getTargetNodeName - This method returns the name of a target specific
  78     //  DAG node.
  79     virtual const char *getTargetNodeName(unsigned Opcode) const;
  80
  81     /// getSetCCResultType - get the ISD::SETCC result ValueType
  82     MVT::SimpleValueType getSetCCResultType(EVT VT) const;
  83
  84     /// getFunctionAlignment - Return the Log2 alignment of this function.
  85     virtual unsigned getFunctionAlignment(const Function *F) const;
  86   private:
  87     // Subtarget Info
  88     const MipsSubtarget *Subtarget;
  89
  90
  91     // Lower Operand helpers
  92     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
  93                             CallingConv::ID CallConv, bool isVarArg,
  94                             const SmallVectorImpl<ISD::InputArg> &Ins,
  95                             DebugLoc dl, SelectionDAG &DAG,
  96                             SmallVectorImpl<SDValue> &InVals) const;
  97
  98     // Lower Operand specifics
  99     SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG) const;
 100     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 101     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 102     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 103     SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
 104     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 105     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 106     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 107     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 108     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 109     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 110
 111     virtual SDValue
 112       LowerFormalArguments(SDValue Chain,
 113                            CallingConv::ID CallConv, bool isVarArg,
 114                            const SmallVectorImpl<ISD::InputArg> &Ins,
 115                            DebugLoc dl, SelectionDAG &DAG,
 116                            SmallVectorImpl<SDValue> &InVals) const;
 117
 118     virtual SDValue
 119       LowerCall(SDValue Chain, SDValue Callee,
 120                 CallingConv::ID CallConv, bool isVarArg,
 121                 bool &isTailCall,
 122                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 123                 const SmallVectorImpl<SDValue> &OutVals,
 124                 const SmallVectorImpl<ISD::InputArg> &Ins,
 125                 DebugLoc dl, SelectionDAG &DAG,
 126                 SmallVectorImpl<SDValue> &InVals) const;
 127
 128     virtual SDValue
 129       LowerReturn(SDValue Chain,
 130                   CallingConv::ID CallConv, bool isVarArg,
 131                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 132                   const SmallVectorImpl<SDValue> &OutVals,
 133                   DebugLoc dl, SelectionDAG &DAG) const;
 134
 135     virtual MachineBasicBlock *
 136       EmitInstrWithCustomInserter(MachineInstr *MI,
 137                                   MachineBasicBlock *MBB) const;
 138
 139     // Inline asm support
 140     ConstraintType getConstraintType(const std::string &Constraint) const;
 141
 142     /// Examine constraint string and operand type and determine a weight value.
 143     /// The operand object must already have been set up with the operand type.
 144     ConstraintWeight getSingleConstraintMatchWeight(
 145       AsmOperandInfo &info, const char *constraint) const;
 146
 147     std::pair<unsigned, const TargetRegisterClass*>
 148               getRegForInlineAsmConstraint(const std::string &Constraint,
 149               EVT VT) const;
 150
 151     std::vector<unsigned>
 152     getRegClassForInlineAsmConstraint(const std::string &Constraint,
 153               EVT VT) const;
 154
 155     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
 156
 157     /// isFPImmLegal - Returns true if the target can instruction select the
 158     /// specified FP immediate natively. If false, the legalizer will
 159     /// materialize the FP immediate as a load from a constant pool.
 160     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
 161   };
 162 }
 163
 164 #endif // MipsISELLOWERING_H