lib/Target/PowerPC/PPCInstrInfo.h

   1 //===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef POWERPC32_INSTRUCTIONINFO_H
  15 #define POWERPC32_INSTRUCTIONINFO_H
  16
  17 #include "PPC.h"
  18 #include "llvm/Target/TargetInstrInfo.h"
  19 #include "PPCRegisterInfo.h"
  20
  21 namespace llvm {
  22
  23 /// PPCII - This namespace holds all of the PowerPC target-specific
  24 /// per-instruction flags.  These must match the corresponding definitions in
  25 /// PPC.td and PPCInstrFormats.td.
  26 namespace PPCII {
  27 enum {
  28   // PPC970 Instruction Flags.  These flags describe the characteristics of the
  29   // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
  30   // raw machine instructions.
  31
  32   /// PPC970_First - This instruction starts a new dispatch group, so it will
  33   /// always be the first one in the group.
  34   PPC970_First = 0x1,
  35
  36   /// PPC970_Single - This instruction starts a new dispatch group and
  37   /// terminates it, so it will be the sole instruction in the group.
  38   PPC970_Single = 0x2,
  39
  40   /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
  41   /// two dispatch pipes to be available to issue.
  42   PPC970_Cracked = 0x4,
  43
  44   /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
  45   /// an instruction is issued to.
  46   PPC970_Shift = 3,
  47   PPC970_Mask = 0x07 << PPC970_Shift
  48 };
  49 enum PPC970_Unit {
  50   /// These are the various PPC970 execution unit pipelines.  Each instruction
  51   /// is one of these.
  52   PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
  53   PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
  54   PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
  55   PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
  56   PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
  57   PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
  58   PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
  59   PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
  60 };
  61 }
  62
  63
  64 class PPCInstrInfo : public TargetInstrInfoImpl {
  65   PPCTargetMachine &TM;
  66   const PPCRegisterInfo RI;
  67
  68   bool StoreRegToStackSlot(MachineFunction &MF,
  69                            unsigned SrcReg, bool isKill, int FrameIdx,
  70                            const TargetRegisterClass *RC,
  71                            SmallVectorImpl<MachineInstr*> &NewMIs) const;
  72   void LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
  73                             unsigned DestReg, int FrameIdx,
  74                             const TargetRegisterClass *RC,
  75                             SmallVectorImpl<MachineInstr*> &NewMIs) const;
  76 public:
  77   explicit PPCInstrInfo(PPCTargetMachine &TM);
  78
  79   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  80   /// such, whenever a client has an instance of instruction info, it should
  81   /// always be able to get register info as well (through this method).
  82   ///
  83   virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
  84
  85   unsigned isLoadFromStackSlot(const MachineInstr *MI,
  86                                int &FrameIndex) const;
  87   unsigned isStoreToStackSlot(const MachineInstr *MI,
  88                               int &FrameIndex) const;
  89
  90   // commuteInstruction - We can commute rlwimi instructions, but only if the
  91   // rotate amt is zero.  We also have to munge the immediates a bit.
  92   virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
  93
  94   virtual void insertNoop(MachineBasicBlock &MBB,
  95                           MachineBasicBlock::iterator MI) const;
  96
  97
  98   // Branch analysis.
  99   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 100                              MachineBasicBlock *&FBB,
 101                              SmallVectorImpl<MachineOperand> &Cond,
 102                              bool AllowModify) const;
 103   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
 104   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 105                                 MachineBasicBlock *FBB,
 106                                 const SmallVectorImpl<MachineOperand> &Cond,
 107                                 DebugLoc DL) const;
 108   virtual void copyPhysReg(MachineBasicBlock &MBB,
 109                            MachineBasicBlock::iterator I, DebugLoc DL,
 110                            unsigned DestReg, unsigned SrcReg,
 111                            bool KillSrc) const;
 112
 113   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
 114                                    MachineBasicBlock::iterator MBBI,
 115                                    unsigned SrcReg, bool isKill, int FrameIndex,
 116                                    const TargetRegisterClass *RC,
 117                                    const TargetRegisterInfo *TRI) const;
 118
 119   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
 120                                     MachineBasicBlock::iterator MBBI,
 121                                     unsigned DestReg, int FrameIndex,
 122                                     const TargetRegisterClass *RC,
 123                                     const TargetRegisterInfo *TRI) const;
 124
 125   virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
 126                                                  int FrameIx,
 127                                                  uint64_t Offset,
 128                                                  const MDNode *MDPtr,
 129                                                  DebugLoc DL) const;
 130
 131   virtual
 132   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 133
 134   /// GetInstSize - Return the number of bytes of code the specified
 135   /// instruction may be.  This returns the maximum number of bytes.
 136   ///
 137   virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
 138 };
 139
 140 }
 141
 142 #endif