lib/Target/Sparc/SparcRegisterInfo.cpp

   1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Sparc.h"
  15 #include "SparcRegisterInfo.h"
  16 #include "SparcSubtarget.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineLocation.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/Target/TargetInstrInfo.h"
  23 #include "llvm/Type.h"
  24 #include "llvm/ADT/BitVector.h"
  25 #include "llvm/ADT/STLExtras.h"
  26 using namespace llvm;
  27
  28 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
  29                                      const TargetInstrInfo &tii)
  30   : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
  31     Subtarget(st), TII(tii) {
  32 }
  33
  34 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
  35                                                                          const {
  36   static const unsigned CalleeSavedRegs[] = { 0 };
  37   return CalleeSavedRegs;
  38 }
  39
  40 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  41   BitVector Reserved(getNumRegs());
  42   Reserved.set(SP::G2);
  43   Reserved.set(SP::G3);
  44   Reserved.set(SP::G4);
  45   Reserved.set(SP::O6);
  46   Reserved.set(SP::I6);
  47   Reserved.set(SP::I7);
  48   Reserved.set(SP::G0);
  49   Reserved.set(SP::G5);
  50   Reserved.set(SP::G6);
  51   Reserved.set(SP::G7);
  52   return Reserved;
  53 }
  54
  55 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
  56   return false;
  57 }
  58
  59 void SparcRegisterInfo::
  60 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
  61                               MachineBasicBlock::iterator I) const {
  62   MachineInstr &MI = *I;
  63   DebugLoc dl = MI.getDebugLoc();
  64   int Size = MI.getOperand(0).getImm();
  65   if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
  66     Size = -Size;
  67   if (Size)
  68     BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
  69   MBB.erase(I);
  70 }
  71
  72 void
  73 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
  74                                        int SPAdj, RegScavenger *RS) const {
  75   assert(SPAdj == 0 && "Unexpected");
  76
  77   unsigned i = 0;
  78   MachineInstr &MI = *II;
  79   DebugLoc dl = MI.getDebugLoc();
  80   while (!MI.getOperand(i).isFI()) {
  81     ++i;
  82     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
  83   }
  84
  85   int FrameIndex = MI.getOperand(i).getIndex();
  86
  87   // Addressable stack objects are accessed using neg. offsets from %fp
  88   MachineFunction &MF = *MI.getParent()->getParent();
  89   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
  90                MI.getOperand(i+1).getImm();
  91
  92   // Replace frame index with a frame pointer reference.
  93   if (Offset >= -4096 && Offset <= 4095) {
  94     // If the offset is small enough to fit in the immediate field, directly
  95     // encode it.
  96     MI.getOperand(i).ChangeToRegister(SP::I6, false);
  97     MI.getOperand(i+1).ChangeToImmediate(Offset);
  98   } else {
  99     // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
 100     // scavenge a register here instead of reserving G1 all of the time.
 101     unsigned OffHi = (unsigned)Offset >> 10U;
 102     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
 103     // Emit G1 = G1 + I6
 104     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
 105       .addReg(SP::I6);
 106     // Insert: G1+%lo(offset) into the user.
 107     MI.getOperand(i).ChangeToRegister(SP::G1, false);
 108     MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
 109   }
 110 }
 111
 112 void SparcRegisterInfo::
 113 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
 114
 115 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
 116   MachineBasicBlock &MBB = MF.front();
 117   MachineFrameInfo *MFI = MF.getFrameInfo();
 118   MachineBasicBlock::iterator MBBI = MBB.begin();
 119   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
 120
 121   // Get the number of bytes to allocate from the FrameInfo
 122   int NumBytes = (int) MFI->getStackSize();
 123
 124   // Emit the correct save instruction based on the number of bytes in
 125   // the frame. Minimum stack frame size according to V8 ABI is:
 126   //   16 words for register window spill
 127   //    1 word for address of returned aggregate-value
 128   // +  6 words for passing parameters on the stack
 129   // ----------
 130   //   23 words * 4 bytes per word = 92 bytes
 131   NumBytes += 92;
 132
 133   // Round up to next doubleword boundary -- a double-word boundary
 134   // is required by the ABI.
 135   NumBytes = (NumBytes + 7) & ~7;
 136   NumBytes = -NumBytes;
 137
 138   if (NumBytes >= -4096) {
 139     BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
 140       .addReg(SP::O6).addImm(NumBytes);
 141   } else {
 142     // Emit this the hard way.  This clobbers G1 which we always know is
 143     // available here.
 144     unsigned OffHi = (unsigned)NumBytes >> 10U;
 145     BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
 146     // Emit G1 = G1 + I6
 147     BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
 148       .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
 149     BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
 150       .addReg(SP::O6).addReg(SP::G1);
 151   }
 152 }
 153
 154 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
 155                                      MachineBasicBlock &MBB) const {
 156   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 157   DebugLoc dl = MBBI->getDebugLoc();
 158   assert(MBBI->getOpcode() == SP::RETL &&
 159          "Can only put epilog before 'retl' instruction!");
 160   BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
 161     .addReg(SP::G0);
 162 }
 163
 164 unsigned SparcRegisterInfo::getRARegister() const {
 165   return SP::I7;
 166 }
 167
 168 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 169   return SP::I6;
 170 }
 171
 172 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
 173   llvm_unreachable("What is the exception register");
 174   return 0;
 175 }
 176
 177 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
 178   llvm_unreachable("What is the exception handler register");
 179   return 0;
 180 }
 181
 182 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 183   return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
 184 }
 185
 186 #include "SparcGenRegisterInfo.inc"
 187