lib/Target/X86/X86Subtarget.cpp

   1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the X86 specific subclass of TargetSubtarget.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "subtarget"
  15 #include "X86Subtarget.h"
  16 #include "X86InstrInfo.h"
  17 #include "X86GenSubtarget.inc"
  18 #include "llvm/GlobalValue.h"
  19 #include "llvm/Support/Debug.h"
  20 #include "llvm/Support/raw_ostream.h"
  21 #include "llvm/System/Host.h"
  22 #include "llvm/Target/TargetMachine.h"
  23 #include "llvm/Target/TargetOptions.h"
  24 #include "llvm/ADT/SmallVector.h"
  25 using namespace llvm;
  26
  27 #if defined(_MSC_VER)
  28 #include <intrin.h>
  29 #endif
  30
  31 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
  32 /// current subtarget according to how we should reference it in a non-pcrel
  33 /// context.
  34 unsigned char X86Subtarget::
  35 ClassifyBlockAddressReference() const {
  36   if (isPICStyleGOT())    // 32-bit ELF targets.
  37     return X86II::MO_GOTOFF;
  38
  39   if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
  40     return X86II::MO_PIC_BASE_OFFSET;
  41
  42   // Direct static reference to label.
  43   return X86II::MO_NO_FLAG;
  44 }
  45
  46 /// ClassifyGlobalReference - Classify a global variable reference for the
  47 /// current subtarget according to how we should reference it in a non-pcrel
  48 /// context.
  49 unsigned char X86Subtarget::
  50 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
  51   // DLLImport only exists on windows, it is implemented as a load from a
  52   // DLLIMPORT stub.
  53   if (GV->hasDLLImportLinkage())
  54     return X86II::MO_DLLIMPORT;
  55
  56   // Determine whether this is a reference to a definition or a declaration.
  57   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
  58   // load from stub.
  59   bool isDecl = GV->hasAvailableExternallyLinkage();
  60   if (GV->isDeclaration() && !GV->isMaterializable())
  61     isDecl = true;
  62
  63   // X86-64 in PIC mode.
  64   if (isPICStyleRIPRel()) {
  65     // Large model never uses stubs.
  66     if (TM.getCodeModel() == CodeModel::Large)
  67       return X86II::MO_NO_FLAG;
  68
  69     if (isTargetDarwin()) {
  70       // If symbol visibility is hidden, the extra load is not needed if
  71       // target is x86-64 or the symbol is definitely defined in the current
  72       // translation unit.
  73       if (GV->hasDefaultVisibility() &&
  74           (isDecl || GV->isWeakForLinker()))
  75         return X86II::MO_GOTPCREL;
  76     } else if (!isTargetWin64()) {
  77       assert(isTargetELF() && "Unknown rip-relative target");
  78
  79       // Extra load is needed for all externally visible.
  80       if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
  81         return X86II::MO_GOTPCREL;
  82     }
  83
  84     return X86II::MO_NO_FLAG;
  85   }
  86
  87   if (isPICStyleGOT()) {   // 32-bit ELF targets.
  88     // Extra load is needed for all externally visible.
  89     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
  90       return X86II::MO_GOTOFF;
  91     return X86II::MO_GOT;
  92   }
  93
  94   if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
  95     // Determine whether we have a stub reference and/or whether the reference
  96     // is relative to the PIC base or not.
  97
  98     // If this is a strong reference to a definition, it is definitely not
  99     // through a stub.
 100     if (!isDecl && !GV->isWeakForLinker())
 101       return X86II::MO_PIC_BASE_OFFSET;
 102
 103     // Unless we have a symbol with hidden visibility, we have to go through a
 104     // normal $non_lazy_ptr stub because this symbol might be resolved late.
 105     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
 106       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
 107
 108     // If symbol visibility is hidden, we have a stub for common symbol
 109     // references and external declarations.
 110     if (isDecl || GV->hasCommonLinkage()) {
 111       // Hidden $non_lazy_ptr reference.
 112       return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
 113     }
 114
 115     // Otherwise, no stub.
 116     return X86II::MO_PIC_BASE_OFFSET;
 117   }
 118
 119   if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
 120     // Determine whether we have a stub reference.
 121
 122     // If this is a strong reference to a definition, it is definitely not
 123     // through a stub.
 124     if (!isDecl && !GV->isWeakForLinker())
 125       return X86II::MO_NO_FLAG;
 126
 127     // Unless we have a symbol with hidden visibility, we have to go through a
 128     // normal $non_lazy_ptr stub because this symbol might be resolved late.
 129     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
 130       return X86II::MO_DARWIN_NONLAZY;
 131
 132     // Otherwise, no stub.
 133     return X86II::MO_NO_FLAG;
 134   }
 135
 136   // Direct static reference to global.
 137   return X86II::MO_NO_FLAG;
 138 }
 139
 140
 141 /// getBZeroEntry - This function returns the name of a function which has an
 142 /// interface like the non-standard bzero function, if such a function exists on
 143 /// the current subtarget and it is considered prefereable over memset with zero
 144 /// passed as the second argument. Otherwise it returns null.
 145 const char *X86Subtarget::getBZeroEntry() const {
 146   // Darwin 10 has a __bzero entry point for this purpose.
 147   if (getDarwinVers() >= 10)
 148     return "__bzero";
 149
 150   return 0;
 151 }
 152
 153 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
 154 /// to immediate address.
 155 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
 156   if (Is64Bit)
 157     return false;
 158   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
 159 }
 160
 161 /// getSpecialAddressLatency - For targets where it is beneficial to
 162 /// backschedule instructions that compute addresses, return a value
 163 /// indicating the number of scheduling cycles of backscheduling that
 164 /// should be attempted.
 165 unsigned X86Subtarget::getSpecialAddressLatency() const {
 166   // For x86 out-of-order targets, back-schedule address computations so
 167   // that loads and stores aren't blocked.
 168   // This value was chosen arbitrarily.
 169   return 200;
 170 }
 171
 172 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
 173 /// specified arguments.  If we can't run cpuid on the host, return true.
 174 static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
 175                             unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
 176 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
 177   #if defined(__GNUC__)
 178     // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
 179     asm ("movq\t%%rbx, %%rsi\n\t"
 180          "cpuid\n\t"
 181          "xchgq\t%%rbx, %%rsi\n\t"
 182          : "=a" (*rEAX),
 183            "=S" (*rEBX),
 184            "=c" (*rECX),
 185            "=d" (*rEDX)
 186          :  "a" (value));
 187     return false;
 188   #elif defined(_MSC_VER)
 189     int registers[4];
 190     __cpuid(registers, value);
 191     *rEAX = registers[0];
 192     *rEBX = registers[1];
 193     *rECX = registers[2];
 194     *rEDX = registers[3];
 195     return false;
 196   #endif
 197 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
 198   #if defined(__GNUC__)
 199     asm ("movl\t%%ebx, %%esi\n\t"
 200          "cpuid\n\t"
 201          "xchgl\t%%ebx, %%esi\n\t"
 202          : "=a" (*rEAX),
 203            "=S" (*rEBX),
 204            "=c" (*rECX),
 205            "=d" (*rEDX)
 206          :  "a" (value));
 207     return false;
 208   #elif defined(_MSC_VER)
 209     __asm {
 210       mov   eax,value
 211       cpuid
 212       mov   esi,rEAX
 213       mov   dword ptr [esi],eax
 214       mov   esi,rEBX
 215       mov   dword ptr [esi],ebx
 216       mov   esi,rECX
 217       mov   dword ptr [esi],ecx
 218       mov   esi,rEDX
 219       mov   dword ptr [esi],edx
 220     }
 221     return false;
 222   #endif
 223 #endif
 224   return true;
 225 }
 226
 227 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
 228   Family = (EAX >> 8) & 0xf; // Bits 8 - 11
 229   Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
 230   if (Family == 6 || Family == 0xf) {
 231     if (Family == 0xf)
 232       // Examine extended family ID if family ID is F.
 233       Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
 234     // Examine extended model ID if family ID is 6 or F.
 235     Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
 236   }
 237 }
 238
 239 void X86Subtarget::AutoDetectSubtargetFeatures() {
 240   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
 241   union {
 242     unsigned u[3];
 243     char     c[12];
 244   } text;
 245
 246   if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
 247     return;
 248
 249   GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
 250
 251   if ((EDX >> 15) & 1) HasCMov = true;
 252   if ((EDX >> 23) & 1) X86SSELevel = MMX;
 253   if ((EDX >> 25) & 1) X86SSELevel = SSE1;
 254   if ((EDX >> 26) & 1) X86SSELevel = SSE2;
 255   if (ECX & 0x1)       X86SSELevel = SSE3;
 256   if ((ECX >> 9)  & 1) X86SSELevel = SSSE3;
 257   if ((ECX >> 19) & 1) X86SSELevel = SSE41;
 258   if ((ECX >> 20) & 1) X86SSELevel = SSE42;
 259
 260   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
 261   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
 262
 263   HasCLMUL = IsIntel && ((ECX >> 1) & 0x1);
 264   HasFMA3  = IsIntel && ((ECX >> 12) & 0x1);
 265   HasAVX   = ((ECX >> 28) & 0x1);
 266   HasAES   = IsIntel && ((ECX >> 25) & 0x1);
 267
 268   if (IsIntel || IsAMD) {
 269     // Determine if bit test memory instructions are slow.
 270     unsigned Family = 0;
 271     unsigned Model  = 0;
 272     DetectFamilyModel(EAX, Family, Model);
 273     IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
 274     // If it's Nehalem, unaligned memory access is fast.
 275     if (Family == 15 && Model == 26)
 276       IsUAMemFast = true;
 277
 278     GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
 279     HasX86_64 = (EDX >> 29) & 0x1;
 280     HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
 281     HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
 282   }
 283 }
 284
 285 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
 286                            bool is64Bit)
 287   : PICStyle(PICStyles::None)
 288   , X86SSELevel(NoMMXSSE)
 289   , X863DNowLevel(NoThreeDNow)
 290   , HasCMov(false)
 291   , HasX86_64(false)
 292   , HasSSE4A(false)
 293   , HasAVX(false)
 294   , HasAES(false)
 295   , HasCLMUL(false)
 296   , HasFMA3(false)
 297   , HasFMA4(false)
 298   , IsBTMemSlow(false)
 299   , IsUAMemFast(false)
 300   , HasVectorUAMem(false)
 301   , stackAlignment(8)
 302   // FIXME: this is a known good value for Yonah. How about others?
 303   , MaxInlineSizeThreshold(128)
 304   , TargetTriple(TT)
 305   , Is64Bit(is64Bit) {
 306
 307   // default to hard float ABI
 308   if (FloatABIType == FloatABI::Default)
 309     FloatABIType = FloatABI::Hard;
 310
 311   // Determine default and user specified characteristics
 312   if (!FS.empty()) {
 313     // If feature string is not empty, parse features string.
 314     std::string CPU = sys::getHostCPUName();
 315     ParseSubtargetFeatures(FS, CPU);
 316     // All X86-64 CPUs also have SSE2, however user might request no SSE via
 317     // -mattr, so don't force SSELevel here.
 318   } else {
 319     // Otherwise, use CPUID to auto-detect feature set.
 320     AutoDetectSubtargetFeatures();
 321     // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
 322     if (Is64Bit && X86SSELevel < SSE2)
 323       X86SSELevel = SSE2;
 324   }
 325
 326   // If requesting codegen for X86-64, make sure that 64-bit features
 327   // are enabled.
 328   if (Is64Bit) {
 329     HasX86_64 = true;
 330
 331     // All 64-bit cpus have cmov support.
 332     HasCMov = true;
 333   }
 334
 335   DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
 336                << ", 3DNowLevel " << X863DNowLevel
 337                << ", 64bit " << HasX86_64 << "\n");
 338   assert((!Is64Bit || HasX86_64) &&
 339          "64-bit code requested on a subtarget that doesn't support it!");
 340
 341   // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
 342   // bit targets.
 343   if (isTargetDarwin() || Is64Bit)
 344     stackAlignment = 16;
 345
 346   if (StackAlignment)
 347     stackAlignment = StackAlignment;
 348 }
 349
 350 /// IsCalleePop - Determines whether the callee is required to pop its
 351 /// own arguments. Callee pop is necessary to support tail calls.
 352 bool X86Subtarget::IsCalleePop(bool IsVarArg,
 353                                CallingConv::ID CallingConv) const {
 354   if (IsVarArg)
 355     return false;
 356
 357   switch (CallingConv) {
 358   default:
 359     return false;
 360   case CallingConv::X86_StdCall:
 361     return !is64Bit();
 362   case CallingConv::X86_FastCall:
 363     return !is64Bit();
 364   case CallingConv::X86_ThisCall:
 365     return !is64Bit();
 366   case CallingConv::Fast:
 367     return GuaranteedTailCallOpt;
 368   case CallingConv::GHC:
 369     return GuaranteedTailCallOpt;
 370   }
 371 }