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Fixed some bugs.
[llvm/zpu.git]
/
test
/
CodeGen
/
X86
/
shift-i256.ll
blob
d5f65a6ed18cd30926181e83c4c45c0108dd2b09
1
; RUN: llc < %s -march=x86
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; RUN: llc < %s -march=x86-64
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define void @t(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
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entry:
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%0 = ashr i256 %x, %a
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store i256 %0, i256* %r
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ret void
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}