1 ;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
4 ;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
5 ; should run on .s source files rather than using llc to generate the
6 ; assembly. There's also a large number of instruction encodings the
7 ; compiler never generates, so we need the integrated assembler to be
8 ; able to test those at all.
10 declare void @llvm.trap() nounwind
11 declare i32 @llvm.ctlz.i32(i32)
13 define i32 @foo(i32 %a, i32 %b) {
15 ; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07]
16 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
18 tail call void @llvm.trap()
22 define i32 @f2(i32 %a, i32 %b) {
24 ; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0]
25 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
26 %add = add nsw i32 %b, %a
31 define i32 @f3(i32 %a, i32 %b) {
33 ; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0]
34 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
36 %add = add nsw i32 %mul, %a
40 define i32 @f4(i32 %a, i32 %b) {
42 ; CHECK: add r0, r0, #254, 28 @ encoding: [0xfe,0x0e,0x80,0xe2]
44 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
45 %add = add nsw i32 %a, 4064
49 define i32 @f5(i32 %a, i32 %b, i32 %c) {
51 ; CHECK: cmp r0, r1 @ encoding: [0x01,0x00,0x50,0xe1]
52 ; CHECK: mov r0, r2 @ encoding: [0x02,0x00,0xa0,0xe1]
53 ; CHECK: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1]
54 %cmp = icmp sgt i32 %a, %b
55 %retval.0 = select i1 %cmp, i32 %b, i32 %c
59 define i64 @f6(i64 %a, i64 %b, i64 %c) {
61 ; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0]
62 ; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0]
63 %add = add nsw i64 %b, %a
67 define i32 @f7(i32 %a, i32 %b) {
69 ; CHECK: uxtab r0, r0, r1 @ encoding: [0x71,0x00,0xe0,0xe6]
70 %and = and i32 %b, 255
71 %add = add i32 %and, %a
75 define i32 @f8(i32 %a) {
77 ; CHECK: movt r0, #42405 @ encoding: [0xa5,0x05,0x4a,0xe3]
78 %and = and i32 %a, 65535
79 %or = or i32 %and, -1515913216
85 ; CHECK: movw r0, #42405 @ encoding: [0xa5,0x05,0x0a,0xe3]
89 define i64 @f10(i64 %a) {
91 ; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1]
92 ; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1]
97 define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) {
99 ; CHECK: ubfx r1, r1, #8, #5 @ encoding: [0x51,0x14,0xe4,0xe7]
100 ; CHECK: sbfx r0, r0, #13, #7 @ encoding: [0xd0,0x06,0xa6,0xe7]
101 %tmp1 = extractvalue [1 x i32] %A.coerce0, 0
102 %tmp2 = extractvalue [1 x i32] %B.coerce0, 0
103 %tmp3 = shl i32 %tmp1, 12
104 %bf.val.sext = ashr i32 %tmp3, 25
105 %tmp4 = lshr i32 %tmp2, 8
106 %bf.clear2 = and i32 %tmp4, 31
107 %mul = mul nsw i32 %bf.val.sext, %bf.clear2
111 define i32 @f12(i32 %a) {
113 ; CHECK: bfc r0, #4, #20 @ encoding: [0x1f,0x02,0xd7,0xe7]
114 %tmp = and i32 %a, 4278190095
120 ; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3]
121 ; CHECK: mvn r1, #2, 2 @ encoding: [0x02,0x11,0xe0,0xe3]
122 ret i64 9223372036854775807
125 define i32 @f14(i32 %x, i32 %y) {
127 ; CHECK: smmul r0, r1, r0 @ encoding: [0x11,0xf0,0x50,0xe7]
128 %tmp = sext i32 %x to i64
129 %tmp1 = sext i32 %y to i64
130 %tmp2 = mul i64 %tmp1, %tmp
131 %tmp3 = lshr i64 %tmp2, 32
132 %tmp3.upgrd.1 = trunc i64 %tmp3 to i32
133 ret i32 %tmp3.upgrd.1
136 define i32 @f15(i32 %x, i32 %y) {
138 ; CHECK: umull r1, r0, r1, r0 @ encoding: [0x91,0x10,0x80,0xe0]
139 %tmp = zext i32 %x to i64
140 %tmp1 = zext i32 %y to i64
141 %tmp2 = mul i64 %tmp1, %tmp
142 %tmp3 = lshr i64 %tmp2, 32
143 %tmp3.upgrd.2 = trunc i64 %tmp3 to i32
144 ret i32 %tmp3.upgrd.2
147 define i32 @f16(i16 %x, i32 %y) {
149 ; CHECK: smulbt r0, r0, r1 @ encoding: [0xc0,0x01,0x60,0xe1]
150 %tmp1 = add i16 %x, 2
151 %tmp2 = sext i16 %tmp1 to i32
152 %tmp3 = ashr i32 %y, 16
153 %tmp4 = mul i32 %tmp2, %tmp3
157 define i32 @f17(i32 %x, i32 %y) {
159 ; CHECK: smultt r0, r1, r0 @ encoding: [0xe1,0x00,0x60,0xe1]
160 %tmp1 = ashr i32 %x, 16
161 %tmp3 = ashr i32 %y, 16
162 %tmp4 = mul i32 %tmp3, %tmp1
166 define i32 @f18(i32 %a, i16 %x, i32 %y) {
168 ; CHECK: smlabt r0, r1, r2, r0 @ encoding: [0xc1,0x02,0x00,0xe1]
169 %tmp = sext i16 %x to i32
170 %tmp2 = ashr i32 %y, 16
171 %tmp3 = mul i32 %tmp2, %tmp
172 %tmp5 = add i32 %tmp3, %a
176 define i32 @f19(i32 %x) {
178 ; CHECK: clz r0, r0 @ encoding: [0x10,0x0f,0x6f,0xe1]
179 %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x )
183 define i32 @f20(i32 %X) {
185 ; CHECK: rev16 r0, r0 @ encoding: [0xb0,0x0f,0xbf,0xe6]
186 %tmp1 = lshr i32 %X, 8
187 %X15 = bitcast i32 %X to i32
188 %tmp4 = shl i32 %X15, 8
189 %tmp2 = and i32 %tmp1, 16711680
190 %tmp5 = and i32 %tmp4, -16777216
191 %tmp9 = and i32 %tmp1, 255
192 %tmp13 = and i32 %tmp4, 65280
193 %tmp6 = or i32 %tmp5, %tmp2
194 %tmp10 = or i32 %tmp6, %tmp13
195 %tmp14 = or i32 %tmp10, %tmp9
199 define i32 @f21(i32 %X) {
201 ; CHECK: revsh r0, r0 @ encoding: [0xb0,0x0f,0xff,0xe6]
202 %tmp1 = lshr i32 %X, 8
203 %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
204 %tmp3 = trunc i32 %X to i16
205 %tmp2 = and i16 %tmp1.upgrd.1, 255
206 %tmp4 = shl i16 %tmp3, 8
207 %tmp5 = or i16 %tmp2, %tmp4
208 %tmp5.upgrd.2 = sext i16 %tmp5 to i32
209 ret i32 %tmp5.upgrd.2
212 define i32 @f22(i32 %X, i32 %Y) {
214 ; CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0x51,0x0b,0x80,0xe6]
215 %tmp1 = and i32 %X, -65536
216 %tmp2 = lshr i32 %Y, 22
217 %tmp3 = or i32 %tmp2, %tmp1
221 define i32 @f23(i32 %X, i32 %Y) {
223 ; CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x11,0x09,0x80,0xe6]
224 %tmp1 = and i32 %X, 65535
225 %tmp2 = shl i32 %Y, 18
226 %tmp3 = or i32 %tmp1, %tmp2
230 define void @f24(i32 %a) {
232 ; CHECK: cmp r0, #1, 16 @ encoding: [0x01,0x08,0x50,0xe3]
233 %b = icmp ugt i32 %a, 65536
234 br i1 %b, label %r, label %r