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Fixed some bugs.
[llvm/zpu.git]
/
test
/
TableGen
/
eqbit.td
blob
3953252c4179412e24391e1abc53a886a67c07bf
1
// RUN: tblgen %s | FileCheck %s
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// XFAIL: vg_leak
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// CHECK: a = 6
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// CHECK: a = 5
5
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class A<bit b = 1> {
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int a = !if(!eq(b, 1), 5, 6);
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}
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def X : A<0>;
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def Y : A;