Fixed some bugs.

[llvm/zpu.git] / test / TableGen / ifbit.td

// RUN: tblgen %s | FileCheck %s
// XFAIL: vg_leak
// CHECK: a = 6
// CHECK: a = 5

class A<bit b = 1> {
  int a = !if(b, 5, 6);
}

def X : A<0>;
def Y : A;