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Fixed some bugs.
[llvm/zpu.git] / utils / TableGen / CodeGenTarget.cpp
blobf8ba6748a1cbbc5a6184bc68986247bb37316bbc
1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class wraps target description classes used by the various code
11 // generation TableGen backends. This makes it easier to access the data and
12 // provides a single place that needs to check it for validity. All of these
13 // classes throw exceptions on error conditions.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #include "CodeGenTarget.h"
18 #include "CodeGenIntrinsics.h"
19 #include "Record.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/CommandLine.h"
23 #include <algorithm>
24 using namespace llvm;
25
26 static cl::opt<unsigned>
27 AsmParserNum("asmparsernum", cl::init(0),
28 cl::desc("Make -gen-asm-parser emit assembly parser #N"));
29
30 static cl::opt<unsigned>
31 AsmWriterNum("asmwriternum", cl::init(0),
32 cl::desc("Make -gen-asm-writer emit assembly writer #N"));
33
34 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
35 /// record corresponds to.
36 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
37 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
38 }
39
40 std::string llvm::getName(MVT::SimpleValueType T) {
41 switch (T) {
42 case MVT::Other: return "UNKNOWN";
43 case MVT::iPTR: return "TLI.getPointerTy()";
44 case MVT::iPTRAny: return "TLI.getPointerTy()";
45 default: return getEnumName(T);
46 }
47 }
48
49 std::string llvm::getEnumName(MVT::SimpleValueType T) {
50 switch (T) {
51 case MVT::Other: return "MVT::Other";
52 case MVT::i1: return "MVT::i1";
53 case MVT::i8: return "MVT::i8";
54 case MVT::i16: return "MVT::i16";
55 case MVT::i32: return "MVT::i32";
56 case MVT::i64: return "MVT::i64";
57 case MVT::i128: return "MVT::i128";
58 case MVT::iAny: return "MVT::iAny";
59 case MVT::fAny: return "MVT::fAny";
60 case MVT::vAny: return "MVT::vAny";
61 case MVT::f32: return "MVT::f32";
62 case MVT::f64: return "MVT::f64";
63 case MVT::f80: return "MVT::f80";
64 case MVT::f128: return "MVT::f128";
65 case MVT::ppcf128: return "MVT::ppcf128";
66 case MVT::x86mmx: return "MVT::x86mmx";
67 case MVT::Flag: return "MVT::Flag";
68 case MVT::isVoid: return "MVT::isVoid";
69 case MVT::v2i8: return "MVT::v2i8";
70 case MVT::v4i8: return "MVT::v4i8";
71 case MVT::v8i8: return "MVT::v8i8";
72 case MVT::v16i8: return "MVT::v16i8";
73 case MVT::v32i8: return "MVT::v32i8";
74 case MVT::v2i16: return "MVT::v2i16";
75 case MVT::v4i16: return "MVT::v4i16";
76 case MVT::v8i16: return "MVT::v8i16";
77 case MVT::v16i16: return "MVT::v16i16";
78 case MVT::v2i32: return "MVT::v2i32";
79 case MVT::v4i32: return "MVT::v4i32";
80 case MVT::v8i32: return "MVT::v8i32";
81 case MVT::v1i64: return "MVT::v1i64";
82 case MVT::v2i64: return "MVT::v2i64";
83 case MVT::v4i64: return "MVT::v4i64";
84 case MVT::v8i64: return "MVT::v8i64";
85 case MVT::v2f32: return "MVT::v2f32";
86 case MVT::v4f32: return "MVT::v4f32";
87 case MVT::v8f32: return "MVT::v8f32";
88 case MVT::v2f64: return "MVT::v2f64";
89 case MVT::v4f64: return "MVT::v4f64";
90 case MVT::Metadata: return "MVT::Metadata";
91 case MVT::iPTR: return "MVT::iPTR";
92 case MVT::iPTRAny: return "MVT::iPTRAny";
93 default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
94 }
95 }
96
97 /// getQualifiedName - Return the name of the specified record, with a
98 /// namespace qualifier if the record contains one.
99 ///
100 std::string llvm::getQualifiedName(const Record *R) {
101 std::string Namespace = R->getValueAsString("Namespace");
102 if (Namespace.empty()) return R->getName();
103 return Namespace + "::" + R->getName();
104 }
105
106
107
108
109 /// getTarget - Return the current instance of the Target class.
110 ///
111 CodeGenTarget::CodeGenTarget() {
112 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
113 if (Targets.size() == 0)
114 throw std::string("ERROR: No 'Target' subclasses defined!");
115 if (Targets.size() != 1)
116 throw std::string("ERROR: Multiple subclasses of Target defined!");
117 TargetRec = Targets[0];
118 }
119
120
121 const std::string &CodeGenTarget::getName() const {
122 return TargetRec->getName();
123 }
124
125 std::string CodeGenTarget::getInstNamespace() const {
126 for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) {
127 // Make sure not to pick up "TargetOpcode" by accidentally getting
128 // the namespace off the PHI instruction or something.
129 if ((*i)->Namespace != "TargetOpcode")
130 return (*i)->Namespace;
131 }
132
133 return "";
134 }
135
136 Record *CodeGenTarget::getInstructionSet() const {
137 return TargetRec->getValueAsDef("InstructionSet");
138 }
139
140
141 /// getAsmParser - Return the AssemblyParser definition for this target.
142 ///
143 Record *CodeGenTarget::getAsmParser() const {
144 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
145 if (AsmParserNum >= LI.size())
146 throw "Target does not have an AsmParser #" + utostr(AsmParserNum) + "!";
147 return LI[AsmParserNum];
148 }
149
150 /// getAsmWriter - Return the AssemblyWriter definition for this target.
151 ///
152 Record *CodeGenTarget::getAsmWriter() const {
153 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
154 if (AsmWriterNum >= LI.size())
155 throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
156 return LI[AsmWriterNum];
157 }
158
159 void CodeGenTarget::ReadRegisters() const {
160 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
161 if (Regs.empty())
162 throw std::string("No 'Register' subclasses defined!");
163 std::sort(Regs.begin(), Regs.end(), LessRecord());
164
165 Registers.reserve(Regs.size());
166 Registers.assign(Regs.begin(), Regs.end());
167 }
168
169 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
170 DeclaredSpillSize = R->getValueAsInt("SpillSize");
171 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
172 }
173
174 const std::string &CodeGenRegister::getName() const {
175 return TheDef->getName();
176 }
177
178 void CodeGenTarget::ReadSubRegIndices() const {
179 SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
180 std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
181 }
182
183 void CodeGenTarget::ReadRegisterClasses() const {
184 std::vector<Record*> RegClasses =
185 Records.getAllDerivedDefinitions("RegisterClass");
186 if (RegClasses.empty())
187 throw std::string("No 'RegisterClass' subclasses defined!");
188
189 RegisterClasses.reserve(RegClasses.size());
190 RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
191 }
192
193 /// getRegisterByName - If there is a register with the specific AsmName,
194 /// return it.
195 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
196 const std::vector<CodeGenRegister> &Regs = getRegisters();
197 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
198 const CodeGenRegister &Reg = Regs[i];
199 if (Reg.TheDef->getValueAsString("AsmName") == Name)
200 return &Reg;
201 }
202
203 return 0;
204 }
205
206 std::vector<MVT::SimpleValueType> CodeGenTarget::
207 getRegisterVTs(Record *R) const {
208 std::vector<MVT::SimpleValueType> Result;
209 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
210 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
211 const CodeGenRegisterClass &RC = RegisterClasses[i];
212 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
213 if (R == RC.Elements[ei]) {
214 const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
215 Result.insert(Result.end(), InVTs.begin(), InVTs.end());
216 }
217 }
218 }
219
220 // Remove duplicates.
221 array_pod_sort(Result.begin(), Result.end());
222 Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
223 return Result;
224 }
225
226
227 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
228 // Rename anonymous register classes.
229 if (R->getName().size() > 9 && R->getName()[9] == '.') {
230 static unsigned AnonCounter = 0;
231 R->setName("AnonRegClass_"+utostr(AnonCounter++));
232 }
233
234 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
235 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
236 Record *Type = TypeList[i];
237 if (!Type->isSubClassOf("ValueType"))
238 throw "RegTypes list member '" + Type->getName() +
239 "' does not derive from the ValueType class!";
240 VTs.push_back(getValueType(Type));
241 }
242 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
243
244 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
245 for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
246 Record *Reg = RegList[i];
247 if (!Reg->isSubClassOf("Register"))
248 throw "Register Class member '" + Reg->getName() +
249 "' does not derive from the Register class!";
250 Elements.push_back(Reg);
251 }
252
253 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
254 ListInit *SRC = R->getValueAsListInit("SubRegClasses");
255 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
256 DagInit *DAG = dynamic_cast<DagInit*>(*i);
257 if (!DAG) throw "SubRegClasses must contain DAGs";
258 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
259 Record *RCRec;
260 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
261 throw "Operator '" + DAG->getOperator()->getAsString() +
262 "' in SubRegClasses is not a RegisterClass";
263 // Iterate over args, all SubRegIndex instances.
264 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
265 ai != ae; ++ai) {
266 DefInit *Idx = dynamic_cast<DefInit*>(*ai);
267 Record *IdxRec;
268 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
269 throw "Argument '" + (*ai)->getAsString() +
270 "' in SubRegClasses is not a SubRegIndex";
271 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
272 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
273 }
274 }
275
276 // Allow targets to override the size in bits of the RegisterClass.
277 unsigned Size = R->getValueAsInt("Size");
278
279 Namespace = R->getValueAsString("Namespace");
280 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
281 SpillAlignment = R->getValueAsInt("Alignment");
282 CopyCost = R->getValueAsInt("CopyCost");
283 MethodBodies = R->getValueAsCode("MethodBodies");
284 MethodProtos = R->getValueAsCode("MethodProtos");
285 }
286
287 const std::string &CodeGenRegisterClass::getName() const {
288 return TheDef->getName();
289 }
290
291 void CodeGenTarget::ReadLegalValueTypes() const {
292 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
293 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
294 for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
295 LegalValueTypes.push_back(RCs[i].VTs[ri]);
296
297 // Remove duplicates.
298 std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
299 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
300 LegalValueTypes.end()),
301 LegalValueTypes.end());
302 }
303
304
305 void CodeGenTarget::ReadInstructions() const {
306 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
307 if (Insts.size() <= 2)
308 throw std::string("No 'Instruction' subclasses defined!");
309
310 // Parse the instructions defined in the .td file.
311 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
312 Instructions[Insts[i]] = new CodeGenInstruction(Insts[i]);
313 }
314
315 static const CodeGenInstruction *
316 GetInstByName(const char *Name,
317 const DenseMap<const Record*, CodeGenInstruction*> &Insts) {
318 const Record *Rec = Records.getDef(Name);
319
320 DenseMap<const Record*, CodeGenInstruction*>::const_iterator
321 I = Insts.find(Rec);
322 if (Rec == 0 || I == Insts.end())
323 throw std::string("Could not find '") + Name + "' instruction!";
324 return I->second;
325 }
326
327 namespace {
328 /// SortInstByName - Sorting predicate to sort instructions by name.
329 ///
330 struct SortInstByName {
331 bool operator()(const CodeGenInstruction *Rec1,
332 const CodeGenInstruction *Rec2) const {
333 return Rec1->TheDef->getName() < Rec2->TheDef->getName();
334 }
335 };
336 }
337
338 /// getInstructionsByEnumValue - Return all of the instructions defined by the
339 /// target, ordered by their enum value.
340 void CodeGenTarget::ComputeInstrsByEnum() const {
341 // The ordering here must match the ordering in TargetOpcodes.h.
342 const char *const FixedInstrs[] = {
343 "PHI",
344 "INLINEASM",
345 "PROLOG_LABEL",
346 "EH_LABEL",
347 "GC_LABEL",
348 "KILL",
349 "EXTRACT_SUBREG",
350 "INSERT_SUBREG",
351 "IMPLICIT_DEF",
352 "SUBREG_TO_REG",
353 "COPY_TO_REGCLASS",
354 "DBG_VALUE",
355 "REG_SEQUENCE",
356 "COPY",
357 0
358 };
359 const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
360 for (const char *const *p = FixedInstrs; *p; ++p) {
361 const CodeGenInstruction *Instr = GetInstByName(*p, Insts);
362 assert(Instr && "Missing target independent instruction");
363 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
364 InstrsByEnum.push_back(Instr);
365 }
366 unsigned EndOfPredefines = InstrsByEnum.size();
367
368 for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator
369 I = Insts.begin(), E = Insts.end(); I != E; ++I) {
370 const CodeGenInstruction *CGI = I->second;
371 if (CGI->Namespace != "TargetOpcode")
372 InstrsByEnum.push_back(CGI);
373 }
374
375 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
376
377 // All of the instructions are now in random order based on the map iteration.
378 // Sort them by name.
379 std::sort(InstrsByEnum.begin()+EndOfPredefines, InstrsByEnum.end(),
380 SortInstByName());
381 }
382
383
384 /// isLittleEndianEncoding - Return whether this target encodes its instruction
385 /// in little-endian format, i.e. bits laid out in the order [0..n]
386 ///
387 bool CodeGenTarget::isLittleEndianEncoding() const {
388 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
389 }
390
391 //===----------------------------------------------------------------------===//
392 // ComplexPattern implementation
393 //
394 ComplexPattern::ComplexPattern(Record *R) {
395 Ty = ::getValueType(R->getValueAsDef("Ty"));
396 NumOperands = R->getValueAsInt("NumOperands");
397 SelectFunc = R->getValueAsString("SelectFunc");
398 RootNodes = R->getValueAsListOfDefs("RootNodes");
399
400 // Parse the properties.
401 Properties = 0;
402 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
403 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
404 if (PropList[i]->getName() == "SDNPHasChain") {
405 Properties |= 1 << SDNPHasChain;
406 } else if (PropList[i]->getName() == "SDNPOptInFlag") {
407 Properties |= 1 << SDNPOptInFlag;
408 } else if (PropList[i]->getName() == "SDNPMayStore") {
409 Properties |= 1 << SDNPMayStore;
410 } else if (PropList[i]->getName() == "SDNPMayLoad") {
411 Properties |= 1 << SDNPMayLoad;
412 } else if (PropList[i]->getName() == "SDNPSideEffect") {
413 Properties |= 1 << SDNPSideEffect;
414 } else if (PropList[i]->getName() == "SDNPMemOperand") {
415 Properties |= 1 << SDNPMemOperand;
416 } else if (PropList[i]->getName() == "SDNPVariadic") {
417 Properties |= 1 << SDNPVariadic;
418 } else if (PropList[i]->getName() == "SDNPWantRoot") {
419 Properties |= 1 << SDNPWantRoot;
420 } else if (PropList[i]->getName() == "SDNPWantParent") {
421 Properties |= 1 << SDNPWantParent;
422 } else {
423 errs() << "Unsupported SD Node property '" << PropList[i]->getName()
424 << "' on ComplexPattern '" << R->getName() << "'!\n";
425 exit(1);
426 }
427 }
428
429 //===----------------------------------------------------------------------===//
430 // CodeGenIntrinsic Implementation
431 //===----------------------------------------------------------------------===//
432
433 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC,
434 bool TargetOnly) {
435 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
436
437 std::vector<CodeGenIntrinsic> Result;
438
439 for (unsigned i = 0, e = I.size(); i != e; ++i) {
440 bool isTarget = I[i]->getValueAsBit("isTarget");
441 if (isTarget == TargetOnly)
442 Result.push_back(CodeGenIntrinsic(I[i]));
443 }
444 return Result;
445 }
446
447 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
448 TheDef = R;
449 std::string DefName = R->getName();
450 ModRef = ReadWriteMem;
451 isOverloaded = false;
452 isCommutative = false;
453
454 if (DefName.size() <= 4 ||
455 std::string(DefName.begin(), DefName.begin() + 4) != "int_")
456 throw "Intrinsic '" + DefName + "' does not start with 'int_'!";
457
458 EnumName = std::string(DefName.begin()+4, DefName.end());
459
460 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
461 GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
462
463 TargetPrefix = R->getValueAsString("TargetPrefix");
464 Name = R->getValueAsString("LLVMName");
465
466 if (Name == "") {
467 // If an explicit name isn't specified, derive one from the DefName.
468 Name = "llvm.";
469
470 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
471 Name += (EnumName[i] == '_') ? '.' : EnumName[i];
472 } else {
473 // Verify it starts with "llvm.".
474 if (Name.size() <= 5 ||
475 std::string(Name.begin(), Name.begin() + 5) != "llvm.")
476 throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!";
477 }
478
479 // If TargetPrefix is specified, make sure that Name starts with
480 // "llvm.<targetprefix>.".
481 if (!TargetPrefix.empty()) {
482 if (Name.size() < 6+TargetPrefix.size() ||
483 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
484 != (TargetPrefix + "."))
485 throw "Intrinsic '" + DefName + "' does not start with 'llvm." +
486 TargetPrefix + ".'!";
487 }
488
489 // Parse the list of return types.
490 std::vector<MVT::SimpleValueType> OverloadedVTs;
491 ListInit *TypeList = R->getValueAsListInit("RetTypes");
492 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
493 Record *TyEl = TypeList->getElementAsRecord(i);
494 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
495 MVT::SimpleValueType VT;
496 if (TyEl->isSubClassOf("LLVMMatchType")) {
497 unsigned MatchTy = TyEl->getValueAsInt("Number");
498 assert(MatchTy < OverloadedVTs.size() &&
499 "Invalid matching number!");
500 VT = OverloadedVTs[MatchTy];
501 // It only makes sense to use the extended and truncated vector element
502 // variants with iAny types; otherwise, if the intrinsic is not
503 // overloaded, all the types can be specified directly.
504 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
505 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
506 VT == MVT::iAny || VT == MVT::vAny) &&
507 "Expected iAny or vAny type");
508 } else {
509 VT = getValueType(TyEl->getValueAsDef("VT"));
510 }
511 if (EVT(VT).isOverloaded()) {
512 OverloadedVTs.push_back(VT);
513 isOverloaded = true;
514 }
515
516 // Reject invalid types.
517 if (VT == MVT::isVoid)
518 throw "Intrinsic '" + DefName + " has void in result type list!";
519
520 IS.RetVTs.push_back(VT);
521 IS.RetTypeDefs.push_back(TyEl);
522 }
523
524 // Parse the list of parameter types.
525 TypeList = R->getValueAsListInit("ParamTypes");
526 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
527 Record *TyEl = TypeList->getElementAsRecord(i);
528 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
529 MVT::SimpleValueType VT;
530 if (TyEl->isSubClassOf("LLVMMatchType")) {
531 unsigned MatchTy = TyEl->getValueAsInt("Number");
532 assert(MatchTy < OverloadedVTs.size() &&
533 "Invalid matching number!");
534 VT = OverloadedVTs[MatchTy];
535 // It only makes sense to use the extended and truncated vector element
536 // variants with iAny types; otherwise, if the intrinsic is not
537 // overloaded, all the types can be specified directly.
538 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
539 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
540 VT == MVT::iAny || VT == MVT::vAny) &&
541 "Expected iAny or vAny type");
542 } else
543 VT = getValueType(TyEl->getValueAsDef("VT"));
544
545 if (EVT(VT).isOverloaded()) {
546 OverloadedVTs.push_back(VT);
547 isOverloaded = true;
548 }
549
550 // Reject invalid types.
551 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
552 throw "Intrinsic '" + DefName + " has void in result type list!";
553
554 IS.ParamVTs.push_back(VT);
555 IS.ParamTypeDefs.push_back(TyEl);
556 }
557
558 // Parse the intrinsic properties.
559 ListInit *PropList = R->getValueAsListInit("Properties");
560 for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
561 Record *Property = PropList->getElementAsRecord(i);
562 assert(Property->isSubClassOf("IntrinsicProperty") &&
563 "Expected a property!");
564
565 if (Property->getName() == "IntrNoMem")
566 ModRef = NoMem;
567 else if (Property->getName() == "IntrReadArgMem")
568 ModRef = ReadArgMem;
569 else if (Property->getName() == "IntrReadMem")
570 ModRef = ReadMem;
571 else if (Property->getName() == "IntrReadWriteArgMem")
572 ModRef = ReadWriteArgMem;
573 else if (Property->getName() == "Commutative")
574 isCommutative = true;
575 else if (Property->isSubClassOf("NoCapture")) {
576 unsigned ArgNo = Property->getValueAsInt("ArgNo");
577 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
578 } else
579 assert(0 && "Unknown property!");
580 }
581 }
ZPU llvm backend wip