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init from v2.6.32.60
[mach-moxart.git] / arch / mips / include / asm / mipsregs.h
blob608dc976455b19ab76c10bc393873eea56c2fb8d
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <asm/hazards.h>
18 #include <asm/war.h>
19
20 /*
21 * The following macros are especially useful for __asm__
22 * inline assembler.
23 */
24 #ifndef __STR
25 #define __STR(x) #x
26 #endif
27 #ifndef STR
28 #define STR(x) __STR(x)
29 #endif
30
31 /*
32 * Configure language
33 */
34 #ifdef __ASSEMBLY__
35 #define _ULCAST_
36 #else
37 #define _ULCAST_ (unsigned long)
38 #endif
39
40 /*
41 * Coprocessor 0 register names
42 */
43 #define CP0_INDEX $0
44 #define CP0_RANDOM $1
45 #define CP0_ENTRYLO0 $2
46 #define CP0_ENTRYLO1 $3
47 #define CP0_CONF $3
48 #define CP0_CONTEXT $4
49 #define CP0_PAGEMASK $5
50 #define CP0_WIRED $6
51 #define CP0_INFO $7
52 #define CP0_BADVADDR $8
53 #define CP0_COUNT $9
54 #define CP0_ENTRYHI $10
55 #define CP0_COMPARE $11
56 #define CP0_STATUS $12
57 #define CP0_CAUSE $13
58 #define CP0_EPC $14
59 #define CP0_PRID $15
60 #define CP0_CONFIG $16
61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22
67 #define CP0_DEBUG $23
68 #define CP0_DEPC $24
69 #define CP0_PERFORMANCE $25
70 #define CP0_ECC $26
71 #define CP0_CACHEERR $27
72 #define CP0_TAGLO $28
73 #define CP0_TAGHI $29
74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31
76
77 /*
78 * R4640/R4650 cp0 register names. These registers are listed
79 * here only for completeness; without MMU these CPUs are not useable
80 * by Linux. A future ELKS port might take make Linux run on them
81 * though ...
82 */
83 #define CP0_IBASE $0
84 #define CP0_IBOUND $1
85 #define CP0_DBASE $2
86 #define CP0_DBOUND $3
87 #define CP0_CALG $17
88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19
90
91 /*
92 * Coprocessor 0 Set 1 register names
93 */
94 #define CP0_S1_DERRADDR0 $26
95 #define CP0_S1_DERRADDR1 $27
96 #define CP0_S1_INTCONTROL $20
97
98 /*
99 * Coprocessor 0 Set 2 register names
100 */
101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
102
103 /*
104 * Coprocessor 0 Set 3 register names
105 */
106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
107
108 /*
109 * TX39 Series
110 */
111 #define CP0_TX39_CACHE $7
112
113 /*
114 * Coprocessor 1 (FPU) register names
115 */
116 #define CP1_REVISION $0
117 #define CP1_STATUS $31
118
119 /*
120 * FPU Status Register Values
121 */
122 /*
123 * Status Register Values
124 */
125
126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
136
137 /*
138 * Bits 18 - 20 of the FPU Status Register will be read as 0,
139 * and should be written as zero.
140 */
141 #define FPU_CSR_RSVD 0x001c0000
142
143 /*
144 * X the exception cause indicator
145 * E the exception enable
146 * S the sticky/flag bit
147 */
148 #define FPU_CSR_ALL_X 0x0003f000
149 #define FPU_CSR_UNI_X 0x00020000
150 #define FPU_CSR_INV_X 0x00010000
151 #define FPU_CSR_DIV_X 0x00008000
152 #define FPU_CSR_OVF_X 0x00004000
153 #define FPU_CSR_UDF_X 0x00002000
154 #define FPU_CSR_INE_X 0x00001000
155
156 #define FPU_CSR_ALL_E 0x00000f80
157 #define FPU_CSR_INV_E 0x00000800
158 #define FPU_CSR_DIV_E 0x00000400
159 #define FPU_CSR_OVF_E 0x00000200
160 #define FPU_CSR_UDF_E 0x00000100
161 #define FPU_CSR_INE_E 0x00000080
162
163 #define FPU_CSR_ALL_S 0x0000007c
164 #define FPU_CSR_INV_S 0x00000040
165 #define FPU_CSR_DIV_S 0x00000020
166 #define FPU_CSR_OVF_S 0x00000010
167 #define FPU_CSR_UDF_S 0x00000008
168 #define FPU_CSR_INE_S 0x00000004
169
170 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
171 #define FPU_CSR_RM 0x00000003
172 #define FPU_CSR_RN 0x0 /* nearest */
173 #define FPU_CSR_RZ 0x1 /* towards zero */
174 #define FPU_CSR_RU 0x2 /* towards +Infinity */
175 #define FPU_CSR_RD 0x3 /* towards -Infinity */
176
177
178 /*
179 * Values for PageMask register
180 */
181 #ifdef CONFIG_CPU_VR41XX
182
183 /* Why doesn't stupidity hurt ... */
184
185 #define PM_1K 0x00000000
186 #define PM_4K 0x00001800
187 #define PM_16K 0x00007800
188 #define PM_64K 0x0001f800
189 #define PM_256K 0x0007f800
190
191 #else
192
193 #define PM_4K 0x00000000
194 #define PM_8K 0x00002000
195 #define PM_16K 0x00006000
196 #define PM_32K 0x0000e000
197 #define PM_64K 0x0001e000
198 #define PM_128K 0x0003e000
199 #define PM_256K 0x0007e000
200 #define PM_512K 0x000fe000
201 #define PM_1M 0x001fe000
202 #define PM_2M 0x003fe000
203 #define PM_4M 0x007fe000
204 #define PM_8M 0x00ffe000
205 #define PM_16M 0x01ffe000
206 #define PM_32M 0x03ffe000
207 #define PM_64M 0x07ffe000
208 #define PM_256M 0x1fffe000
209 #define PM_1G 0x7fffe000
210
211 #endif
212
213 /*
214 * Default page size for a given kernel configuration
215 */
216 #ifdef CONFIG_PAGE_SIZE_4KB
217 #define PM_DEFAULT_MASK PM_4K
218 #elif defined(CONFIG_PAGE_SIZE_8KB)
219 #define PM_DEFAULT_MASK PM_8K
220 #elif defined(CONFIG_PAGE_SIZE_16KB)
221 #define PM_DEFAULT_MASK PM_16K
222 #elif defined(CONFIG_PAGE_SIZE_32KB)
223 #define PM_DEFAULT_MASK PM_32K
224 #elif defined(CONFIG_PAGE_SIZE_64KB)
225 #define PM_DEFAULT_MASK PM_64K
226 #else
227 #error Bad page size configuration!
228 #endif
229
230 /*
231 * Default huge tlb size for a given kernel configuration
232 */
233 #ifdef CONFIG_PAGE_SIZE_4KB
234 #define PM_HUGE_MASK PM_1M
235 #elif defined(CONFIG_PAGE_SIZE_8KB)
236 #define PM_HUGE_MASK PM_4M
237 #elif defined(CONFIG_PAGE_SIZE_16KB)
238 #define PM_HUGE_MASK PM_16M
239 #elif defined(CONFIG_PAGE_SIZE_32KB)
240 #define PM_HUGE_MASK PM_64M
241 #elif defined(CONFIG_PAGE_SIZE_64KB)
242 #define PM_HUGE_MASK PM_256M
243 #elif defined(CONFIG_HUGETLB_PAGE)
244 #error Bad page size configuration for hugetlbfs!
245 #endif
246
247 /*
248 * Values used for computation of new tlb entries
249 */
250 #define PL_4K 12
251 #define PL_16K 14
252 #define PL_64K 16
253 #define PL_256K 18
254 #define PL_1M 20
255 #define PL_4M 22
256 #define PL_16M 24
257 #define PL_64M 26
258 #define PL_256M 28
259
260 /*
261 * R4x00 interrupt enable / cause bits
262 */
263 #define IE_SW0 (_ULCAST_(1) << 8)
264 #define IE_SW1 (_ULCAST_(1) << 9)
265 #define IE_IRQ0 (_ULCAST_(1) << 10)
266 #define IE_IRQ1 (_ULCAST_(1) << 11)
267 #define IE_IRQ2 (_ULCAST_(1) << 12)
268 #define IE_IRQ3 (_ULCAST_(1) << 13)
269 #define IE_IRQ4 (_ULCAST_(1) << 14)
270 #define IE_IRQ5 (_ULCAST_(1) << 15)
271
272 /*
273 * R4x00 interrupt cause bits
274 */
275 #define C_SW0 (_ULCAST_(1) << 8)
276 #define C_SW1 (_ULCAST_(1) << 9)
277 #define C_IRQ0 (_ULCAST_(1) << 10)
278 #define C_IRQ1 (_ULCAST_(1) << 11)
279 #define C_IRQ2 (_ULCAST_(1) << 12)
280 #define C_IRQ3 (_ULCAST_(1) << 13)
281 #define C_IRQ4 (_ULCAST_(1) << 14)
282 #define C_IRQ5 (_ULCAST_(1) << 15)
283
284 /*
285 * Bitfields in the R4xx0 cp0 status register
286 */
287 #define ST0_IE 0x00000001
288 #define ST0_EXL 0x00000002
289 #define ST0_ERL 0x00000004
290 #define ST0_KSU 0x00000018
291 # define KSU_USER 0x00000010
292 # define KSU_SUPERVISOR 0x00000008
293 # define KSU_KERNEL 0x00000000
294 #define ST0_UX 0x00000020
295 #define ST0_SX 0x00000040
296 #define ST0_KX 0x00000080
297 #define ST0_DE 0x00010000
298 #define ST0_CE 0x00020000
299
300 /*
301 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
302 * cacheops in userspace. This bit exists only on RM7000 and RM9000
303 * processors.
304 */
305 #define ST0_CO 0x08000000
306
307 /*
308 * Bitfields in the R[23]000 cp0 status register.
309 */
310 #define ST0_IEC 0x00000001
311 #define ST0_KUC 0x00000002
312 #define ST0_IEP 0x00000004
313 #define ST0_KUP 0x00000008
314 #define ST0_IEO 0x00000010
315 #define ST0_KUO 0x00000020
316 /* bits 6 & 7 are reserved on R[23]000 */
317 #define ST0_ISC 0x00010000
318 #define ST0_SWC 0x00020000
319 #define ST0_CM 0x00080000
320
321 /*
322 * Bits specific to the R4640/R4650
323 */
324 #define ST0_UM (_ULCAST_(1) << 4)
325 #define ST0_IL (_ULCAST_(1) << 23)
326 #define ST0_DL (_ULCAST_(1) << 24)
327
328 /*
329 * Enable the MIPS MDMX and DSP ASEs
330 */
331 #define ST0_MX 0x01000000
332
333 /*
334 * Bitfields in the TX39 family CP0 Configuration Register 3
335 */
336 #define TX39_CONF_ICS_SHIFT 19
337 #define TX39_CONF_ICS_MASK 0x00380000
338 #define TX39_CONF_ICS_1KB 0x00000000
339 #define TX39_CONF_ICS_2KB 0x00080000
340 #define TX39_CONF_ICS_4KB 0x00100000
341 #define TX39_CONF_ICS_8KB 0x00180000
342 #define TX39_CONF_ICS_16KB 0x00200000
343
344 #define TX39_CONF_DCS_SHIFT 16
345 #define TX39_CONF_DCS_MASK 0x00070000
346 #define TX39_CONF_DCS_1KB 0x00000000
347 #define TX39_CONF_DCS_2KB 0x00010000
348 #define TX39_CONF_DCS_4KB 0x00020000
349 #define TX39_CONF_DCS_8KB 0x00030000
350 #define TX39_CONF_DCS_16KB 0x00040000
351
352 #define TX39_CONF_CWFON 0x00004000
353 #define TX39_CONF_WBON 0x00002000
354 #define TX39_CONF_RF_SHIFT 10
355 #define TX39_CONF_RF_MASK 0x00000c00
356 #define TX39_CONF_DOZE 0x00000200
357 #define TX39_CONF_HALT 0x00000100
358 #define TX39_CONF_LOCK 0x00000080
359 #define TX39_CONF_ICE 0x00000020
360 #define TX39_CONF_DCE 0x00000010
361 #define TX39_CONF_IRSIZE_SHIFT 2
362 #define TX39_CONF_IRSIZE_MASK 0x0000000c
363 #define TX39_CONF_DRSIZE_SHIFT 0
364 #define TX39_CONF_DRSIZE_MASK 0x00000003
365
366 /*
367 * Status register bits available in all MIPS CPUs.
368 */
369 #define ST0_IM 0x0000ff00
370 #define STATUSB_IP0 8
371 #define STATUSF_IP0 (_ULCAST_(1) << 8)
372 #define STATUSB_IP1 9
373 #define STATUSF_IP1 (_ULCAST_(1) << 9)
374 #define STATUSB_IP2 10
375 #define STATUSF_IP2 (_ULCAST_(1) << 10)
376 #define STATUSB_IP3 11
377 #define STATUSF_IP3 (_ULCAST_(1) << 11)
378 #define STATUSB_IP4 12
379 #define STATUSF_IP4 (_ULCAST_(1) << 12)
380 #define STATUSB_IP5 13
381 #define STATUSF_IP5 (_ULCAST_(1) << 13)
382 #define STATUSB_IP6 14
383 #define STATUSF_IP6 (_ULCAST_(1) << 14)
384 #define STATUSB_IP7 15
385 #define STATUSF_IP7 (_ULCAST_(1) << 15)
386 #define STATUSB_IP8 0
387 #define STATUSF_IP8 (_ULCAST_(1) << 0)
388 #define STATUSB_IP9 1
389 #define STATUSF_IP9 (_ULCAST_(1) << 1)
390 #define STATUSB_IP10 2
391 #define STATUSF_IP10 (_ULCAST_(1) << 2)
392 #define STATUSB_IP11 3
393 #define STATUSF_IP11 (_ULCAST_(1) << 3)
394 #define STATUSB_IP12 4
395 #define STATUSF_IP12 (_ULCAST_(1) << 4)
396 #define STATUSB_IP13 5
397 #define STATUSF_IP13 (_ULCAST_(1) << 5)
398 #define STATUSB_IP14 6
399 #define STATUSF_IP14 (_ULCAST_(1) << 6)
400 #define STATUSB_IP15 7
401 #define STATUSF_IP15 (_ULCAST_(1) << 7)
402 #define ST0_CH 0x00040000
403 #define ST0_SR 0x00100000
404 #define ST0_TS 0x00200000
405 #define ST0_BEV 0x00400000
406 #define ST0_RE 0x02000000
407 #define ST0_FR 0x04000000
408 #define ST0_CU 0xf0000000
409 #define ST0_CU0 0x10000000
410 #define ST0_CU1 0x20000000
411 #define ST0_CU2 0x40000000
412 #define ST0_CU3 0x80000000
413 #define ST0_XX 0x80000000 /* MIPS IV naming */
414
415 /*
416 * Bitfields and bit numbers in the coprocessor 0 cause register.
417 *
418 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
419 */
420 #define CAUSEB_EXCCODE 2
421 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
422 #define CAUSEB_IP 8
423 #define CAUSEF_IP (_ULCAST_(255) << 8)
424 #define CAUSEB_IP0 8
425 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
426 #define CAUSEB_IP1 9
427 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
428 #define CAUSEB_IP2 10
429 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
430 #define CAUSEB_IP3 11
431 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
432 #define CAUSEB_IP4 12
433 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
434 #define CAUSEB_IP5 13
435 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
436 #define CAUSEB_IP6 14
437 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
438 #define CAUSEB_IP7 15
439 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
440 #define CAUSEB_IV 23
441 #define CAUSEF_IV (_ULCAST_(1) << 23)
442 #define CAUSEB_CE 28
443 #define CAUSEF_CE (_ULCAST_(3) << 28)
444 #define CAUSEB_BD 31
445 #define CAUSEF_BD (_ULCAST_(1) << 31)
446
447 /*
448 * Bits in the coprocessor 0 config register.
449 */
450 /* Generic bits. */
451 #define CONF_CM_CACHABLE_NO_WA 0
452 #define CONF_CM_CACHABLE_WA 1
453 #define CONF_CM_UNCACHED 2
454 #define CONF_CM_CACHABLE_NONCOHERENT 3
455 #define CONF_CM_CACHABLE_CE 4
456 #define CONF_CM_CACHABLE_COW 5
457 #define CONF_CM_CACHABLE_CUW 6
458 #define CONF_CM_CACHABLE_ACCELERATED 7
459 #define CONF_CM_CMASK 7
460 #define CONF_BE (_ULCAST_(1) << 15)
461
462 /* Bits common to various processors. */
463 #define CONF_CU (_ULCAST_(1) << 3)
464 #define CONF_DB (_ULCAST_(1) << 4)
465 #define CONF_IB (_ULCAST_(1) << 5)
466 #define CONF_DC (_ULCAST_(7) << 6)
467 #define CONF_IC (_ULCAST_(7) << 9)
468 #define CONF_EB (_ULCAST_(1) << 13)
469 #define CONF_EM (_ULCAST_(1) << 14)
470 #define CONF_SM (_ULCAST_(1) << 16)
471 #define CONF_SC (_ULCAST_(1) << 17)
472 #define CONF_EW (_ULCAST_(3) << 18)
473 #define CONF_EP (_ULCAST_(15)<< 24)
474 #define CONF_EC (_ULCAST_(7) << 28)
475 #define CONF_CM (_ULCAST_(1) << 31)
476
477 /* Bits specific to the R4xx0. */
478 #define R4K_CONF_SW (_ULCAST_(1) << 20)
479 #define R4K_CONF_SS (_ULCAST_(1) << 21)
480 #define R4K_CONF_SB (_ULCAST_(3) << 22)
481
482 /* Bits specific to the R5000. */
483 #define R5K_CONF_SE (_ULCAST_(1) << 12)
484 #define R5K_CONF_SS (_ULCAST_(3) << 20)
485
486 /* Bits specific to the RM7000. */
487 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
488 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
489 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
490 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
491 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
492 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
493
494 /* Bits specific to the R10000. */
495 #define R10K_CONF_DN (_ULCAST_(3) << 3)
496 #define R10K_CONF_CT (_ULCAST_(1) << 5)
497 #define R10K_CONF_PE (_ULCAST_(1) << 6)
498 #define R10K_CONF_PM (_ULCAST_(3) << 7)
499 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
500 #define R10K_CONF_SB (_ULCAST_(1) << 13)
501 #define R10K_CONF_SK (_ULCAST_(1) << 14)
502 #define R10K_CONF_SS (_ULCAST_(7) << 16)
503 #define R10K_CONF_SC (_ULCAST_(7) << 19)
504 #define R10K_CONF_DC (_ULCAST_(7) << 26)
505 #define R10K_CONF_IC (_ULCAST_(7) << 29)
506
507 /* Bits specific to the VR41xx. */
508 #define VR41_CONF_CS (_ULCAST_(1) << 12)
509 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
510 #define VR41_CONF_BP (_ULCAST_(1) << 16)
511 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
512 #define VR41_CONF_AD (_ULCAST_(1) << 23)
513
514 /* Bits specific to the R30xx. */
515 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
516 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
517 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
518 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
519 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
520 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
521 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
522 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
523 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
524
525 /* Bits specific to the TX49. */
526 #define TX49_CONF_DC (_ULCAST_(1) << 16)
527 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
528 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
529 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
530
531 /* Bits specific to the MIPS32/64 PRA. */
532 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
533 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
534 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
535 #define MIPS_CONF_M (_ULCAST_(1) << 31)
536
537 /*
538 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
539 */
540 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
541 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
542 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
543 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
544 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
545 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
546 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
547 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
548 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
549 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
550 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
551 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
552 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
553 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
554
555 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
556 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
557 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
558 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
559 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
560 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
561 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
562 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
563
564 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
565 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
566 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
567 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
568 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
569 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
570 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
571 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
572 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
573
574 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
575
576 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
577
578
579 /*
580 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
581 */
582 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
583 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
584 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
585 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
586 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
587 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
588 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
589
590 #ifndef __ASSEMBLY__
591
592 /*
593 * Functions to access the R10000 performance counters. These are basically
594 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
595 * performance counter number encoded into bits 1 ... 5 of the instruction.
596 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
597 * disassembler these will look like an access to sel 0 or 1.
598 */
599 #define read_r10k_perf_cntr(counter) \
600 ({ \
601 unsigned int __res; \
602 __asm__ __volatile__( \
603 "mfpc\t%0, %1" \
604 : "=r" (__res) \
605 : "i" (counter)); \
606 \
607 __res; \
608 })
609
610 #define write_r10k_perf_cntr(counter,val) \
611 do { \
612 __asm__ __volatile__( \
613 "mtpc\t%0, %1" \
614 : \
615 : "r" (val), "i" (counter)); \
616 } while (0)
617
618 #define read_r10k_perf_event(counter) \
619 ({ \
620 unsigned int __res; \
621 __asm__ __volatile__( \
622 "mfps\t%0, %1" \
623 : "=r" (__res) \
624 : "i" (counter)); \
625 \
626 __res; \
627 })
628
629 #define write_r10k_perf_cntl(counter,val) \
630 do { \
631 __asm__ __volatile__( \
632 "mtps\t%0, %1" \
633 : \
634 : "r" (val), "i" (counter)); \
635 } while (0)
636
637
638 /*
639 * Macros to access the system control coprocessor
640 */
641
642 #define __read_32bit_c0_register(source, sel) \
643 ({ int __res; \
644 if (sel == 0) \
645 __asm__ __volatile__( \
646 "mfc0\t%0, " #source "\n\t" \
647 : "=r" (__res)); \
648 else \
649 __asm__ __volatile__( \
650 ".set\tmips32\n\t" \
651 "mfc0\t%0, " #source ", " #sel "\n\t" \
652 ".set\tmips0\n\t" \
653 : "=r" (__res)); \
654 __res; \
655 })
656
657 #define __read_64bit_c0_register(source, sel) \
658 ({ unsigned long long __res; \
659 if (sizeof(unsigned long) == 4) \
660 __res = __read_64bit_c0_split(source, sel); \
661 else if (sel == 0) \
662 __asm__ __volatile__( \
663 ".set\tmips3\n\t" \
664 "dmfc0\t%0, " #source "\n\t" \
665 ".set\tmips0" \
666 : "=r" (__res)); \
667 else \
668 __asm__ __volatile__( \
669 ".set\tmips64\n\t" \
670 "dmfc0\t%0, " #source ", " #sel "\n\t" \
671 ".set\tmips0" \
672 : "=r" (__res)); \
673 __res; \
674 })
675
676 #define __write_32bit_c0_register(register, sel, value) \
677 do { \
678 if (sel == 0) \
679 __asm__ __volatile__( \
680 "mtc0\t%z0, " #register "\n\t" \
681 : : "Jr" ((unsigned int)(value))); \
682 else \
683 __asm__ __volatile__( \
684 ".set\tmips32\n\t" \
685 "mtc0\t%z0, " #register ", " #sel "\n\t" \
686 ".set\tmips0" \
687 : : "Jr" ((unsigned int)(value))); \
688 } while (0)
689
690 #define __write_64bit_c0_register(register, sel, value) \
691 do { \
692 if (sizeof(unsigned long) == 4) \
693 __write_64bit_c0_split(register, sel, value); \
694 else if (sel == 0) \
695 __asm__ __volatile__( \
696 ".set\tmips3\n\t" \
697 "dmtc0\t%z0, " #register "\n\t" \
698 ".set\tmips0" \
699 : : "Jr" (value)); \
700 else \
701 __asm__ __volatile__( \
702 ".set\tmips64\n\t" \
703 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
704 ".set\tmips0" \
705 : : "Jr" (value)); \
706 } while (0)
707
708 #define __read_ulong_c0_register(reg, sel) \
709 ((sizeof(unsigned long) == 4) ? \
710 (unsigned long) __read_32bit_c0_register(reg, sel) : \
711 (unsigned long) __read_64bit_c0_register(reg, sel))
712
713 #define __write_ulong_c0_register(reg, sel, val) \
714 do { \
715 if (sizeof(unsigned long) == 4) \
716 __write_32bit_c0_register(reg, sel, val); \
717 else \
718 __write_64bit_c0_register(reg, sel, val); \
719 } while (0)
720
721 /*
722 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
723 */
724 #define __read_32bit_c0_ctrl_register(source) \
725 ({ int __res; \
726 __asm__ __volatile__( \
727 "cfc0\t%0, " #source "\n\t" \
728 : "=r" (__res)); \
729 __res; \
730 })
731
732 #define __write_32bit_c0_ctrl_register(register, value) \
733 do { \
734 __asm__ __volatile__( \
735 "ctc0\t%z0, " #register "\n\t" \
736 : : "Jr" ((unsigned int)(value))); \
737 } while (0)
738
739 /*
740 * These versions are only needed for systems with more than 38 bits of
741 * physical address space running the 32-bit kernel. That's none atm :-)
742 */
743 #define __read_64bit_c0_split(source, sel) \
744 ({ \
745 unsigned long long __val; \
746 unsigned long __flags; \
747 \
748 local_irq_save(__flags); \
749 if (sel == 0) \
750 __asm__ __volatile__( \
751 ".set\tmips64\n\t" \
752 "dmfc0\t%M0, " #source "\n\t" \
753 "dsll\t%L0, %M0, 32\n\t" \
754 "dsra\t%M0, %M0, 32\n\t" \
755 "dsra\t%L0, %L0, 32\n\t" \
756 ".set\tmips0" \
757 : "=r" (__val)); \
758 else \
759 __asm__ __volatile__( \
760 ".set\tmips64\n\t" \
761 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
762 "dsll\t%L0, %M0, 32\n\t" \
763 "dsra\t%M0, %M0, 32\n\t" \
764 "dsra\t%L0, %L0, 32\n\t" \
765 ".set\tmips0" \
766 : "=r" (__val)); \
767 local_irq_restore(__flags); \
768 \
769 __val; \
770 })
771
772 #define __write_64bit_c0_split(source, sel, val) \
773 do { \
774 unsigned long __flags; \
775 \
776 local_irq_save(__flags); \
777 if (sel == 0) \
778 __asm__ __volatile__( \
779 ".set\tmips64\n\t" \
780 "dsll\t%L0, %L0, 32\n\t" \
781 "dsrl\t%L0, %L0, 32\n\t" \
782 "dsll\t%M0, %M0, 32\n\t" \
783 "or\t%L0, %L0, %M0\n\t" \
784 "dmtc0\t%L0, " #source "\n\t" \
785 ".set\tmips0" \
786 : : "r" (val)); \
787 else \
788 __asm__ __volatile__( \
789 ".set\tmips64\n\t" \
790 "dsll\t%L0, %L0, 32\n\t" \
791 "dsrl\t%L0, %L0, 32\n\t" \
792 "dsll\t%M0, %M0, 32\n\t" \
793 "or\t%L0, %L0, %M0\n\t" \
794 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
795 ".set\tmips0" \
796 : : "r" (val)); \
797 local_irq_restore(__flags); \
798 } while (0)
799
800 #define read_c0_index() __read_32bit_c0_register($0, 0)
801 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
802
803 #define read_c0_random() __read_32bit_c0_register($1, 0)
804 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
805
806 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
807 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
808
809 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
810 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
811
812 #define read_c0_conf() __read_32bit_c0_register($3, 0)
813 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
814
815 #define read_c0_context() __read_ulong_c0_register($4, 0)
816 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
817
818 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
819 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
820
821 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
822 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
823
824 #define read_c0_wired() __read_32bit_c0_register($6, 0)
825 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
826
827 #define read_c0_info() __read_32bit_c0_register($7, 0)
828
829 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
830 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
831
832 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
833 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
834
835 #define read_c0_count() __read_32bit_c0_register($9, 0)
836 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
837
838 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
839 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
840
841 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
842 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
843
844 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
845 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
846
847 #define read_c0_compare() __read_32bit_c0_register($11, 0)
848 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
849
850 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
851 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
852
853 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
854 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
855
856 #define read_c0_status() __read_32bit_c0_register($12, 0)
857 #ifdef CONFIG_MIPS_MT_SMTC
858 #define write_c0_status(val) \
859 do { \
860 __write_32bit_c0_register($12, 0, val); \
861 __ehb(); \
862 } while (0)
863 #else
864 /*
865 * Legacy non-SMTC code, which may be hazardous
866 * but which might not support EHB
867 */
868 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
869 #endif /* CONFIG_MIPS_MT_SMTC */
870
871 #define read_c0_cause() __read_32bit_c0_register($13, 0)
872 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
873
874 #define read_c0_epc() __read_ulong_c0_register($14, 0)
875 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
876
877 #define read_c0_prid() __read_32bit_c0_register($15, 0)
878
879 #define read_c0_config() __read_32bit_c0_register($16, 0)
880 #define read_c0_config1() __read_32bit_c0_register($16, 1)
881 #define read_c0_config2() __read_32bit_c0_register($16, 2)
882 #define read_c0_config3() __read_32bit_c0_register($16, 3)
883 #define read_c0_config4() __read_32bit_c0_register($16, 4)
884 #define read_c0_config5() __read_32bit_c0_register($16, 5)
885 #define read_c0_config6() __read_32bit_c0_register($16, 6)
886 #define read_c0_config7() __read_32bit_c0_register($16, 7)
887 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
888 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
889 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
890 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
891 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
892 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
893 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
894 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
895
896 /*
897 * The WatchLo register. There may be upto 8 of them.
898 */
899 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
900 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
901 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
902 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
903 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
904 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
905 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
906 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
907 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
908 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
909 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
910 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
911 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
912 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
913 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
914 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
915
916 /*
917 * The WatchHi register. There may be upto 8 of them.
918 */
919 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
920 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
921 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
922 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
923 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
924 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
925 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
926 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
927
928 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
929 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
930 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
931 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
932 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
933 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
934 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
935 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
936
937 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
938 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
939
940 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
941 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
942
943 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
944 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
945
946 /* RM9000 PerfControl performance counter control register */
947 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
948 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
949
950 #define read_c0_diag() __read_32bit_c0_register($22, 0)
951 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
952
953 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
954 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
955
956 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
957 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
958
959 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
960 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
961
962 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
963 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
964
965 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
966 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
967
968 #define read_c0_debug() __read_32bit_c0_register($23, 0)
969 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
970
971 #define read_c0_depc() __read_ulong_c0_register($24, 0)
972 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
973
974 /*
975 * MIPS32 / MIPS64 performance counters
976 */
977 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
978 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
979 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
980 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
981 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
982 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
983 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
984 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
985 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
986 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
987 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
988 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
989 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
990 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
991 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
992 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
993
994 /* RM9000 PerfCount performance counter register */
995 #define read_c0_perfcount() __read_64bit_c0_register($25, 0)
996 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
997
998 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
999 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1000
1001 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1002 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1003
1004 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1005
1006 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1007 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1008
1009 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1010 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1011
1012 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1013 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1014
1015 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1016 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1017
1018 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1019 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1020
1021 /* MIPSR2 */
1022 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1023 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1024
1025 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1026 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1027
1028 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1029 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1030
1031 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1032 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1033
1034 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1035 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1036
1037
1038 /* Cavium OCTEON (cnMIPS) */
1039 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1040 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1041
1042 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1043 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1044
1045 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1046 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1047 /*
1048 * The cacheerr registers are not standardized. On OCTEON, they are
1049 * 64 bits wide.
1050 */
1051 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1052 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1053
1054 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1055 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1056
1057 /*
1058 * Macros to access the floating point coprocessor control registers
1059 */
1060 #define read_32bit_cp1_register(source) \
1061 ({ int __res; \
1062 __asm__ __volatile__( \
1063 ".set\tpush\n\t" \
1064 ".set\treorder\n\t" \
1065 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
1066 ".set\tmips1\n\t" \
1067 "cfc1\t%0,"STR(source)"\n\t" \
1068 ".set\tpop" \
1069 : "=r" (__res)); \
1070 __res;})
1071
1072 #define rddsp(mask) \
1073 ({ \
1074 unsigned int __res; \
1075 \
1076 __asm__ __volatile__( \
1077 " .set push \n" \
1078 " .set noat \n" \
1079 " # rddsp $1, %x1 \n" \
1080 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1081 " move %0, $1 \n" \
1082 " .set pop \n" \
1083 : "=r" (__res) \
1084 : "i" (mask)); \
1085 __res; \
1086 })
1087
1088 #define wrdsp(val, mask) \
1089 do { \
1090 __asm__ __volatile__( \
1091 " .set push \n" \
1092 " .set noat \n" \
1093 " move $1, %0 \n" \
1094 " # wrdsp $1, %x1 \n" \
1095 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1096 " .set pop \n" \
1097 : \
1098 : "r" (val), "i" (mask)); \
1099 } while (0)
1100
1101 #if 0 /* Need DSP ASE capable assembler ... */
1102 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1103 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1104 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1105 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1106
1107 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1108 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1109 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1110 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1111
1112 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1113 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1114 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1115 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1116
1117 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1118 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1119 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1120 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1121
1122 #else
1123
1124 #define mfhi0() \
1125 ({ \
1126 unsigned long __treg; \
1127 \
1128 __asm__ __volatile__( \
1129 " .set push \n" \
1130 " .set noat \n" \
1131 " # mfhi %0, $ac0 \n" \
1132 " .word 0x00000810 \n" \
1133 " move %0, $1 \n" \
1134 " .set pop \n" \
1135 : "=r" (__treg)); \
1136 __treg; \
1137 })
1138
1139 #define mfhi1() \
1140 ({ \
1141 unsigned long __treg; \
1142 \
1143 __asm__ __volatile__( \
1144 " .set push \n" \
1145 " .set noat \n" \
1146 " # mfhi %0, $ac1 \n" \
1147 " .word 0x00200810 \n" \
1148 " move %0, $1 \n" \
1149 " .set pop \n" \
1150 : "=r" (__treg)); \
1151 __treg; \
1152 })
1153
1154 #define mfhi2() \
1155 ({ \
1156 unsigned long __treg; \
1157 \
1158 __asm__ __volatile__( \
1159 " .set push \n" \
1160 " .set noat \n" \
1161 " # mfhi %0, $ac2 \n" \
1162 " .word 0x00400810 \n" \
1163 " move %0, $1 \n" \
1164 " .set pop \n" \
1165 : "=r" (__treg)); \
1166 __treg; \
1167 })
1168
1169 #define mfhi3() \
1170 ({ \
1171 unsigned long __treg; \
1172 \
1173 __asm__ __volatile__( \
1174 " .set push \n" \
1175 " .set noat \n" \
1176 " # mfhi %0, $ac3 \n" \
1177 " .word 0x00600810 \n" \
1178 " move %0, $1 \n" \
1179 " .set pop \n" \
1180 : "=r" (__treg)); \
1181 __treg; \
1182 })
1183
1184 #define mflo0() \
1185 ({ \
1186 unsigned long __treg; \
1187 \
1188 __asm__ __volatile__( \
1189 " .set push \n" \
1190 " .set noat \n" \
1191 " # mflo %0, $ac0 \n" \
1192 " .word 0x00000812 \n" \
1193 " move %0, $1 \n" \
1194 " .set pop \n" \
1195 : "=r" (__treg)); \
1196 __treg; \
1197 })
1198
1199 #define mflo1() \
1200 ({ \
1201 unsigned long __treg; \
1202 \
1203 __asm__ __volatile__( \
1204 " .set push \n" \
1205 " .set noat \n" \
1206 " # mflo %0, $ac1 \n" \
1207 " .word 0x00200812 \n" \
1208 " move %0, $1 \n" \
1209 " .set pop \n" \
1210 : "=r" (__treg)); \
1211 __treg; \
1212 })
1213
1214 #define mflo2() \
1215 ({ \
1216 unsigned long __treg; \
1217 \
1218 __asm__ __volatile__( \
1219 " .set push \n" \
1220 " .set noat \n" \
1221 " # mflo %0, $ac2 \n" \
1222 " .word 0x00400812 \n" \
1223 " move %0, $1 \n" \
1224 " .set pop \n" \
1225 : "=r" (__treg)); \
1226 __treg; \
1227 })
1228
1229 #define mflo3() \
1230 ({ \
1231 unsigned long __treg; \
1232 \
1233 __asm__ __volatile__( \
1234 " .set push \n" \
1235 " .set noat \n" \
1236 " # mflo %0, $ac3 \n" \
1237 " .word 0x00600812 \n" \
1238 " move %0, $1 \n" \
1239 " .set pop \n" \
1240 : "=r" (__treg)); \
1241 __treg; \
1242 })
1243
1244 #define mthi0(x) \
1245 do { \
1246 __asm__ __volatile__( \
1247 " .set push \n" \
1248 " .set noat \n" \
1249 " move $1, %0 \n" \
1250 " # mthi $1, $ac0 \n" \
1251 " .word 0x00200011 \n" \
1252 " .set pop \n" \
1253 : \
1254 : "r" (x)); \
1255 } while (0)
1256
1257 #define mthi1(x) \
1258 do { \
1259 __asm__ __volatile__( \
1260 " .set push \n" \
1261 " .set noat \n" \
1262 " move $1, %0 \n" \
1263 " # mthi $1, $ac1 \n" \
1264 " .word 0x00200811 \n" \
1265 " .set pop \n" \
1266 : \
1267 : "r" (x)); \
1268 } while (0)
1269
1270 #define mthi2(x) \
1271 do { \
1272 __asm__ __volatile__( \
1273 " .set push \n" \
1274 " .set noat \n" \
1275 " move $1, %0 \n" \
1276 " # mthi $1, $ac2 \n" \
1277 " .word 0x00201011 \n" \
1278 " .set pop \n" \
1279 : \
1280 : "r" (x)); \
1281 } while (0)
1282
1283 #define mthi3(x) \
1284 do { \
1285 __asm__ __volatile__( \
1286 " .set push \n" \
1287 " .set noat \n" \
1288 " move $1, %0 \n" \
1289 " # mthi $1, $ac3 \n" \
1290 " .word 0x00201811 \n" \
1291 " .set pop \n" \
1292 : \
1293 : "r" (x)); \
1294 } while (0)
1295
1296 #define mtlo0(x) \
1297 do { \
1298 __asm__ __volatile__( \
1299 " .set push \n" \
1300 " .set noat \n" \
1301 " move $1, %0 \n" \
1302 " # mtlo $1, $ac0 \n" \
1303 " .word 0x00200013 \n" \
1304 " .set pop \n" \
1305 : \
1306 : "r" (x)); \
1307 } while (0)
1308
1309 #define mtlo1(x) \
1310 do { \
1311 __asm__ __volatile__( \
1312 " .set push \n" \
1313 " .set noat \n" \
1314 " move $1, %0 \n" \
1315 " # mtlo $1, $ac1 \n" \
1316 " .word 0x00200813 \n" \
1317 " .set pop \n" \
1318 : \
1319 : "r" (x)); \
1320 } while (0)
1321
1322 #define mtlo2(x) \
1323 do { \
1324 __asm__ __volatile__( \
1325 " .set push \n" \
1326 " .set noat \n" \
1327 " move $1, %0 \n" \
1328 " # mtlo $1, $ac2 \n" \
1329 " .word 0x00201013 \n" \
1330 " .set pop \n" \
1331 : \
1332 : "r" (x)); \
1333 } while (0)
1334
1335 #define mtlo3(x) \
1336 do { \
1337 __asm__ __volatile__( \
1338 " .set push \n" \
1339 " .set noat \n" \
1340 " move $1, %0 \n" \
1341 " # mtlo $1, $ac3 \n" \
1342 " .word 0x00201813 \n" \
1343 " .set pop \n" \
1344 : \
1345 : "r" (x)); \
1346 } while (0)
1347
1348 #endif
1349
1350 /*
1351 * TLB operations.
1352 *
1353 * It is responsibility of the caller to take care of any TLB hazards.
1354 */
1355 static inline void tlb_probe(void)
1356 {
1357 __asm__ __volatile__(
1358 ".set noreorder\n\t"
1359 "tlbp\n\t"
1360 ".set reorder");
1361 }
1362
1363 static inline void tlb_read(void)
1364 {
1365 #if MIPS34K_MISSED_ITLB_WAR
1366 int res = 0;
1367
1368 __asm__ __volatile__(
1369 " .set push \n"
1370 " .set noreorder \n"
1371 " .set noat \n"
1372 " .set mips32r2 \n"
1373 " .word 0x41610001 # dvpe $1 \n"
1374 " move %0, $1 \n"
1375 " ehb \n"
1376 " .set pop \n"
1377 : "=r" (res));
1378
1379 instruction_hazard();
1380 #endif
1381
1382 __asm__ __volatile__(
1383 ".set noreorder\n\t"
1384 "tlbr\n\t"
1385 ".set reorder");
1386
1387 #if MIPS34K_MISSED_ITLB_WAR
1388 if ((res & _ULCAST_(1)))
1389 __asm__ __volatile__(
1390 " .set push \n"
1391 " .set noreorder \n"
1392 " .set noat \n"
1393 " .set mips32r2 \n"
1394 " .word 0x41600021 # evpe \n"
1395 " ehb \n"
1396 " .set pop \n");
1397 #endif
1398 }
1399
1400 static inline void tlb_write_indexed(void)
1401 {
1402 __asm__ __volatile__(
1403 ".set noreorder\n\t"
1404 "tlbwi\n\t"
1405 ".set reorder");
1406 }
1407
1408 static inline void tlb_write_random(void)
1409 {
1410 __asm__ __volatile__(
1411 ".set noreorder\n\t"
1412 "tlbwr\n\t"
1413 ".set reorder");
1414 }
1415
1416 /*
1417 * Manipulate bits in a c0 register.
1418 */
1419 #ifndef CONFIG_MIPS_MT_SMTC
1420 /*
1421 * SMTC Linux requires shutting-down microthread scheduling
1422 * during CP0 register read-modify-write sequences.
1423 */
1424 #define __BUILD_SET_C0(name) \
1425 static inline unsigned int \
1426 set_c0_##name(unsigned int set) \
1427 { \
1428 unsigned int res, new; \
1429 \
1430 res = read_c0_##name(); \
1431 new = res | set; \
1432 write_c0_##name(new); \
1433 \
1434 return res; \
1435 } \
1436 \
1437 static inline unsigned int \
1438 clear_c0_##name(unsigned int clear) \
1439 { \
1440 unsigned int res, new; \
1441 \
1442 res = read_c0_##name(); \
1443 new = res & ~clear; \
1444 write_c0_##name(new); \
1445 \
1446 return res; \
1447 } \
1448 \
1449 static inline unsigned int \
1450 change_c0_##name(unsigned int change, unsigned int val) \
1451 { \
1452 unsigned int res, new; \
1453 \
1454 res = read_c0_##name(); \
1455 new = res & ~change; \
1456 new |= (val & change); \
1457 write_c0_##name(new); \
1458 \
1459 return res; \
1460 }
1461
1462 #else /* SMTC versions that manage MT scheduling */
1463
1464 #include <linux/irqflags.h>
1465
1466 /*
1467 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1468 * header file recursion.
1469 */
1470 static inline unsigned int __dmt(void)
1471 {
1472 int res;
1473
1474 __asm__ __volatile__(
1475 " .set push \n"
1476 " .set mips32r2 \n"
1477 " .set noat \n"
1478 " .word 0x41610BC1 # dmt $1 \n"
1479 " ehb \n"
1480 " move %0, $1 \n"
1481 " .set pop \n"
1482 : "=r" (res));
1483
1484 instruction_hazard();
1485
1486 return res;
1487 }
1488
1489 #define __VPECONTROL_TE_SHIFT 15
1490 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT)
1491
1492 #define __EMT_ENABLE __VPECONTROL_TE
1493
1494 static inline void __emt(unsigned int previous)
1495 {
1496 if ((previous & __EMT_ENABLE))
1497 __asm__ __volatile__(
1498 " .set mips32r2 \n"
1499 " .word 0x41600be1 # emt \n"
1500 " ehb \n"
1501 " .set mips0 \n");
1502 }
1503
1504 static inline void __ehb(void)
1505 {
1506 __asm__ __volatile__(
1507 " .set mips32r2 \n"
1508 " ehb \n" " .set mips0 \n");
1509 }
1510
1511 /*
1512 * Note that local_irq_save/restore affect TC-specific IXMT state,
1513 * not Status.IE as in non-SMTC kernel.
1514 */
1515
1516 #define __BUILD_SET_C0(name) \
1517 static inline unsigned int \
1518 set_c0_##name(unsigned int set) \
1519 { \
1520 unsigned int res; \
1521 unsigned int new; \
1522 unsigned int omt; \
1523 unsigned long flags; \
1524 \
1525 local_irq_save(flags); \
1526 omt = __dmt(); \
1527 res = read_c0_##name(); \
1528 new = res | set; \
1529 write_c0_##name(new); \
1530 __emt(omt); \
1531 local_irq_restore(flags); \
1532 \
1533 return res; \
1534 } \
1535 \
1536 static inline unsigned int \
1537 clear_c0_##name(unsigned int clear) \
1538 { \
1539 unsigned int res; \
1540 unsigned int new; \
1541 unsigned int omt; \
1542 unsigned long flags; \
1543 \
1544 local_irq_save(flags); \
1545 omt = __dmt(); \
1546 res = read_c0_##name(); \
1547 new = res & ~clear; \
1548 write_c0_##name(new); \
1549 __emt(omt); \
1550 local_irq_restore(flags); \
1551 \
1552 return res; \
1553 } \
1554 \
1555 static inline unsigned int \
1556 change_c0_##name(unsigned int change, unsigned int newbits) \
1557 { \
1558 unsigned int res; \
1559 unsigned int new; \
1560 unsigned int omt; \
1561 unsigned long flags; \
1562 \
1563 local_irq_save(flags); \
1564 \
1565 omt = __dmt(); \
1566 res = read_c0_##name(); \
1567 new = res & ~change; \
1568 new |= (newbits & change); \
1569 write_c0_##name(new); \
1570 __emt(omt); \
1571 local_irq_restore(flags); \
1572 \
1573 return res; \
1574 }
1575 #endif
1576
1577 __BUILD_SET_C0(status)
1578 __BUILD_SET_C0(cause)
1579 __BUILD_SET_C0(config)
1580 __BUILD_SET_C0(intcontrol)
1581 __BUILD_SET_C0(intctl)
1582 __BUILD_SET_C0(srsmap)
1583
1584 #endif /* !__ASSEMBLY__ */
1585
1586 #endif /* _ASM_MIPSREGS_H */
Linux MOXA ART SoC ARM port