arch/x86/include/asm/apicdef.h

   1 #ifndef _ASM_X86_APICDEF_H
   2 #define _ASM_X86_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define IO_APIC_DEFAULT_PHYS_BASE       0xfec00000
  12 #define APIC_DEFAULT_PHYS_BASE          0xfee00000
  13
  14 #define APIC_ID         0x20
  15
  16 #define APIC_LVR        0x30
  17 #define         APIC_LVR_MASK           0xFF00FF
  18 #define         APIC_LVR_DIRECTED_EOI   (1 << 24)
  19 #define         GET_APIC_VERSION(x)     ((x) & 0xFFu)
  20 #define         GET_APIC_MAXLVT(x)      (((x) >> 16) & 0xFFu)
  21 #ifdef CONFIG_X86_32
  22 #  define       APIC_INTEGRATED(x)      ((x) & 0xF0u)
  23 #else
  24 #  define       APIC_INTEGRATED(x)      (1)
  25 #endif
  26 #define         APIC_XAPIC(x)           ((x) >= 0x14)
  27 #define         APIC_EXT_SPACE(x)       ((x) & 0x80000000)
  28 #define APIC_TASKPRI    0x80
  29 #define         APIC_TPRI_MASK          0xFFu
  30 #define APIC_ARBPRI     0x90
  31 #define         APIC_ARBPRI_MASK        0xFFu
  32 #define APIC_PROCPRI    0xA0
  33 #define APIC_EOI        0xB0
  34 #define         APIC_EIO_ACK            0x0
  35 #define APIC_RRR        0xC0
  36 #define APIC_LDR        0xD0
  37 #define         APIC_LDR_MASK           (0xFFu << 24)
  38 #define         GET_APIC_LOGICAL_ID(x)  (((x) >> 24) & 0xFFu)
  39 #define         SET_APIC_LOGICAL_ID(x)  (((x) << 24))
  40 #define         APIC_ALL_CPUS           0xFFu
  41 #define APIC_DFR        0xE0
  42 #define         APIC_DFR_CLUSTER                0x0FFFFFFFul
  43 #define         APIC_DFR_FLAT                   0xFFFFFFFFul
  44 #define APIC_SPIV       0xF0
  45 #define         APIC_SPIV_DIRECTED_EOI          (1 << 12)
  46 #define         APIC_SPIV_FOCUS_DISABLED        (1 << 9)
  47 #define         APIC_SPIV_APIC_ENABLED          (1 << 8)
  48 #define APIC_ISR        0x100
  49 #define APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
  50 #define APIC_TMR        0x180
  51 #define APIC_IRR        0x200
  52 #define APIC_ESR        0x280
  53 #define         APIC_ESR_SEND_CS        0x00001
  54 #define         APIC_ESR_RECV_CS        0x00002
  55 #define         APIC_ESR_SEND_ACC       0x00004
  56 #define         APIC_ESR_RECV_ACC       0x00008
  57 #define         APIC_ESR_SENDILL        0x00020
  58 #define         APIC_ESR_RECVILL        0x00040
  59 #define         APIC_ESR_ILLREGA        0x00080
  60 #define         APIC_LVTCMCI    0x2f0
  61 #define APIC_ICR        0x300
  62 #define         APIC_DEST_SELF          0x40000
  63 #define         APIC_DEST_ALLINC        0x80000
  64 #define         APIC_DEST_ALLBUT        0xC0000
  65 #define         APIC_ICR_RR_MASK        0x30000
  66 #define         APIC_ICR_RR_INVALID     0x00000
  67 #define         APIC_ICR_RR_INPROG      0x10000
  68 #define         APIC_ICR_RR_VALID       0x20000
  69 #define         APIC_INT_LEVELTRIG      0x08000
  70 #define         APIC_INT_ASSERT         0x04000
  71 #define         APIC_ICR_BUSY           0x01000
  72 #define         APIC_DEST_LOGICAL       0x00800
  73 #define         APIC_DEST_PHYSICAL      0x00000
  74 #define         APIC_DM_FIXED           0x00000
  75 #define         APIC_DM_FIXED_MASK      0x00700
  76 #define         APIC_DM_LOWEST          0x00100
  77 #define         APIC_DM_SMI             0x00200
  78 #define         APIC_DM_REMRD           0x00300
  79 #define         APIC_DM_NMI             0x00400
  80 #define         APIC_DM_INIT            0x00500
  81 #define         APIC_DM_STARTUP         0x00600
  82 #define         APIC_DM_EXTINT          0x00700
  83 #define         APIC_VECTOR_MASK        0x000FF
  84 #define APIC_ICR2       0x310
  85 #define         GET_APIC_DEST_FIELD(x)  (((x) >> 24) & 0xFF)
  86 #define         SET_APIC_DEST_FIELD(x)  ((x) << 24)
  87 #define APIC_LVTT       0x320
  88 #define APIC_LVTTHMR    0x330
  89 #define APIC_LVTPC      0x340
  90 #define APIC_LVT0       0x350
  91 #define         APIC_LVT_TIMER_BASE_MASK        (0x3 << 18)
  92 #define         GET_APIC_TIMER_BASE(x)          (((x) >> 18) & 0x3)
  93 #define         SET_APIC_TIMER_BASE(x)          (((x) << 18))
  94 #define         APIC_TIMER_BASE_CLKIN           0x0
  95 #define         APIC_TIMER_BASE_TMBASE          0x1
  96 #define         APIC_TIMER_BASE_DIV             0x2
  97 #define         APIC_LVT_TIMER_PERIODIC         (1 << 17)
  98 #define         APIC_LVT_MASKED                 (1 << 16)
  99 #define         APIC_LVT_LEVEL_TRIGGER          (1 << 15)
 100 #define         APIC_LVT_REMOTE_IRR             (1 << 14)
 101 #define         APIC_INPUT_POLARITY             (1 << 13)
 102 #define         APIC_SEND_PENDING               (1 << 12)
 103 #define         APIC_MODE_MASK                  0x700
 104 #define         GET_APIC_DELIVERY_MODE(x)       (((x) >> 8) & 0x7)
 105 #define         SET_APIC_DELIVERY_MODE(x, y)    (((x) & ~0x700) | ((y) << 8))
 106 #define                 APIC_MODE_FIXED         0x0
 107 #define                 APIC_MODE_NMI           0x4
 108 #define                 APIC_MODE_EXTINT        0x7
 109 #define APIC_LVT1       0x360
 110 #define APIC_LVTERR     0x370
 111 #define APIC_TMICT      0x380
 112 #define APIC_TMCCT      0x390
 113 #define APIC_TDCR       0x3E0
 114 #define APIC_SELF_IPI   0x3F0
 115 #define         APIC_TDR_DIV_TMBASE     (1 << 2)
 116 #define         APIC_TDR_DIV_1          0xB
 117 #define         APIC_TDR_DIV_2          0x0
 118 #define         APIC_TDR_DIV_4          0x1
 119 #define         APIC_TDR_DIV_8          0x2
 120 #define         APIC_TDR_DIV_16         0x3
 121 #define         APIC_TDR_DIV_32         0x8
 122 #define         APIC_TDR_DIV_64         0x9
 123 #define         APIC_TDR_DIV_128        0xA
 124 #define APIC_EFEAT      0x400
 125 #define APIC_ECTRL      0x410
 126 #define APIC_EILVTn(n)  (0x500 + 0x10 * n)
 127 #define         APIC_EILVT_NR_AMD_K8    1       /* # of extended interrupts */
 128 #define         APIC_EILVT_NR_AMD_10H   4
 129 #define         APIC_EILVT_LVTOFF(x)    (((x) >> 4) & 0xF)
 130 #define         APIC_EILVT_MSG_FIX      0x0
 131 #define         APIC_EILVT_MSG_SMI      0x2
 132 #define         APIC_EILVT_MSG_NMI      0x4
 133 #define         APIC_EILVT_MSG_EXT      0x7
 134 #define         APIC_EILVT_MASKED       (1 << 16)
 135
 136 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 137 #define APIC_BASE_MSR   0x800
 138 #define X2APIC_ENABLE   (1UL << 10)
 139
 140 #ifdef CONFIG_X86_32
 141 # define MAX_IO_APICS 64
 142 #else
 143 # define MAX_IO_APICS 128
 144 # define MAX_LOCAL_APIC 32768
 145 #endif
 146
 147 /*
 148  * All x86-64 systems are xAPIC compatible.
 149  * In the following, "apicid" is a physical APIC ID.
 150  */
 151 #define XAPIC_DEST_CPUS_SHIFT   4
 152 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
 153 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
 154 #define APIC_CLUSTER(apicid)    ((apicid) & XAPIC_DEST_CLUSTER_MASK)
 155 #define APIC_CLUSTERID(apicid)  (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
 156 #define APIC_CPUID(apicid)      ((apicid) & XAPIC_DEST_CPUS_MASK)
 157 #define NUM_APIC_CLUSTERS       ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
 158
 159 /*
 160  * the local APIC register structure, memory mapped. Not terribly well
 161  * tested, but we might eventually use this one in the future - the
 162  * problem why we cannot use it right now is the P5 APIC, it has an
 163  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 164  */
 165 #define u32 unsigned int
 166
 167 struct local_apic {
 168
 169 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 170
 171 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 172
 173 /*020*/ struct { /* APIC ID Register */
 174                 u32   __reserved_1      : 24,
 175                         phys_apic_id    :  4,
 176                         __reserved_2    :  4;
 177                 u32 __reserved[3];
 178         } id;
 179
 180 /*030*/ const
 181         struct { /* APIC Version Register */
 182                 u32   version           :  8,
 183                         __reserved_1    :  8,
 184                         max_lvt         :  8,
 185                         __reserved_2    :  8;
 186                 u32 __reserved[3];
 187         } version;
 188
 189 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 190
 191 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 192
 193 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 194
 195 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 196
 197 /*080*/ struct { /* Task Priority Register */
 198                 u32   priority  :  8,
 199                         __reserved_1    : 24;
 200                 u32 __reserved_2[3];
 201         } tpr;
 202
 203 /*090*/ const
 204         struct { /* Arbitration Priority Register */
 205                 u32   priority  :  8,
 206                         __reserved_1    : 24;
 207                 u32 __reserved_2[3];
 208         } apr;
 209
 210 /*0A0*/ const
 211         struct { /* Processor Priority Register */
 212                 u32   priority  :  8,
 213                         __reserved_1    : 24;
 214                 u32 __reserved_2[3];
 215         } ppr;
 216
 217 /*0B0*/ struct { /* End Of Interrupt Register */
 218                 u32   eoi;
 219                 u32 __reserved[3];
 220         } eoi;
 221
 222 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 223
 224 /*0D0*/ struct { /* Logical Destination Register */
 225                 u32   __reserved_1      : 24,
 226                         logical_dest    :  8;
 227                 u32 __reserved_2[3];
 228         } ldr;
 229
 230 /*0E0*/ struct { /* Destination Format Register */
 231                 u32   __reserved_1      : 28,
 232                         model           :  4;
 233                 u32 __reserved_2[3];
 234         } dfr;
 235
 236 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 237                 u32     spurious_vector :  8,
 238                         apic_enabled    :  1,
 239                         focus_cpu       :  1,
 240                         __reserved_2    : 22;
 241                 u32 __reserved_3[3];
 242         } svr;
 243
 244 /*100*/ struct { /* In Service Register */
 245 /*170*/         u32 bitfield;
 246                 u32 __reserved[3];
 247         } isr [8];
 248
 249 /*180*/ struct { /* Trigger Mode Register */
 250 /*1F0*/         u32 bitfield;
 251                 u32 __reserved[3];
 252         } tmr [8];
 253
 254 /*200*/ struct { /* Interrupt Request Register */
 255 /*270*/         u32 bitfield;
 256                 u32 __reserved[3];
 257         } irr [8];
 258
 259 /*280*/ union { /* Error Status Register */
 260                 struct {
 261                         u32   send_cs_error                     :  1,
 262                                 receive_cs_error                :  1,
 263                                 send_accept_error               :  1,
 264                                 receive_accept_error            :  1,
 265                                 __reserved_1                    :  1,
 266                                 send_illegal_vector             :  1,
 267                                 receive_illegal_vector          :  1,
 268                                 illegal_register_address        :  1,
 269                                 __reserved_2                    : 24;
 270                         u32 __reserved_3[3];
 271                 } error_bits;
 272                 struct {
 273                         u32 errors;
 274                         u32 __reserved_3[3];
 275                 } all_errors;
 276         } esr;
 277
 278 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 279
 280 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 281
 282 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 283
 284 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 285
 286 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 287
 288 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 289
 290 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 291
 292 /*300*/ struct { /* Interrupt Command Register 1 */
 293                 u32   vector                    :  8,
 294                         delivery_mode           :  3,
 295                         destination_mode        :  1,
 296                         delivery_status         :  1,
 297                         __reserved_1            :  1,
 298                         level                   :  1,
 299                         trigger                 :  1,
 300                         __reserved_2            :  2,
 301                         shorthand               :  2,
 302                         __reserved_3            :  12;
 303                 u32 __reserved_4[3];
 304         } icr1;
 305
 306 /*310*/ struct { /* Interrupt Command Register 2 */
 307                 union {
 308                         u32   __reserved_1      : 24,
 309                                 phys_dest       :  4,
 310                                 __reserved_2    :  4;
 311                         u32   __reserved_3      : 24,
 312                                 logical_dest    :  8;
 313                 } dest;
 314                 u32 __reserved_4[3];
 315         } icr2;
 316
 317 /*320*/ struct { /* LVT - Timer */
 318                 u32   vector            :  8,
 319                         __reserved_1    :  4,
 320                         delivery_status :  1,
 321                         __reserved_2    :  3,
 322                         mask            :  1,
 323                         timer_mode      :  1,
 324                         __reserved_3    : 14;
 325                 u32 __reserved_4[3];
 326         } lvt_timer;
 327
 328 /*330*/ struct { /* LVT - Thermal Sensor */
 329                 u32  vector             :  8,
 330                         delivery_mode   :  3,
 331                         __reserved_1    :  1,
 332                         delivery_status :  1,
 333                         __reserved_2    :  3,
 334                         mask            :  1,
 335                         __reserved_3    : 15;
 336                 u32 __reserved_4[3];
 337         } lvt_thermal;
 338
 339 /*340*/ struct { /* LVT - Performance Counter */
 340                 u32   vector            :  8,
 341                         delivery_mode   :  3,
 342                         __reserved_1    :  1,
 343                         delivery_status :  1,
 344                         __reserved_2    :  3,
 345                         mask            :  1,
 346                         __reserved_3    : 15;
 347                 u32 __reserved_4[3];
 348         } lvt_pc;
 349
 350 /*350*/ struct { /* LVT - LINT0 */
 351                 u32   vector            :  8,
 352                         delivery_mode   :  3,
 353                         __reserved_1    :  1,
 354                         delivery_status :  1,
 355                         polarity        :  1,
 356                         remote_irr      :  1,
 357                         trigger         :  1,
 358                         mask            :  1,
 359                         __reserved_2    : 15;
 360                 u32 __reserved_3[3];
 361         } lvt_lint0;
 362
 363 /*360*/ struct { /* LVT - LINT1 */
 364                 u32   vector            :  8,
 365                         delivery_mode   :  3,
 366                         __reserved_1    :  1,
 367                         delivery_status :  1,
 368                         polarity        :  1,
 369                         remote_irr      :  1,
 370                         trigger         :  1,
 371                         mask            :  1,
 372                         __reserved_2    : 15;
 373                 u32 __reserved_3[3];
 374         } lvt_lint1;
 375
 376 /*370*/ struct { /* LVT - Error */
 377                 u32   vector            :  8,
 378                         __reserved_1    :  4,
 379                         delivery_status :  1,
 380                         __reserved_2    :  3,
 381                         mask            :  1,
 382                         __reserved_3    : 15;
 383                 u32 __reserved_4[3];
 384         } lvt_error;
 385
 386 /*380*/ struct { /* Timer Initial Count Register */
 387                 u32   initial_count;
 388                 u32 __reserved_2[3];
 389         } timer_icr;
 390
 391 /*390*/ const
 392         struct { /* Timer Current Count Register */
 393                 u32   curr_count;
 394                 u32 __reserved_2[3];
 395         } timer_ccr;
 396
 397 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 398
 399 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 400
 401 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 402
 403 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 404
 405 /*3E0*/ struct { /* Timer Divide Configuration Register */
 406                 u32   divisor           :  4,
 407                         __reserved_1    : 28;
 408                 u32 __reserved_2[3];
 409         } timer_dcr;
 410
 411 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 412
 413 } __attribute__ ((packed));
 414
 415 #undef u32
 416
 417 #ifdef CONFIG_X86_32
 418  #define BAD_APICID 0xFFu
 419 #else
 420  #define BAD_APICID 0xFFFFu
 421 #endif
 422 #endif /* _ASM_X86_APICDEF_H */