arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/cpu.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/uv/uv_mmrs.h>
  25 #include <asm/uv/uv_hub.h>
  26 #include <asm/current.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/bios.h>
  29 #include <asm/uv/uv.h>
  30 #include <asm/apic.h>
  31 #include <asm/ipi.h>
  32 #include <asm/smp.h>
  33
  34 DEFINE_PER_CPU(int, x2apic_extra_bits);
  35
  36 static enum uv_system_type uv_system_type;
  37
  38 static int early_get_nodeid(void)
  39 {
  40         union uvh_node_id_u node_id;
  41         unsigned long *mmr;
  42
  43         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
  44         node_id.v = *mmr;
  45         early_iounmap(mmr, sizeof(*mmr));
  46         return node_id.s.node_id;
  47 }
  48
  49 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  50 {
  51         if (!strcmp(oem_id, "SGI")) {
  52                 if (!strcmp(oem_table_id, "UVL"))
  53                         uv_system_type = UV_LEGACY_APIC;
  54                 else if (!strcmp(oem_table_id, "UVX"))
  55                         uv_system_type = UV_X2APIC;
  56                 else if (!strcmp(oem_table_id, "UVH")) {
  57                         __get_cpu_var(x2apic_extra_bits) =
  58                                 early_get_nodeid() << (UV_APIC_PNODE_SHIFT - 1);
  59                         uv_system_type = UV_NON_UNIQUE_APIC;
  60                         return 1;
  61                 }
  62         }
  63         return 0;
  64 }
  65
  66 enum uv_system_type get_uv_system_type(void)
  67 {
  68         return uv_system_type;
  69 }
  70
  71 int is_uv_system(void)
  72 {
  73         return uv_system_type != UV_NONE;
  74 }
  75 EXPORT_SYMBOL_GPL(is_uv_system);
  76
  77 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  78 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  79
  80 struct uv_blade_info *uv_blade_info;
  81 EXPORT_SYMBOL_GPL(uv_blade_info);
  82
  83 short *uv_node_to_blade;
  84 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  85
  86 short *uv_cpu_to_blade;
  87 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  88
  89 short uv_possible_blades;
  90 EXPORT_SYMBOL_GPL(uv_possible_blades);
  91
  92 unsigned long sn_rtc_cycles_per_second;
  93 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  94
  95 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  96
  97 static const struct cpumask *uv_target_cpus(void)
  98 {
  99         return cpumask_of(0);
 100 }
 101
 102 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 103 {
 104         cpumask_clear(retmask);
 105         cpumask_set_cpu(cpu, retmask);
 106 }
 107
 108 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 109 {
 110 #ifdef CONFIG_SMP
 111         unsigned long val;
 112         int pnode;
 113
 114         pnode = uv_apicid_to_pnode(phys_apicid);
 115         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 116             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 117             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 118             APIC_DM_INIT;
 119         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 120
 121         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 122             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 123             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 124             APIC_DM_STARTUP;
 125         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 126
 127         atomic_set(&init_deasserted, 1);
 128 #endif
 129         return 0;
 130 }
 131
 132 static void uv_send_IPI_one(int cpu, int vector)
 133 {
 134         unsigned long apicid;
 135         int pnode;
 136
 137         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 138         pnode = uv_apicid_to_pnode(apicid);
 139         uv_hub_send_ipi(pnode, apicid, vector);
 140 }
 141
 142 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 143 {
 144         unsigned int cpu;
 145
 146         for_each_cpu(cpu, mask)
 147                 uv_send_IPI_one(cpu, vector);
 148 }
 149
 150 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 151 {
 152         unsigned int this_cpu = smp_processor_id();
 153         unsigned int cpu;
 154
 155         for_each_cpu(cpu, mask) {
 156                 if (cpu != this_cpu)
 157                         uv_send_IPI_one(cpu, vector);
 158         }
 159 }
 160
 161 static void uv_send_IPI_allbutself(int vector)
 162 {
 163         unsigned int this_cpu = smp_processor_id();
 164         unsigned int cpu;
 165
 166         for_each_online_cpu(cpu) {
 167                 if (cpu != this_cpu)
 168                         uv_send_IPI_one(cpu, vector);
 169         }
 170 }
 171
 172 static void uv_send_IPI_all(int vector)
 173 {
 174         uv_send_IPI_mask(cpu_online_mask, vector);
 175 }
 176
 177 static int uv_apic_id_registered(void)
 178 {
 179         return 1;
 180 }
 181
 182 static void uv_init_apic_ldr(void)
 183 {
 184 }
 185
 186 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 187 {
 188         /*
 189          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 190          * May as well be the first.
 191          */
 192         int cpu = cpumask_first(cpumask);
 193
 194         if ((unsigned)cpu < nr_cpu_ids)
 195                 return per_cpu(x86_cpu_to_apicid, cpu);
 196         else
 197                 return BAD_APICID;
 198 }
 199
 200 static unsigned int
 201 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 202                           const struct cpumask *andmask)
 203 {
 204         int cpu;
 205
 206         /*
 207          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 208          * May as well be the first.
 209          */
 210         for_each_cpu_and(cpu, cpumask, andmask) {
 211                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 212                         break;
 213         }
 214         if (cpu < nr_cpu_ids)
 215                 return per_cpu(x86_cpu_to_apicid, cpu);
 216
 217         return BAD_APICID;
 218 }
 219
 220 static unsigned int x2apic_get_apic_id(unsigned long x)
 221 {
 222         unsigned int id;
 223
 224         WARN_ON(preemptible() && num_online_cpus() > 1);
 225         id = x | __get_cpu_var(x2apic_extra_bits);
 226
 227         return id;
 228 }
 229
 230 static unsigned long set_apic_id(unsigned int id)
 231 {
 232         unsigned long x;
 233
 234         /* maskout x2apic_extra_bits ? */
 235         x = id;
 236         return x;
 237 }
 238
 239 static unsigned int uv_read_apic_id(void)
 240 {
 241
 242         return x2apic_get_apic_id(apic_read(APIC_ID));
 243 }
 244
 245 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 246 {
 247         return uv_read_apic_id() >> index_msb;
 248 }
 249
 250 static void uv_send_IPI_self(int vector)
 251 {
 252         apic_write(APIC_SELF_IPI, vector);
 253 }
 254
 255 struct apic __refdata apic_x2apic_uv_x = {
 256
 257         .name                           = "UV large system",
 258         .probe                          = NULL,
 259         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 260         .apic_id_registered             = uv_apic_id_registered,
 261
 262         .irq_delivery_mode              = dest_Fixed,
 263         .irq_dest_mode                  = 0, /* physical */
 264
 265         .target_cpus                    = uv_target_cpus,
 266         .disable_esr                    = 0,
 267         .dest_logical                   = APIC_DEST_LOGICAL,
 268         .check_apicid_used              = NULL,
 269         .check_apicid_present           = NULL,
 270
 271         .vector_allocation_domain       = uv_vector_allocation_domain,
 272         .init_apic_ldr                  = uv_init_apic_ldr,
 273
 274         .ioapic_phys_id_map             = NULL,
 275         .setup_apic_routing             = NULL,
 276         .multi_timer_check              = NULL,
 277         .apicid_to_node                 = NULL,
 278         .cpu_to_logical_apicid          = NULL,
 279         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 280         .apicid_to_cpu_present          = NULL,
 281         .setup_portio_remap             = NULL,
 282         .check_phys_apicid_present      = default_check_phys_apicid_present,
 283         .enable_apic_mode               = NULL,
 284         .phys_pkg_id                    = uv_phys_pkg_id,
 285         .mps_oem_check                  = NULL,
 286
 287         .get_apic_id                    = x2apic_get_apic_id,
 288         .set_apic_id                    = set_apic_id,
 289         .apic_id_mask                   = 0xFFFFFFFFu,
 290
 291         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 292         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 293
 294         .send_IPI_mask                  = uv_send_IPI_mask,
 295         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 296         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 297         .send_IPI_all                   = uv_send_IPI_all,
 298         .send_IPI_self                  = uv_send_IPI_self,
 299
 300         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 301         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 302         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 303         .wait_for_init_deassert         = NULL,
 304         .smp_callin_clear_local_apic    = NULL,
 305         .inquire_remote_apic            = NULL,
 306
 307         .read                           = native_apic_msr_read,
 308         .write                          = native_apic_msr_write,
 309         .icr_read                       = native_x2apic_icr_read,
 310         .icr_write                      = native_x2apic_icr_write,
 311         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 312         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 313 };
 314
 315 static __cpuinit void set_x2apic_extra_bits(int pnode)
 316 {
 317         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 318 }
 319
 320 /*
 321  * Called on boot cpu.
 322  */
 323 static __init int boot_pnode_to_blade(int pnode)
 324 {
 325         int blade;
 326
 327         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 328                 if (pnode == uv_blade_info[blade].pnode)
 329                         return blade;
 330         BUG();
 331 }
 332
 333 struct redir_addr {
 334         unsigned long redirect;
 335         unsigned long alias;
 336 };
 337
 338 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 339
 340 static __initdata struct redir_addr redir_addrs[] = {
 341         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 342         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 343         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 344 };
 345
 346 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 347 {
 348         union uvh_si_alias0_overlay_config_u alias;
 349         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 350         int i;
 351
 352         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 353                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 354                 if (alias.s.enable && alias.s.base == 0) {
 355                         *size = (1UL << alias.s.m_alias);
 356                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 357                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 358                         return;
 359                 }
 360         }
 361         *base = *size = 0;
 362 }
 363
 364 enum map_type {map_wb, map_uc};
 365
 366 static __init void map_high(char *id, unsigned long base, int pshift,
 367                         int bshift, int max_pnode, enum map_type map_type)
 368 {
 369         unsigned long bytes, paddr;
 370
 371         paddr = base << pshift;
 372         bytes = (1UL << bshift) * (max_pnode + 1);
 373         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 374                                                 paddr + bytes);
 375         if (map_type == map_uc)
 376                 init_extra_mapping_uc(paddr, bytes);
 377         else
 378                 init_extra_mapping_wb(paddr, bytes);
 379
 380 }
 381 static __init void map_gru_high(int max_pnode)
 382 {
 383         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 384         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 385
 386         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 387         if (gru.s.enable)
 388                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 389 }
 390
 391 static __init void map_mmr_high(int max_pnode)
 392 {
 393         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 394         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 395
 396         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 397         if (mmr.s.enable)
 398                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 399 }
 400
 401 static __init void map_mmioh_high(int max_pnode)
 402 {
 403         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 404         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 405
 406         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 407         if (mmioh.s.enable)
 408                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
 409                         max_pnode, map_uc);
 410 }
 411
 412 static __init void uv_rtc_init(void)
 413 {
 414         long status;
 415         u64 ticks_per_sec;
 416
 417         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 418                                         &ticks_per_sec);
 419         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 420                 printk(KERN_WARNING
 421                         "unable to determine platform RTC clock frequency, "
 422                         "guessing.\n");
 423                 /* BIOS gives wrong value for clock freq. so guess */
 424                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 425         } else
 426                 sn_rtc_cycles_per_second = ticks_per_sec;
 427 }
 428
 429 /*
 430  * percpu heartbeat timer
 431  */
 432 static void uv_heartbeat(unsigned long ignored)
 433 {
 434         struct timer_list *timer = &uv_hub_info->scir.timer;
 435         unsigned char bits = uv_hub_info->scir.state;
 436
 437         /* flip heartbeat bit */
 438         bits ^= SCIR_CPU_HEARTBEAT;
 439
 440         /* is this cpu idle? */
 441         if (idle_cpu(raw_smp_processor_id()))
 442                 bits &= ~SCIR_CPU_ACTIVITY;
 443         else
 444                 bits |= SCIR_CPU_ACTIVITY;
 445
 446         /* update system controller interface reg */
 447         uv_set_scir_bits(bits);
 448
 449         /* enable next timer period */
 450         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 451 }
 452
 453 static void __cpuinit uv_heartbeat_enable(int cpu)
 454 {
 455         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 456                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 457
 458                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 459                 setup_timer(timer, uv_heartbeat, cpu);
 460                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 461                 add_timer_on(timer, cpu);
 462                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 463         }
 464
 465         /* check boot cpu */
 466         if (!uv_cpu_hub_info(0)->scir.enabled)
 467                 uv_heartbeat_enable(0);
 468 }
 469
 470 #ifdef CONFIG_HOTPLUG_CPU
 471 static void __cpuinit uv_heartbeat_disable(int cpu)
 472 {
 473         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 474                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 475                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 476         }
 477         uv_set_cpu_scir_bits(cpu, 0xff);
 478 }
 479
 480 /*
 481  * cpu hotplug notifier
 482  */
 483 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 484                                        unsigned long action, void *hcpu)
 485 {
 486         long cpu = (long)hcpu;
 487
 488         switch (action) {
 489         case CPU_ONLINE:
 490                 uv_heartbeat_enable(cpu);
 491                 break;
 492         case CPU_DOWN_PREPARE:
 493                 uv_heartbeat_disable(cpu);
 494                 break;
 495         default:
 496                 break;
 497         }
 498         return NOTIFY_OK;
 499 }
 500
 501 static __init void uv_scir_register_cpu_notifier(void)
 502 {
 503         hotcpu_notifier(uv_scir_cpu_notify, 0);
 504 }
 505
 506 #else /* !CONFIG_HOTPLUG_CPU */
 507
 508 static __init void uv_scir_register_cpu_notifier(void)
 509 {
 510 }
 511
 512 static __init int uv_init_heartbeat(void)
 513 {
 514         int cpu;
 515
 516         if (is_uv_system())
 517                 for_each_online_cpu(cpu)
 518                         uv_heartbeat_enable(cpu);
 519         return 0;
 520 }
 521
 522 late_initcall(uv_init_heartbeat);
 523
 524 #endif /* !CONFIG_HOTPLUG_CPU */
 525
 526 /*
 527  * Called on each cpu to initialize the per_cpu UV data area.
 528  * FIXME: hotplug not supported yet
 529  */
 530 void __cpuinit uv_cpu_init(void)
 531 {
 532         /* CPU 0 initilization will be done via uv_system_init. */
 533         if (!uv_blade_info)
 534                 return;
 535
 536         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 537
 538         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 539                 set_x2apic_extra_bits(uv_hub_info->pnode);
 540 }
 541
 542
 543 void __init uv_system_init(void)
 544 {
 545         union uvh_si_addr_map_config_u m_n_config;
 546         union uvh_node_id_u node_id;
 547         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 548         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 549         int gnode_extra, max_pnode = 0;
 550         unsigned long mmr_base, present, paddr;
 551         unsigned short pnode_mask;
 552
 553         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 554         m_val = m_n_config.s.m_skt;
 555         n_val = m_n_config.s.n_skt;
 556         mmr_base =
 557             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 558             ~UV_MMR_ENABLE;
 559         pnode_mask = (1 << n_val) - 1;
 560         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 561         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 562         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 563         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
 564                         n_val, m_val, gnode_upper, gnode_extra);
 565
 566         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 567
 568         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 569                 uv_possible_blades +=
 570                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 571         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 572
 573         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 574         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 575         BUG_ON(!uv_blade_info);
 576         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 577                 uv_blade_info[blade].memory_nid = -1;
 578
 579         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 580
 581         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 582         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 583         BUG_ON(!uv_node_to_blade);
 584         memset(uv_node_to_blade, 255, bytes);
 585
 586         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 587         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 588         BUG_ON(!uv_cpu_to_blade);
 589         memset(uv_cpu_to_blade, 255, bytes);
 590
 591         blade = 0;
 592         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 593                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 594                 for (j = 0; j < 64; j++) {
 595                         if (!test_bit(j, &present))
 596                                 continue;
 597                         pnode = (i * 64 + j);
 598                         uv_blade_info[blade].pnode = pnode;
 599                         uv_blade_info[blade].nr_possible_cpus = 0;
 600                         uv_blade_info[blade].nr_online_cpus = 0;
 601                         max_pnode = max(pnode, max_pnode);
 602                         blade++;
 603                 }
 604         }
 605
 606         uv_bios_init();
 607         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 608                             &sn_coherency_id, &sn_region_size);
 609         uv_rtc_init();
 610
 611         for_each_present_cpu(cpu) {
 612                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 613
 614                 nid = cpu_to_node(cpu);
 615                 pnode = uv_apicid_to_pnode(apicid);
 616                 blade = boot_pnode_to_blade(pnode);
 617                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 618                 uv_blade_info[blade].nr_possible_cpus++;
 619
 620                 /* Any node on the blade, else will contain -1. */
 621                 uv_blade_info[blade].memory_nid = nid;
 622
 623                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 624                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 625                 uv_cpu_hub_info(cpu)->m_val = m_val;
 626                 uv_cpu_hub_info(cpu)->n_val = n_val;
 627                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 628                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 629                 uv_cpu_hub_info(cpu)->pnode = pnode;
 630                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 631                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 632                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 633                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 634                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 635                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 636                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 637                 uv_node_to_blade[nid] = blade;
 638                 uv_cpu_to_blade[cpu] = blade;
 639         }
 640
 641         /* Add blade/pnode info for nodes without cpus */
 642         for_each_online_node(nid) {
 643                 if (uv_node_to_blade[nid] >= 0)
 644                         continue;
 645                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 646                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 647                 pnode = (paddr >> m_val) & pnode_mask;
 648                 blade = boot_pnode_to_blade(pnode);
 649                 uv_node_to_blade[nid] = blade;
 650         }
 651
 652         map_gru_high(max_pnode);
 653         map_mmr_high(max_pnode);
 654         map_mmioh_high(max_pnode);
 655
 656         uv_cpu_init();
 657         uv_scir_register_cpu_notifier();
 658         proc_mkdir("sgi_uv", NULL);
 659 }