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init from v2.6.32.60
[mach-moxart.git] / arch / x86 / kvm / lapic.c
blob8dfeaaa7079569badd5165989347154d9180c0d2
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
22 #include <linux/mm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
26 #include <linux/io.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
30 #include <asm/msr.h>
31 #include <asm/page.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include <asm/apicdef.h>
36 #include "kvm_cache_regs.h"
37 #include "irq.h"
38 #include "trace.h"
39 #include "x86.h"
40
41 #ifndef CONFIG_X86_64
42 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
43 #else
44 #define mod_64(x, y) ((x) % (y))
45 #endif
46
47 #define PRId64 "d"
48 #define PRIx64 "llx"
49 #define PRIu64 "u"
50 #define PRIo64 "o"
51
52 #define APIC_BUS_CYCLE_NS 1
53
54 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
55 #define apic_debug(fmt, arg...)
56
57 #define APIC_LVT_NUM 6
58 /* 14 is the version for Xeon and Pentium 8.4.8*/
59 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
60 #define LAPIC_MMIO_LENGTH (1 << 12)
61 /* followed define is not in apicdef.h */
62 #define APIC_SHORT_MASK 0xc0000
63 #define APIC_DEST_NOSHORT 0x0
64 #define APIC_DEST_MASK 0x800
65 #define MAX_APIC_VECTOR 256
66
67 #define VEC_POS(v) ((v) & (32 - 1))
68 #define REG_POS(v) (((v) >> 5) << 4)
69
70 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
71 {
72 return *((u32 *) (apic->regs + reg_off));
73 }
74
75 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
76 {
77 *((u32 *) (apic->regs + reg_off)) = val;
78 }
79
80 static inline int apic_test_and_set_vector(int vec, void *bitmap)
81 {
82 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
83 }
84
85 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
86 {
87 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
88 }
89
90 static inline void apic_set_vector(int vec, void *bitmap)
91 {
92 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
93 }
94
95 static inline void apic_clear_vector(int vec, void *bitmap)
96 {
97 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98 }
99
100 static inline int apic_hw_enabled(struct kvm_lapic *apic)
101 {
102 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
103 }
104
105 static inline int apic_sw_enabled(struct kvm_lapic *apic)
106 {
107 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
108 }
109
110 static inline int apic_enabled(struct kvm_lapic *apic)
111 {
112 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
113 }
114
115 #define LVT_MASK \
116 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
117
118 #define LINT_MASK \
119 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
120 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
121
122 static inline int kvm_apic_id(struct kvm_lapic *apic)
123 {
124 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
125 }
126
127 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
128 {
129 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
130 }
131
132 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
133 {
134 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
135 }
136
137 static inline int apic_lvtt_period(struct kvm_lapic *apic)
138 {
139 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
140 }
141
142 static inline int apic_lvt_nmi_mode(u32 lvt_val)
143 {
144 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
145 }
146
147 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
148 {
149 struct kvm_lapic *apic = vcpu->arch.apic;
150 struct kvm_cpuid_entry2 *feat;
151 u32 v = APIC_VERSION;
152
153 if (!irqchip_in_kernel(vcpu->kvm))
154 return;
155
156 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
157 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
158 v |= APIC_LVR_DIRECTED_EOI;
159 apic_set_reg(apic, APIC_LVR, v);
160 }
161
162 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
163 {
164 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
165 }
166
167 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
168 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
169 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
170 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
171 LINT_MASK, LINT_MASK, /* LVT0-1 */
172 LVT_MASK /* LVTERR */
173 };
174
175 static int find_highest_vector(void *bitmap)
176 {
177 u32 *word = bitmap;
178 int word_offset = MAX_APIC_VECTOR >> 5;
179
180 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
181 continue;
182
183 if (likely(!word_offset && !word[0]))
184 return -1;
185 else
186 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
187 }
188
189 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
190 {
191 apic->irr_pending = true;
192 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
193 }
194
195 static inline int apic_search_irr(struct kvm_lapic *apic)
196 {
197 return find_highest_vector(apic->regs + APIC_IRR);
198 }
199
200 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
201 {
202 int result;
203
204 if (!apic->irr_pending)
205 return -1;
206
207 result = apic_search_irr(apic);
208 ASSERT(result == -1 || result >= 16);
209
210 return result;
211 }
212
213 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
214 {
215 apic->irr_pending = false;
216 apic_clear_vector(vec, apic->regs + APIC_IRR);
217 if (apic_search_irr(apic) != -1)
218 apic->irr_pending = true;
219 }
220
221 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
222 {
223 struct kvm_lapic *apic = vcpu->arch.apic;
224 int highest_irr;
225
226 /* This may race with setting of irr in __apic_accept_irq() and
227 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
228 * will cause vmexit immediately and the value will be recalculated
229 * on the next vmentry.
230 */
231 if (!apic)
232 return 0;
233 highest_irr = apic_find_highest_irr(apic);
234
235 return highest_irr;
236 }
237
238 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
239 int vector, int level, int trig_mode);
240
241 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
242 {
243 struct kvm_lapic *apic = vcpu->arch.apic;
244
245 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
246 irq->level, irq->trig_mode);
247 }
248
249 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
250 {
251 int result;
252
253 result = find_highest_vector(apic->regs + APIC_ISR);
254 ASSERT(result == -1 || result >= 16);
255
256 return result;
257 }
258
259 static void apic_update_ppr(struct kvm_lapic *apic)
260 {
261 u32 tpr, isrv, ppr;
262 int isr;
263
264 tpr = apic_get_reg(apic, APIC_TASKPRI);
265 isr = apic_find_highest_isr(apic);
266 isrv = (isr != -1) ? isr : 0;
267
268 if ((tpr & 0xf0) >= (isrv & 0xf0))
269 ppr = tpr & 0xff;
270 else
271 ppr = isrv & 0xf0;
272
273 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
274 apic, ppr, isr, isrv);
275
276 apic_set_reg(apic, APIC_PROCPRI, ppr);
277 }
278
279 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
280 {
281 apic_set_reg(apic, APIC_TASKPRI, tpr);
282 apic_update_ppr(apic);
283 }
284
285 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
286 {
287 return dest == 0xff || kvm_apic_id(apic) == dest;
288 }
289
290 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
291 {
292 int result = 0;
293 u32 logical_id;
294
295 if (apic_x2apic_mode(apic)) {
296 logical_id = apic_get_reg(apic, APIC_LDR);
297 return logical_id & mda;
298 }
299
300 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
301
302 switch (apic_get_reg(apic, APIC_DFR)) {
303 case APIC_DFR_FLAT:
304 if (logical_id & mda)
305 result = 1;
306 break;
307 case APIC_DFR_CLUSTER:
308 if (((logical_id >> 4) == (mda >> 0x4))
309 && (logical_id & mda & 0xf))
310 result = 1;
311 break;
312 default:
313 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
314 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
315 break;
316 }
317
318 return result;
319 }
320
321 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
322 int short_hand, int dest, int dest_mode)
323 {
324 int result = 0;
325 struct kvm_lapic *target = vcpu->arch.apic;
326
327 apic_debug("target %p, source %p, dest 0x%x, "
328 "dest_mode 0x%x, short_hand 0x%x\n",
329 target, source, dest, dest_mode, short_hand);
330
331 ASSERT(!target);
332 switch (short_hand) {
333 case APIC_DEST_NOSHORT:
334 if (dest_mode == 0)
335 /* Physical mode. */
336 result = kvm_apic_match_physical_addr(target, dest);
337 else
338 /* Logical mode. */
339 result = kvm_apic_match_logical_addr(target, dest);
340 break;
341 case APIC_DEST_SELF:
342 result = (target == source);
343 break;
344 case APIC_DEST_ALLINC:
345 result = 1;
346 break;
347 case APIC_DEST_ALLBUT:
348 result = (target != source);
349 break;
350 default:
351 printk(KERN_WARNING "Bad dest shorthand value %x\n",
352 short_hand);
353 break;
354 }
355
356 return result;
357 }
358
359 /*
360 * Add a pending IRQ into lapic.
361 * Return 1 if successfully added and 0 if discarded.
362 */
363 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
364 int vector, int level, int trig_mode)
365 {
366 int result = 0;
367 struct kvm_vcpu *vcpu = apic->vcpu;
368
369 switch (delivery_mode) {
370 case APIC_DM_LOWEST:
371 vcpu->arch.apic_arb_prio++;
372 case APIC_DM_FIXED:
373 /* FIXME add logic for vcpu on reset */
374 if (unlikely(!apic_enabled(apic)))
375 break;
376
377 if (trig_mode) {
378 apic_debug("level trig mode for vector %d", vector);
379 apic_set_vector(vector, apic->regs + APIC_TMR);
380 } else
381 apic_clear_vector(vector, apic->regs + APIC_TMR);
382
383 result = !apic_test_and_set_irr(vector, apic);
384 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
385 trig_mode, vector, !result);
386 if (!result) {
387 if (trig_mode)
388 apic_debug("level trig mode repeatedly for "
389 "vector %d", vector);
390 break;
391 }
392
393 kvm_vcpu_kick(vcpu);
394 break;
395
396 case APIC_DM_REMRD:
397 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
398 break;
399
400 case APIC_DM_SMI:
401 printk(KERN_DEBUG "Ignoring guest SMI\n");
402 break;
403
404 case APIC_DM_NMI:
405 result = 1;
406 kvm_inject_nmi(vcpu);
407 kvm_vcpu_kick(vcpu);
408 break;
409
410 case APIC_DM_INIT:
411 if (level) {
412 result = 1;
413 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
414 printk(KERN_DEBUG
415 "INIT on a runnable vcpu %d\n",
416 vcpu->vcpu_id);
417 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
418 kvm_vcpu_kick(vcpu);
419 } else {
420 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
421 vcpu->vcpu_id);
422 }
423 break;
424
425 case APIC_DM_STARTUP:
426 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
427 vcpu->vcpu_id, vector);
428 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
429 result = 1;
430 vcpu->arch.sipi_vector = vector;
431 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
432 kvm_vcpu_kick(vcpu);
433 }
434 break;
435
436 case APIC_DM_EXTINT:
437 /*
438 * Should only be called by kvm_apic_local_deliver() with LVT0,
439 * before NMI watchdog was enabled. Already handled by
440 * kvm_apic_accept_pic_intr().
441 */
442 break;
443
444 default:
445 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
446 delivery_mode);
447 break;
448 }
449 return result;
450 }
451
452 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
453 {
454 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
455 }
456
457 static void apic_set_eoi(struct kvm_lapic *apic)
458 {
459 int vector = apic_find_highest_isr(apic);
460 int trigger_mode;
461 /*
462 * Not every write EOI will has corresponding ISR,
463 * one example is when Kernel check timer on setup_IO_APIC
464 */
465 if (vector == -1)
466 return;
467
468 apic_clear_vector(vector, apic->regs + APIC_ISR);
469 apic_update_ppr(apic);
470
471 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
472 trigger_mode = IOAPIC_LEVEL_TRIG;
473 else
474 trigger_mode = IOAPIC_EDGE_TRIG;
475 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)) {
476 mutex_lock(&apic->vcpu->kvm->irq_lock);
477 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
478 mutex_unlock(&apic->vcpu->kvm->irq_lock);
479 }
480 }
481
482 static void apic_send_ipi(struct kvm_lapic *apic)
483 {
484 u32 icr_low = apic_get_reg(apic, APIC_ICR);
485 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
486 struct kvm_lapic_irq irq;
487
488 irq.vector = icr_low & APIC_VECTOR_MASK;
489 irq.delivery_mode = icr_low & APIC_MODE_MASK;
490 irq.dest_mode = icr_low & APIC_DEST_MASK;
491 irq.level = icr_low & APIC_INT_ASSERT;
492 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
493 irq.shorthand = icr_low & APIC_SHORT_MASK;
494 if (apic_x2apic_mode(apic))
495 irq.dest_id = icr_high;
496 else
497 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
498
499 trace_kvm_apic_ipi(icr_low, irq.dest_id);
500
501 apic_debug("icr_high 0x%x, icr_low 0x%x, "
502 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
503 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
504 icr_high, icr_low, irq.shorthand, irq.dest_id,
505 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
506 irq.vector);
507
508 mutex_lock(&apic->vcpu->kvm->irq_lock);
509 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
510 mutex_unlock(&apic->vcpu->kvm->irq_lock);
511 }
512
513 static u32 apic_get_tmcct(struct kvm_lapic *apic)
514 {
515 ktime_t remaining;
516 s64 ns;
517 u32 tmcct;
518
519 ASSERT(apic != NULL);
520
521 /* if initial count is 0, current count should also be 0 */
522 if (apic_get_reg(apic, APIC_TMICT) == 0)
523 return 0;
524
525 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
526 if (ktime_to_ns(remaining) < 0)
527 remaining = ktime_set(0, 0);
528
529 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
530 tmcct = div64_u64(ns,
531 (APIC_BUS_CYCLE_NS * apic->divide_count));
532
533 return tmcct;
534 }
535
536 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
537 {
538 struct kvm_vcpu *vcpu = apic->vcpu;
539 struct kvm_run *run = vcpu->run;
540
541 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
542 run->tpr_access.rip = kvm_rip_read(vcpu);
543 run->tpr_access.is_write = write;
544 }
545
546 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
547 {
548 if (apic->vcpu->arch.tpr_access_reporting)
549 __report_tpr_access(apic, write);
550 }
551
552 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
553 {
554 u32 val = 0;
555
556 if (offset >= LAPIC_MMIO_LENGTH)
557 return 0;
558
559 switch (offset) {
560 case APIC_ID:
561 if (apic_x2apic_mode(apic))
562 val = kvm_apic_id(apic);
563 else
564 val = kvm_apic_id(apic) << 24;
565 break;
566 case APIC_ARBPRI:
567 printk(KERN_WARNING "Access APIC ARBPRI register "
568 "which is for P6\n");
569 break;
570
571 case APIC_TMCCT: /* Timer CCR */
572 val = apic_get_tmcct(apic);
573 break;
574
575 case APIC_TASKPRI:
576 report_tpr_access(apic, false);
577 /* fall thru */
578 default:
579 apic_update_ppr(apic);
580 val = apic_get_reg(apic, offset);
581 break;
582 }
583
584 return val;
585 }
586
587 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
588 {
589 return container_of(dev, struct kvm_lapic, dev);
590 }
591
592 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
593 void *data)
594 {
595 unsigned char alignment = offset & 0xf;
596 u32 result;
597 /* this bitmask has a bit cleared for each reserver register */
598 static const u64 rmask = 0x43ff01ffffffe70cULL;
599
600 if ((alignment + len) > 4) {
601 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
602 offset, len);
603 return 1;
604 }
605
606 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
607 apic_debug("KVM_APIC_READ: read reserved register %x\n",
608 offset);
609 return 1;
610 }
611
612 result = __apic_read(apic, offset & ~0xf);
613
614 trace_kvm_apic_read(offset, result);
615
616 switch (len) {
617 case 1:
618 case 2:
619 case 4:
620 memcpy(data, (char *)&result + alignment, len);
621 break;
622 default:
623 printk(KERN_ERR "Local APIC read with len = %x, "
624 "should be 1,2, or 4 instead\n", len);
625 break;
626 }
627 return 0;
628 }
629
630 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
631 {
632 return apic_hw_enabled(apic) &&
633 addr >= apic->base_address &&
634 addr < apic->base_address + LAPIC_MMIO_LENGTH;
635 }
636
637 static int apic_mmio_read(struct kvm_io_device *this,
638 gpa_t address, int len, void *data)
639 {
640 struct kvm_lapic *apic = to_lapic(this);
641 u32 offset = address - apic->base_address;
642
643 if (!apic_mmio_in_range(apic, address))
644 return -EOPNOTSUPP;
645
646 apic_reg_read(apic, offset, len, data);
647
648 return 0;
649 }
650
651 static void update_divide_count(struct kvm_lapic *apic)
652 {
653 u32 tmp1, tmp2, tdcr;
654
655 tdcr = apic_get_reg(apic, APIC_TDCR);
656 tmp1 = tdcr & 0xf;
657 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
658 apic->divide_count = 0x1 << (tmp2 & 0x7);
659
660 apic_debug("timer divide count is 0x%x\n",
661 apic->divide_count);
662 }
663
664 static void start_apic_timer(struct kvm_lapic *apic)
665 {
666 ktime_t now = apic->lapic_timer.timer.base->get_time();
667
668 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
669 APIC_BUS_CYCLE_NS * apic->divide_count;
670 atomic_set(&apic->lapic_timer.pending, 0);
671
672 if (!apic->lapic_timer.period)
673 return;
674 /*
675 * Do not allow the guest to program periodic timers with small
676 * interval, since the hrtimers are not throttled by the host
677 * scheduler.
678 */
679 if (apic_lvtt_period(apic)) {
680 if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
681 apic->lapic_timer.period = NSEC_PER_MSEC/2;
682 }
683
684 hrtimer_start(&apic->lapic_timer.timer,
685 ktime_add_ns(now, apic->lapic_timer.period),
686 HRTIMER_MODE_ABS);
687
688 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
689 PRIx64 ", "
690 "timer initial count 0x%x, period %lldns, "
691 "expire @ 0x%016" PRIx64 ".\n", __func__,
692 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
693 apic_get_reg(apic, APIC_TMICT),
694 apic->lapic_timer.period,
695 ktime_to_ns(ktime_add_ns(now,
696 apic->lapic_timer.period)));
697 }
698
699 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
700 {
701 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
702
703 if (apic_lvt_nmi_mode(lvt0_val)) {
704 if (!nmi_wd_enabled) {
705 apic_debug("Receive NMI setting on APIC_LVT0 "
706 "for cpu %d\n", apic->vcpu->vcpu_id);
707 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
708 }
709 } else if (nmi_wd_enabled)
710 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
711 }
712
713 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
714 {
715 int ret = 0;
716
717 trace_kvm_apic_write(reg, val);
718
719 switch (reg) {
720 case APIC_ID: /* Local APIC ID */
721 if (!apic_x2apic_mode(apic))
722 apic_set_reg(apic, APIC_ID, val);
723 else
724 ret = 1;
725 break;
726
727 case APIC_TASKPRI:
728 report_tpr_access(apic, true);
729 apic_set_tpr(apic, val & 0xff);
730 break;
731
732 case APIC_EOI:
733 apic_set_eoi(apic);
734 break;
735
736 case APIC_LDR:
737 if (!apic_x2apic_mode(apic))
738 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
739 else
740 ret = 1;
741 break;
742
743 case APIC_DFR:
744 if (!apic_x2apic_mode(apic))
745 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
746 else
747 ret = 1;
748 break;
749
750 case APIC_SPIV: {
751 u32 mask = 0x3ff;
752 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
753 mask |= APIC_SPIV_DIRECTED_EOI;
754 apic_set_reg(apic, APIC_SPIV, val & mask);
755 if (!(val & APIC_SPIV_APIC_ENABLED)) {
756 int i;
757 u32 lvt_val;
758
759 for (i = 0; i < APIC_LVT_NUM; i++) {
760 lvt_val = apic_get_reg(apic,
761 APIC_LVTT + 0x10 * i);
762 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
763 lvt_val | APIC_LVT_MASKED);
764 }
765 atomic_set(&apic->lapic_timer.pending, 0);
766
767 }
768 break;
769 }
770 case APIC_ICR:
771 /* No delay here, so we always clear the pending bit */
772 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
773 apic_send_ipi(apic);
774 break;
775
776 case APIC_ICR2:
777 if (!apic_x2apic_mode(apic))
778 val &= 0xff000000;
779 apic_set_reg(apic, APIC_ICR2, val);
780 break;
781
782 case APIC_LVT0:
783 apic_manage_nmi_watchdog(apic, val);
784 case APIC_LVTT:
785 case APIC_LVTTHMR:
786 case APIC_LVTPC:
787 case APIC_LVT1:
788 case APIC_LVTERR:
789 /* TODO: Check vector */
790 if (!apic_sw_enabled(apic))
791 val |= APIC_LVT_MASKED;
792
793 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
794 apic_set_reg(apic, reg, val);
795
796 break;
797
798 case APIC_TMICT:
799 hrtimer_cancel(&apic->lapic_timer.timer);
800 apic_set_reg(apic, APIC_TMICT, val);
801 start_apic_timer(apic);
802 break;
803
804 case APIC_TDCR:
805 if (val & 4)
806 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
807 apic_set_reg(apic, APIC_TDCR, val);
808 update_divide_count(apic);
809 break;
810
811 case APIC_ESR:
812 if (apic_x2apic_mode(apic) && val != 0) {
813 printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
814 ret = 1;
815 }
816 break;
817
818 case APIC_SELF_IPI:
819 if (apic_x2apic_mode(apic)) {
820 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
821 } else
822 ret = 1;
823 break;
824 default:
825 ret = 1;
826 break;
827 }
828 if (ret)
829 apic_debug("Local APIC Write to read-only register %x\n", reg);
830 return ret;
831 }
832
833 static int apic_mmio_write(struct kvm_io_device *this,
834 gpa_t address, int len, const void *data)
835 {
836 struct kvm_lapic *apic = to_lapic(this);
837 unsigned int offset = address - apic->base_address;
838 u32 val;
839
840 if (!apic_mmio_in_range(apic, address))
841 return -EOPNOTSUPP;
842
843 /*
844 * APIC register must be aligned on 128-bits boundary.
845 * 32/64/128 bits registers must be accessed thru 32 bits.
846 * Refer SDM 8.4.1
847 */
848 if (len != 4 || (offset & 0xf)) {
849 /* Don't shout loud, $infamous_os would cause only noise. */
850 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
851 return 0;
852 }
853
854 val = *(u32*)data;
855
856 /* too common printing */
857 if (offset != APIC_EOI)
858 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
859 "0x%x\n", __func__, offset, len, val);
860
861 apic_reg_write(apic, offset & 0xff0, val);
862
863 return 0;
864 }
865
866 void kvm_free_lapic(struct kvm_vcpu *vcpu)
867 {
868 if (!vcpu->arch.apic)
869 return;
870
871 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
872
873 if (vcpu->arch.apic->regs_page)
874 __free_page(vcpu->arch.apic->regs_page);
875
876 kfree(vcpu->arch.apic);
877 }
878
879 /*
880 *----------------------------------------------------------------------
881 * LAPIC interface
882 *----------------------------------------------------------------------
883 */
884
885 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
886 {
887 struct kvm_lapic *apic = vcpu->arch.apic;
888
889 if (!apic)
890 return;
891 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
892 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
893 }
894
895 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
896 {
897 struct kvm_lapic *apic = vcpu->arch.apic;
898 u64 tpr;
899
900 if (!apic)
901 return 0;
902 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
903
904 return (tpr & 0xf0) >> 4;
905 }
906
907 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
908 {
909 struct kvm_lapic *apic = vcpu->arch.apic;
910
911 if (!apic) {
912 value |= MSR_IA32_APICBASE_BSP;
913 vcpu->arch.apic_base = value;
914 return;
915 }
916
917 if (!kvm_vcpu_is_bsp(apic->vcpu))
918 value &= ~MSR_IA32_APICBASE_BSP;
919
920 vcpu->arch.apic_base = value;
921 if (apic_x2apic_mode(apic)) {
922 u32 id = kvm_apic_id(apic);
923 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
924 apic_set_reg(apic, APIC_LDR, ldr);
925 }
926 apic->base_address = apic->vcpu->arch.apic_base &
927 MSR_IA32_APICBASE_BASE;
928
929 /* with FSB delivery interrupt, we can restart APIC functionality */
930 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
931 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
932
933 }
934
935 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
936 {
937 struct kvm_lapic *apic;
938 int i;
939
940 apic_debug("%s\n", __func__);
941
942 ASSERT(vcpu);
943 apic = vcpu->arch.apic;
944 ASSERT(apic != NULL);
945
946 /* Stop the timer in case it's a reset to an active apic */
947 hrtimer_cancel(&apic->lapic_timer.timer);
948
949 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
950 kvm_apic_set_version(apic->vcpu);
951
952 for (i = 0; i < APIC_LVT_NUM; i++)
953 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
954 apic_set_reg(apic, APIC_LVT0,
955 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
956
957 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
958 apic_set_reg(apic, APIC_SPIV, 0xff);
959 apic_set_reg(apic, APIC_TASKPRI, 0);
960 apic_set_reg(apic, APIC_LDR, 0);
961 apic_set_reg(apic, APIC_ESR, 0);
962 apic_set_reg(apic, APIC_ICR, 0);
963 apic_set_reg(apic, APIC_ICR2, 0);
964 apic_set_reg(apic, APIC_TDCR, 0);
965 apic_set_reg(apic, APIC_TMICT, 0);
966 for (i = 0; i < 8; i++) {
967 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
968 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
969 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
970 }
971 apic->irr_pending = false;
972 update_divide_count(apic);
973 atomic_set(&apic->lapic_timer.pending, 0);
974 if (kvm_vcpu_is_bsp(vcpu))
975 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
976 apic_update_ppr(apic);
977
978 vcpu->arch.apic_arb_prio = 0;
979
980 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
981 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
982 vcpu, kvm_apic_id(apic),
983 vcpu->arch.apic_base, apic->base_address);
984 }
985
986 bool kvm_apic_present(struct kvm_vcpu *vcpu)
987 {
988 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
989 }
990
991 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
992 {
993 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
994 }
995
996 /*
997 *----------------------------------------------------------------------
998 * timer interface
999 *----------------------------------------------------------------------
1000 */
1001
1002 static bool lapic_is_periodic(struct kvm_timer *ktimer)
1003 {
1004 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1005 lapic_timer);
1006 return apic_lvtt_period(apic);
1007 }
1008
1009 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1010 {
1011 struct kvm_lapic *lapic = vcpu->arch.apic;
1012
1013 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1014 return atomic_read(&lapic->lapic_timer.pending);
1015
1016 return 0;
1017 }
1018
1019 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1020 {
1021 u32 reg = apic_get_reg(apic, lvt_type);
1022 int vector, mode, trig_mode;
1023
1024 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1025 vector = reg & APIC_VECTOR_MASK;
1026 mode = reg & APIC_MODE_MASK;
1027 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1028 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1029 }
1030 return 0;
1031 }
1032
1033 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1034 {
1035 struct kvm_lapic *apic = vcpu->arch.apic;
1036
1037 if (apic)
1038 kvm_apic_local_deliver(apic, APIC_LVT0);
1039 }
1040
1041 static struct kvm_timer_ops lapic_timer_ops = {
1042 .is_periodic = lapic_is_periodic,
1043 };
1044
1045 static const struct kvm_io_device_ops apic_mmio_ops = {
1046 .read = apic_mmio_read,
1047 .write = apic_mmio_write,
1048 };
1049
1050 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1051 {
1052 struct kvm_lapic *apic;
1053
1054 ASSERT(vcpu != NULL);
1055 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1056
1057 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1058 if (!apic)
1059 goto nomem;
1060
1061 vcpu->arch.apic = apic;
1062
1063 apic->regs_page = alloc_page(GFP_KERNEL);
1064 if (apic->regs_page == NULL) {
1065 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1066 vcpu->vcpu_id);
1067 goto nomem_free_apic;
1068 }
1069 apic->regs = page_address(apic->regs_page);
1070 memset(apic->regs, 0, PAGE_SIZE);
1071 apic->vcpu = vcpu;
1072
1073 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1074 HRTIMER_MODE_ABS);
1075 apic->lapic_timer.timer.function = kvm_timer_fn;
1076 apic->lapic_timer.t_ops = &lapic_timer_ops;
1077 apic->lapic_timer.kvm = vcpu->kvm;
1078 apic->lapic_timer.vcpu = vcpu;
1079
1080 apic->base_address = APIC_DEFAULT_PHYS_BASE;
1081 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1082
1083 kvm_lapic_reset(vcpu);
1084 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1085
1086 return 0;
1087 nomem_free_apic:
1088 kfree(apic);
1089 nomem:
1090 return -ENOMEM;
1091 }
1092
1093 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1094 {
1095 struct kvm_lapic *apic = vcpu->arch.apic;
1096 int highest_irr;
1097
1098 if (!apic || !apic_enabled(apic))
1099 return -1;
1100
1101 apic_update_ppr(apic);
1102 highest_irr = apic_find_highest_irr(apic);
1103 if ((highest_irr == -1) ||
1104 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1105 return -1;
1106 return highest_irr;
1107 }
1108
1109 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1110 {
1111 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1112 int r = 0;
1113
1114 if (kvm_vcpu_is_bsp(vcpu)) {
1115 if (!apic_hw_enabled(vcpu->arch.apic))
1116 r = 1;
1117 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1118 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1119 r = 1;
1120 }
1121 return r;
1122 }
1123
1124 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1125 {
1126 struct kvm_lapic *apic = vcpu->arch.apic;
1127
1128 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1129 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1130 atomic_dec(&apic->lapic_timer.pending);
1131 }
1132 }
1133
1134 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1135 {
1136 int vector = kvm_apic_has_interrupt(vcpu);
1137 struct kvm_lapic *apic = vcpu->arch.apic;
1138
1139 if (vector == -1)
1140 return -1;
1141
1142 apic_set_vector(vector, apic->regs + APIC_ISR);
1143 apic_update_ppr(apic);
1144 apic_clear_irr(vector, apic);
1145 return vector;
1146 }
1147
1148 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1149 {
1150 struct kvm_lapic *apic = vcpu->arch.apic;
1151
1152 apic->base_address = vcpu->arch.apic_base &
1153 MSR_IA32_APICBASE_BASE;
1154 kvm_apic_set_version(vcpu);
1155
1156 apic_update_ppr(apic);
1157 hrtimer_cancel(&apic->lapic_timer.timer);
1158 update_divide_count(apic);
1159 start_apic_timer(apic);
1160 apic->irr_pending = true;
1161 }
1162
1163 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1164 {
1165 struct kvm_lapic *apic = vcpu->arch.apic;
1166 struct hrtimer *timer;
1167
1168 if (!apic)
1169 return;
1170
1171 timer = &apic->lapic_timer.timer;
1172 if (hrtimer_cancel(timer))
1173 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1174 }
1175
1176 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1177 {
1178 u32 data;
1179 void *vapic;
1180
1181 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1182 return;
1183
1184 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1185 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1186 kunmap_atomic(vapic, KM_USER0);
1187
1188 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1189 }
1190
1191 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1192 {
1193 u32 data, tpr;
1194 int max_irr, max_isr;
1195 struct kvm_lapic *apic;
1196 void *vapic;
1197
1198 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1199 return;
1200
1201 apic = vcpu->arch.apic;
1202 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1203 max_irr = apic_find_highest_irr(apic);
1204 if (max_irr < 0)
1205 max_irr = 0;
1206 max_isr = apic_find_highest_isr(apic);
1207 if (max_isr < 0)
1208 max_isr = 0;
1209 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1210
1211 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1212 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1213 kunmap_atomic(vapic, KM_USER0);
1214 }
1215
1216 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1217 {
1218 if (!irqchip_in_kernel(vcpu->kvm))
1219 return;
1220
1221 vcpu->arch.apic->vapic_addr = vapic_addr;
1222 }
1223
1224 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1225 {
1226 struct kvm_lapic *apic = vcpu->arch.apic;
1227 u32 reg = (msr - APIC_BASE_MSR) << 4;
1228
1229 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1230 return 1;
1231
1232 /* if this is ICR write vector before command */
1233 if (msr == 0x830)
1234 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1235 return apic_reg_write(apic, reg, (u32)data);
1236 }
1237
1238 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1239 {
1240 struct kvm_lapic *apic = vcpu->arch.apic;
1241 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1242
1243 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1244 return 1;
1245
1246 if (apic_reg_read(apic, reg, 4, &low))
1247 return 1;
1248 if (msr == 0x830)
1249 apic_reg_read(apic, APIC_ICR2, 4, &high);
1250
1251 *data = (((u64)high) << 32) | low;
1252
1253 return 0;
1254 }
Linux MOXA ART SoC ARM port