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init from v2.6.32.60
[mach-moxart.git] / drivers / char / agp / intel-agp.c
blobb8e02190bef4302f2fc3d490b7cdb1bc54d5e2e9
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include <asm/smp.h>
12 #include "agp.h"
13
14 /*
15 * If we have Intel graphics, we're not going to have anything other than
16 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
17 * on the Intel IOMMU support (CONFIG_DMAR).
18 * Only newer chipsets need to bother with this, of course.
19 */
20 #ifdef CONFIG_DMAR
21 #define USE_PCI_DMA_API 1
22 #endif
23
24 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
25 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
26 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
27 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
28 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
29 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
30 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
31 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
32 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
33 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
34 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
35 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
36 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
37 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
38 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
39 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
40 #define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010
41 #define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011
42 #define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000
43 #define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001
44 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
45 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
46 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
47 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
48 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
49 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
50 #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
51 #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
52 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
53 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
54 #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
55 #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
56 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
57 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
58 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
59 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
60 #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
61 #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
62 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040
63 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042
64 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044
65 #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB 0x0062
66 #define PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB 0x006a
67 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046
68
69 /* cover 915 and 945 variants */
70 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
71 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
72 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
73 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
74 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
75 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
76
77 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
78 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
79 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
81 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
83
84 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
85 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
87 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
88 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
89
90 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
91 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
92
93 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
96 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
97 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
99 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
100 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
101 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB || \
102 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB)
103
104 extern int agp_memory_reserved;
105
106
107 /* Intel 815 register */
108 #define INTEL_815_APCONT 0x51
109 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
110
111 /* Intel i820 registers */
112 #define INTEL_I820_RDCR 0x51
113 #define INTEL_I820_ERRSTS 0xc8
114
115 /* Intel i840 registers */
116 #define INTEL_I840_MCHCFG 0x50
117 #define INTEL_I840_ERRSTS 0xc8
118
119 /* Intel i850 registers */
120 #define INTEL_I850_MCHCFG 0x50
121 #define INTEL_I850_ERRSTS 0xc8
122
123 /* intel 915G registers */
124 #define I915_GMADDR 0x18
125 #define I915_MMADDR 0x10
126 #define I915_PTEADDR 0x1C
127 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
128 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
129 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
130 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
131 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
132 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
133 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
134 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
135
136 #define I915_IFPADDR 0x60
137
138 /* Intel 965G registers */
139 #define I965_MSAC 0x62
140 #define I965_IFPADDR 0x70
141
142 /* Intel 7505 registers */
143 #define INTEL_I7505_APSIZE 0x74
144 #define INTEL_I7505_NCAPID 0x60
145 #define INTEL_I7505_NISTAT 0x6c
146 #define INTEL_I7505_ATTBASE 0x78
147 #define INTEL_I7505_ERRSTS 0x42
148 #define INTEL_I7505_AGPCTRL 0x70
149 #define INTEL_I7505_MCHCFG 0x50
150
151 static const struct aper_size_info_fixed intel_i810_sizes[] =
152 {
153 {64, 16384, 4},
154 /* The 32M mode still requires a 64k gatt */
155 {32, 8192, 4}
156 };
157
158 #define AGP_DCACHE_MEMORY 1
159 #define AGP_PHYS_MEMORY 2
160 #define INTEL_AGP_CACHED_MEMORY 3
161
162 static struct gatt_mask intel_i810_masks[] =
163 {
164 {.mask = I810_PTE_VALID, .type = 0},
165 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
166 {.mask = I810_PTE_VALID, .type = 0},
167 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
168 .type = INTEL_AGP_CACHED_MEMORY}
169 };
170
171 static struct _intel_private {
172 struct pci_dev *pcidev; /* device one */
173 u8 __iomem *registers;
174 u32 __iomem *gtt; /* I915G */
175 int num_dcache_entries;
176 /* gtt_entries is the number of gtt entries that are already mapped
177 * to stolen memory. Stolen memory is larger than the memory mapped
178 * through gtt_entries, as it includes some reserved space for the BIOS
179 * popup and for the GTT.
180 */
181 int gtt_entries; /* i830+ */
182 int gtt_total_size;
183 union {
184 void __iomem *i9xx_flush_page;
185 void *i8xx_flush_page;
186 };
187 struct page *i8xx_page;
188 struct resource ifp_resource;
189 int resource_valid;
190 } intel_private;
191
192 #ifdef USE_PCI_DMA_API
193 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
194 {
195 *ret = pci_map_page(intel_private.pcidev, page, 0,
196 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
197 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
198 return -EINVAL;
199 return 0;
200 }
201
202 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
203 {
204 pci_unmap_page(intel_private.pcidev, dma,
205 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
206 }
207
208 static void intel_agp_free_sglist(struct agp_memory *mem)
209 {
210 struct sg_table st;
211
212 st.sgl = mem->sg_list;
213 st.orig_nents = st.nents = mem->page_count;
214
215 sg_free_table(&st);
216
217 mem->sg_list = NULL;
218 mem->num_sg = 0;
219 }
220
221 static int intel_agp_map_memory(struct agp_memory *mem)
222 {
223 struct sg_table st;
224 struct scatterlist *sg;
225 int i;
226
227 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
228
229 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
230 return -ENOMEM;
231
232 mem->sg_list = sg = st.sgl;
233
234 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
235 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
236
237 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
238 mem->page_count, PCI_DMA_BIDIRECTIONAL);
239 if (unlikely(!mem->num_sg)) {
240 intel_agp_free_sglist(mem);
241 return -ENOMEM;
242 }
243 return 0;
244 }
245
246 static void intel_agp_unmap_memory(struct agp_memory *mem)
247 {
248 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
249
250 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
251 mem->page_count, PCI_DMA_BIDIRECTIONAL);
252 intel_agp_free_sglist(mem);
253 }
254
255 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
256 off_t pg_start, int mask_type)
257 {
258 struct scatterlist *sg;
259 int i, j;
260
261 j = pg_start;
262
263 WARN_ON(!mem->num_sg);
264
265 if (mem->num_sg == mem->page_count) {
266 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
267 writel(agp_bridge->driver->mask_memory(agp_bridge,
268 sg_dma_address(sg), mask_type),
269 intel_private.gtt+j);
270 j++;
271 }
272 } else {
273 /* sg may merge pages, but we have to seperate
274 * per-page addr for GTT */
275 unsigned int len, m;
276
277 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
278 len = sg_dma_len(sg) / PAGE_SIZE;
279 for (m = 0; m < len; m++) {
280 writel(agp_bridge->driver->mask_memory(agp_bridge,
281 sg_dma_address(sg) + m * PAGE_SIZE,
282 mask_type),
283 intel_private.gtt+j);
284 j++;
285 }
286 }
287 }
288 readl(intel_private.gtt+j-1);
289 }
290
291 #else
292
293 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
294 off_t pg_start, int mask_type)
295 {
296 int i, j;
297
298 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
299 writel(agp_bridge->driver->mask_memory(agp_bridge,
300 page_to_phys(mem->pages[i]), mask_type),
301 intel_private.gtt+j);
302 }
303
304 readl(intel_private.gtt+j-1);
305 }
306
307 #endif
308
309 static int intel_i810_fetch_size(void)
310 {
311 u32 smram_miscc;
312 struct aper_size_info_fixed *values;
313
314 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
315 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
316
317 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
318 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
319 return 0;
320 }
321 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
322 agp_bridge->previous_size =
323 agp_bridge->current_size = (void *) (values + 1);
324 agp_bridge->aperture_size_idx = 1;
325 return values[1].size;
326 } else {
327 agp_bridge->previous_size =
328 agp_bridge->current_size = (void *) (values);
329 agp_bridge->aperture_size_idx = 0;
330 return values[0].size;
331 }
332
333 return 0;
334 }
335
336 static int intel_i810_configure(void)
337 {
338 struct aper_size_info_fixed *current_size;
339 u32 temp;
340 int i;
341
342 current_size = A_SIZE_FIX(agp_bridge->current_size);
343
344 if (!intel_private.registers) {
345 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
346 temp &= 0xfff80000;
347
348 intel_private.registers = ioremap(temp, 128 * 4096);
349 if (!intel_private.registers) {
350 dev_err(&intel_private.pcidev->dev,
351 "can't remap memory\n");
352 return -ENOMEM;
353 }
354 }
355
356 if ((readl(intel_private.registers+I810_DRAM_CTL)
357 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
358 /* This will need to be dynamically assigned */
359 dev_info(&intel_private.pcidev->dev,
360 "detected 4MB dedicated video ram\n");
361 intel_private.num_dcache_entries = 1024;
362 }
363 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
364 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
365 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
366 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
367
368 if (agp_bridge->driver->needs_scratch_page) {
369 for (i = 0; i < current_size->num_entries; i++) {
370 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
371 }
372 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
373 }
374 global_cache_flush();
375 return 0;
376 }
377
378 static void intel_i810_cleanup(void)
379 {
380 writel(0, intel_private.registers+I810_PGETBL_CTL);
381 readl(intel_private.registers); /* PCI Posting. */
382 iounmap(intel_private.registers);
383 }
384
385 static void intel_i810_tlbflush(struct agp_memory *mem)
386 {
387 return;
388 }
389
390 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
391 {
392 return;
393 }
394
395 /* Exists to support ARGB cursors */
396 static struct page *i8xx_alloc_pages(void)
397 {
398 struct page *page;
399
400 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
401 if (page == NULL)
402 return NULL;
403
404 if (set_pages_uc(page, 4) < 0) {
405 set_pages_wb(page, 4);
406 __free_pages(page, 2);
407 return NULL;
408 }
409 get_page(page);
410 atomic_inc(&agp_bridge->current_memory_agp);
411 return page;
412 }
413
414 static void i8xx_destroy_pages(struct page *page)
415 {
416 if (page == NULL)
417 return;
418
419 set_pages_wb(page, 4);
420 put_page(page);
421 __free_pages(page, 2);
422 atomic_dec(&agp_bridge->current_memory_agp);
423 }
424
425 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
426 int type)
427 {
428 if (type < AGP_USER_TYPES)
429 return type;
430 else if (type == AGP_USER_CACHED_MEMORY)
431 return INTEL_AGP_CACHED_MEMORY;
432 else
433 return 0;
434 }
435
436 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
437 int type)
438 {
439 int i, j, num_entries;
440 void *temp;
441 int ret = -EINVAL;
442 int mask_type;
443
444 if (mem->page_count == 0)
445 goto out;
446
447 temp = agp_bridge->current_size;
448 num_entries = A_SIZE_FIX(temp)->num_entries;
449
450 if ((pg_start + mem->page_count) > num_entries)
451 goto out_err;
452
453
454 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
455 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
456 ret = -EBUSY;
457 goto out_err;
458 }
459 }
460
461 if (type != mem->type)
462 goto out_err;
463
464 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
465
466 switch (mask_type) {
467 case AGP_DCACHE_MEMORY:
468 if (!mem->is_flushed)
469 global_cache_flush();
470 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
471 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
472 intel_private.registers+I810_PTE_BASE+(i*4));
473 }
474 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
475 break;
476 case AGP_PHYS_MEMORY:
477 case AGP_NORMAL_MEMORY:
478 if (!mem->is_flushed)
479 global_cache_flush();
480 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
481 writel(agp_bridge->driver->mask_memory(agp_bridge,
482 page_to_phys(mem->pages[i]), mask_type),
483 intel_private.registers+I810_PTE_BASE+(j*4));
484 }
485 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
486 break;
487 default:
488 goto out_err;
489 }
490
491 agp_bridge->driver->tlb_flush(mem);
492 out:
493 ret = 0;
494 out_err:
495 mem->is_flushed = true;
496 return ret;
497 }
498
499 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
500 int type)
501 {
502 int i;
503
504 if (mem->page_count == 0)
505 return 0;
506
507 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
508 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
509 }
510 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
511
512 agp_bridge->driver->tlb_flush(mem);
513 return 0;
514 }
515
516 /*
517 * The i810/i830 requires a physical address to program its mouse
518 * pointer into hardware.
519 * However the Xserver still writes to it through the agp aperture.
520 */
521 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
522 {
523 struct agp_memory *new;
524 struct page *page;
525
526 switch (pg_count) {
527 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
528 break;
529 case 4:
530 /* kludge to get 4 physical pages for ARGB cursor */
531 page = i8xx_alloc_pages();
532 break;
533 default:
534 return NULL;
535 }
536
537 if (page == NULL)
538 return NULL;
539
540 new = agp_create_memory(pg_count);
541 if (new == NULL)
542 return NULL;
543
544 new->pages[0] = page;
545 if (pg_count == 4) {
546 /* kludge to get 4 physical pages for ARGB cursor */
547 new->pages[1] = new->pages[0] + 1;
548 new->pages[2] = new->pages[1] + 1;
549 new->pages[3] = new->pages[2] + 1;
550 }
551 new->page_count = pg_count;
552 new->num_scratch_pages = pg_count;
553 new->type = AGP_PHYS_MEMORY;
554 new->physical = page_to_phys(new->pages[0]);
555 return new;
556 }
557
558 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
559 {
560 struct agp_memory *new;
561
562 if (type == AGP_DCACHE_MEMORY) {
563 if (pg_count != intel_private.num_dcache_entries)
564 return NULL;
565
566 new = agp_create_memory(1);
567 if (new == NULL)
568 return NULL;
569
570 new->type = AGP_DCACHE_MEMORY;
571 new->page_count = pg_count;
572 new->num_scratch_pages = 0;
573 agp_free_page_array(new);
574 return new;
575 }
576 if (type == AGP_PHYS_MEMORY)
577 return alloc_agpphysmem_i8xx(pg_count, type);
578 return NULL;
579 }
580
581 static void intel_i810_free_by_type(struct agp_memory *curr)
582 {
583 agp_free_key(curr->key);
584 if (curr->type == AGP_PHYS_MEMORY) {
585 if (curr->page_count == 4)
586 i8xx_destroy_pages(curr->pages[0]);
587 else {
588 agp_bridge->driver->agp_destroy_page(curr->pages[0],
589 AGP_PAGE_DESTROY_UNMAP);
590 agp_bridge->driver->agp_destroy_page(curr->pages[0],
591 AGP_PAGE_DESTROY_FREE);
592 }
593 agp_free_page_array(curr);
594 }
595 kfree(curr);
596 }
597
598 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
599 dma_addr_t addr, int type)
600 {
601 /* Type checking must be done elsewhere */
602 return addr | bridge->driver->masks[type].mask;
603 }
604
605 static struct aper_size_info_fixed intel_i830_sizes[] =
606 {
607 {128, 32768, 5},
608 /* The 64M mode still requires a 128k gatt */
609 {64, 16384, 5},
610 {256, 65536, 6},
611 {512, 131072, 7},
612 };
613
614 static void intel_i830_init_gtt_entries(void)
615 {
616 u16 gmch_ctrl;
617 int gtt_entries;
618 u8 rdct;
619 int local = 0;
620 static const int ddt[4] = { 0, 16, 32, 64 };
621 int size; /* reserved space (in kb) at the top of stolen memory */
622
623 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
624
625 if (IS_I965) {
626 u32 pgetbl_ctl;
627 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
628
629 /* The 965 has a field telling us the size of the GTT,
630 * which may be larger than what is necessary to map the
631 * aperture.
632 */
633 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
634 case I965_PGETBL_SIZE_128KB:
635 size = 128;
636 break;
637 case I965_PGETBL_SIZE_256KB:
638 size = 256;
639 break;
640 case I965_PGETBL_SIZE_512KB:
641 size = 512;
642 break;
643 case I965_PGETBL_SIZE_1MB:
644 size = 1024;
645 break;
646 case I965_PGETBL_SIZE_2MB:
647 size = 2048;
648 break;
649 case I965_PGETBL_SIZE_1_5MB:
650 size = 1024 + 512;
651 break;
652 default:
653 dev_info(&intel_private.pcidev->dev,
654 "unknown page table size, assuming 512KB\n");
655 size = 512;
656 }
657 size += 4; /* add in BIOS popup space */
658 } else if (IS_G33 && !IS_IGD) {
659 /* G33's GTT size defined in gmch_ctrl */
660 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
661 case G33_PGETBL_SIZE_1M:
662 size = 1024;
663 break;
664 case G33_PGETBL_SIZE_2M:
665 size = 2048;
666 break;
667 default:
668 dev_info(&agp_bridge->dev->dev,
669 "unknown page table size 0x%x, assuming 512KB\n",
670 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
671 size = 512;
672 }
673 size += 4;
674 } else if (IS_G4X || IS_IGD) {
675 /* On 4 series hardware, GTT stolen is separate from graphics
676 * stolen, ignore it in stolen gtt entries counting. However,
677 * 4KB of the stolen memory doesn't get mapped to the GTT.
678 */
679 size = 4;
680 } else {
681 /* On previous hardware, the GTT size was just what was
682 * required to map the aperture.
683 */
684 size = agp_bridge->driver->fetch_size() + 4;
685 }
686
687 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
688 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
689 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
690 case I830_GMCH_GMS_STOLEN_512:
691 gtt_entries = KB(512) - KB(size);
692 break;
693 case I830_GMCH_GMS_STOLEN_1024:
694 gtt_entries = MB(1) - KB(size);
695 break;
696 case I830_GMCH_GMS_STOLEN_8192:
697 gtt_entries = MB(8) - KB(size);
698 break;
699 case I830_GMCH_GMS_LOCAL:
700 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
701 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
702 MB(ddt[I830_RDRAM_DDT(rdct)]);
703 local = 1;
704 break;
705 default:
706 gtt_entries = 0;
707 break;
708 }
709 } else {
710 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
711 case I855_GMCH_GMS_STOLEN_1M:
712 gtt_entries = MB(1) - KB(size);
713 break;
714 case I855_GMCH_GMS_STOLEN_4M:
715 gtt_entries = MB(4) - KB(size);
716 break;
717 case I855_GMCH_GMS_STOLEN_8M:
718 gtt_entries = MB(8) - KB(size);
719 break;
720 case I855_GMCH_GMS_STOLEN_16M:
721 gtt_entries = MB(16) - KB(size);
722 break;
723 case I855_GMCH_GMS_STOLEN_32M:
724 gtt_entries = MB(32) - KB(size);
725 break;
726 case I915_GMCH_GMS_STOLEN_48M:
727 /* Check it's really I915G */
728 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
729 gtt_entries = MB(48) - KB(size);
730 else
731 gtt_entries = 0;
732 break;
733 case I915_GMCH_GMS_STOLEN_64M:
734 /* Check it's really I915G */
735 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
736 gtt_entries = MB(64) - KB(size);
737 else
738 gtt_entries = 0;
739 break;
740 case G33_GMCH_GMS_STOLEN_128M:
741 if (IS_G33 || IS_I965 || IS_G4X)
742 gtt_entries = MB(128) - KB(size);
743 else
744 gtt_entries = 0;
745 break;
746 case G33_GMCH_GMS_STOLEN_256M:
747 if (IS_G33 || IS_I965 || IS_G4X)
748 gtt_entries = MB(256) - KB(size);
749 else
750 gtt_entries = 0;
751 break;
752 case INTEL_GMCH_GMS_STOLEN_96M:
753 if (IS_I965 || IS_G4X)
754 gtt_entries = MB(96) - KB(size);
755 else
756 gtt_entries = 0;
757 break;
758 case INTEL_GMCH_GMS_STOLEN_160M:
759 if (IS_I965 || IS_G4X)
760 gtt_entries = MB(160) - KB(size);
761 else
762 gtt_entries = 0;
763 break;
764 case INTEL_GMCH_GMS_STOLEN_224M:
765 if (IS_I965 || IS_G4X)
766 gtt_entries = MB(224) - KB(size);
767 else
768 gtt_entries = 0;
769 break;
770 case INTEL_GMCH_GMS_STOLEN_352M:
771 if (IS_I965 || IS_G4X)
772 gtt_entries = MB(352) - KB(size);
773 else
774 gtt_entries = 0;
775 break;
776 default:
777 gtt_entries = 0;
778 break;
779 }
780 }
781 if (gtt_entries > 0) {
782 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
783 gtt_entries / KB(1), local ? "local" : "stolen");
784 gtt_entries /= KB(4);
785 } else {
786 dev_info(&agp_bridge->dev->dev,
787 "no pre-allocated video memory detected\n");
788 gtt_entries = 0;
789 }
790
791 intel_private.gtt_entries = gtt_entries;
792 }
793
794 static void intel_i830_fini_flush(void)
795 {
796 kunmap(intel_private.i8xx_page);
797 intel_private.i8xx_flush_page = NULL;
798 unmap_page_from_agp(intel_private.i8xx_page);
799
800 __free_page(intel_private.i8xx_page);
801 intel_private.i8xx_page = NULL;
802 }
803
804 static void intel_i830_setup_flush(void)
805 {
806 /* return if we've already set the flush mechanism up */
807 if (intel_private.i8xx_page)
808 return;
809
810 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
811 if (!intel_private.i8xx_page)
812 return;
813
814 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
815 if (!intel_private.i8xx_flush_page)
816 intel_i830_fini_flush();
817 }
818
819 /* The chipset_flush interface needs to get data that has already been
820 * flushed out of the CPU all the way out to main memory, because the GPU
821 * doesn't snoop those buffers.
822 *
823 * The 8xx series doesn't have the same lovely interface for flushing the
824 * chipset write buffers that the later chips do. According to the 865
825 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
826 * that buffer out, we just fill 1KB and clflush it out, on the assumption
827 * that it'll push whatever was in there out. It appears to work.
828 */
829 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
830 {
831 unsigned int *pg = intel_private.i8xx_flush_page;
832
833 memset(pg, 0, 1024);
834
835 if (cpu_has_clflush)
836 clflush_cache_range(pg, 1024);
837 else if (wbinvd_on_all_cpus() != 0)
838 printk(KERN_ERR "Timed out waiting for cache flush.\n");
839 }
840
841 /* The intel i830 automatically initializes the agp aperture during POST.
842 * Use the memory already set aside for in the GTT.
843 */
844 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
845 {
846 int page_order;
847 struct aper_size_info_fixed *size;
848 int num_entries;
849 u32 temp;
850
851 size = agp_bridge->current_size;
852 page_order = size->page_order;
853 num_entries = size->num_entries;
854 agp_bridge->gatt_table_real = NULL;
855
856 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
857 temp &= 0xfff80000;
858
859 intel_private.registers = ioremap(temp, 128 * 4096);
860 if (!intel_private.registers)
861 return -ENOMEM;
862
863 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
864 global_cache_flush(); /* FIXME: ?? */
865
866 /* we have to call this as early as possible after the MMIO base address is known */
867 intel_i830_init_gtt_entries();
868
869 agp_bridge->gatt_table = NULL;
870
871 agp_bridge->gatt_bus_addr = temp;
872
873 return 0;
874 }
875
876 /* Return the gatt table to a sane state. Use the top of stolen
877 * memory for the GTT.
878 */
879 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
880 {
881 return 0;
882 }
883
884 static int intel_i830_fetch_size(void)
885 {
886 u16 gmch_ctrl;
887 struct aper_size_info_fixed *values;
888
889 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
890
891 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
892 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
893 /* 855GM/852GM/865G has 128MB aperture size */
894 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
895 agp_bridge->aperture_size_idx = 0;
896 return values[0].size;
897 }
898
899 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
900
901 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
902 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
903 agp_bridge->aperture_size_idx = 0;
904 return values[0].size;
905 } else {
906 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
907 agp_bridge->aperture_size_idx = 1;
908 return values[1].size;
909 }
910
911 return 0;
912 }
913
914 static int intel_i830_configure(void)
915 {
916 struct aper_size_info_fixed *current_size;
917 u32 temp;
918 u16 gmch_ctrl;
919 int i;
920
921 current_size = A_SIZE_FIX(agp_bridge->current_size);
922
923 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
924 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
925
926 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
927 gmch_ctrl |= I830_GMCH_ENABLED;
928 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
929
930 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
931 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
932
933 if (agp_bridge->driver->needs_scratch_page) {
934 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
935 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
936 }
937 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
938 }
939
940 global_cache_flush();
941
942 intel_i830_setup_flush();
943 return 0;
944 }
945
946 static void intel_i830_cleanup(void)
947 {
948 iounmap(intel_private.registers);
949 }
950
951 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
952 int type)
953 {
954 int i, j, num_entries;
955 void *temp;
956 int ret = -EINVAL;
957 int mask_type;
958
959 if (mem->page_count == 0)
960 goto out;
961
962 temp = agp_bridge->current_size;
963 num_entries = A_SIZE_FIX(temp)->num_entries;
964
965 if (pg_start < intel_private.gtt_entries) {
966 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
967 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
968 pg_start, intel_private.gtt_entries);
969
970 dev_info(&intel_private.pcidev->dev,
971 "trying to insert into local/stolen memory\n");
972 goto out_err;
973 }
974
975 if ((pg_start + mem->page_count) > num_entries)
976 goto out_err;
977
978 /* The i830 can't check the GTT for entries since its read only,
979 * depend on the caller to make the correct offset decisions.
980 */
981
982 if (type != mem->type)
983 goto out_err;
984
985 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
986
987 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
988 mask_type != INTEL_AGP_CACHED_MEMORY)
989 goto out_err;
990
991 if (!mem->is_flushed)
992 global_cache_flush();
993
994 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
995 writel(agp_bridge->driver->mask_memory(agp_bridge,
996 page_to_phys(mem->pages[i]), mask_type),
997 intel_private.registers+I810_PTE_BASE+(j*4));
998 }
999 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1000 agp_bridge->driver->tlb_flush(mem);
1001
1002 out:
1003 ret = 0;
1004 out_err:
1005 mem->is_flushed = true;
1006 return ret;
1007 }
1008
1009 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1010 int type)
1011 {
1012 int i;
1013
1014 if (mem->page_count == 0)
1015 return 0;
1016
1017 if (pg_start < intel_private.gtt_entries) {
1018 dev_info(&intel_private.pcidev->dev,
1019 "trying to disable local/stolen memory\n");
1020 return -EINVAL;
1021 }
1022
1023 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1024 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1025 }
1026 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1027
1028 agp_bridge->driver->tlb_flush(mem);
1029 return 0;
1030 }
1031
1032 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1033 {
1034 if (type == AGP_PHYS_MEMORY)
1035 return alloc_agpphysmem_i8xx(pg_count, type);
1036 /* always return NULL for other allocation types for now */
1037 return NULL;
1038 }
1039
1040 static int intel_alloc_chipset_flush_resource(void)
1041 {
1042 int ret;
1043 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1044 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1045 pcibios_align_resource, agp_bridge->dev);
1046
1047 return ret;
1048 }
1049
1050 static void intel_i915_setup_chipset_flush(void)
1051 {
1052 int ret;
1053 u32 temp;
1054
1055 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1056 if (!(temp & 0x1)) {
1057 intel_alloc_chipset_flush_resource();
1058 intel_private.resource_valid = 1;
1059 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1060 } else {
1061 temp &= ~1;
1062
1063 intel_private.resource_valid = 1;
1064 intel_private.ifp_resource.start = temp;
1065 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1066 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1067 /* some BIOSes reserve this area in a pnp some don't */
1068 if (ret)
1069 intel_private.resource_valid = 0;
1070 }
1071 }
1072
1073 static void intel_i965_g33_setup_chipset_flush(void)
1074 {
1075 u32 temp_hi, temp_lo;
1076 int ret;
1077
1078 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1079 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1080
1081 if (!(temp_lo & 0x1)) {
1082
1083 intel_alloc_chipset_flush_resource();
1084
1085 intel_private.resource_valid = 1;
1086 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1087 upper_32_bits(intel_private.ifp_resource.start));
1088 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1089 } else {
1090 u64 l64;
1091
1092 temp_lo &= ~0x1;
1093 l64 = ((u64)temp_hi << 32) | temp_lo;
1094
1095 intel_private.resource_valid = 1;
1096 intel_private.ifp_resource.start = l64;
1097 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1098 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1099 /* some BIOSes reserve this area in a pnp some don't */
1100 if (ret)
1101 intel_private.resource_valid = 0;
1102 }
1103 }
1104
1105 static void intel_i9xx_setup_flush(void)
1106 {
1107 /* return if already configured */
1108 if (intel_private.ifp_resource.start)
1109 return;
1110
1111 /* setup a resource for this object */
1112 intel_private.ifp_resource.name = "Intel Flush Page";
1113 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1114
1115 /* Setup chipset flush for 915 */
1116 if (IS_I965 || IS_G33 || IS_G4X) {
1117 intel_i965_g33_setup_chipset_flush();
1118 } else {
1119 intel_i915_setup_chipset_flush();
1120 }
1121
1122 if (intel_private.ifp_resource.start) {
1123 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1124 if (!intel_private.i9xx_flush_page)
1125 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1126 }
1127 }
1128
1129 static int intel_i915_configure(void)
1130 {
1131 struct aper_size_info_fixed *current_size;
1132 u32 temp;
1133 u16 gmch_ctrl;
1134 int i;
1135
1136 current_size = A_SIZE_FIX(agp_bridge->current_size);
1137
1138 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1139
1140 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1141
1142 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1143 gmch_ctrl |= I830_GMCH_ENABLED;
1144 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1145
1146 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1147 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1148
1149 if (agp_bridge->driver->needs_scratch_page) {
1150 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
1151 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1152 }
1153 readl(intel_private.gtt+i-1); /* PCI Posting. */
1154 }
1155
1156 global_cache_flush();
1157
1158 intel_i9xx_setup_flush();
1159
1160 return 0;
1161 }
1162
1163 static void intel_i915_cleanup(void)
1164 {
1165 if (intel_private.i9xx_flush_page)
1166 iounmap(intel_private.i9xx_flush_page);
1167 if (intel_private.resource_valid)
1168 release_resource(&intel_private.ifp_resource);
1169 intel_private.ifp_resource.start = 0;
1170 intel_private.resource_valid = 0;
1171 iounmap(intel_private.gtt);
1172 iounmap(intel_private.registers);
1173 }
1174
1175 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1176 {
1177 if (intel_private.i9xx_flush_page)
1178 writel(1, intel_private.i9xx_flush_page);
1179 }
1180
1181 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1182 int type)
1183 {
1184 int num_entries;
1185 void *temp;
1186 int ret = -EINVAL;
1187 int mask_type;
1188
1189 if (mem->page_count == 0)
1190 goto out;
1191
1192 temp = agp_bridge->current_size;
1193 num_entries = A_SIZE_FIX(temp)->num_entries;
1194
1195 if (pg_start < intel_private.gtt_entries) {
1196 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1197 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1198 pg_start, intel_private.gtt_entries);
1199
1200 dev_info(&intel_private.pcidev->dev,
1201 "trying to insert into local/stolen memory\n");
1202 goto out_err;
1203 }
1204
1205 if ((pg_start + mem->page_count) > num_entries)
1206 goto out_err;
1207
1208 /* The i915 can't check the GTT for entries since it's read only;
1209 * depend on the caller to make the correct offset decisions.
1210 */
1211
1212 if (type != mem->type)
1213 goto out_err;
1214
1215 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1216
1217 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1218 mask_type != INTEL_AGP_CACHED_MEMORY)
1219 goto out_err;
1220
1221 if (!mem->is_flushed)
1222 global_cache_flush();
1223
1224 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1225 agp_bridge->driver->tlb_flush(mem);
1226
1227 out:
1228 ret = 0;
1229 out_err:
1230 mem->is_flushed = true;
1231 return ret;
1232 }
1233
1234 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1235 int type)
1236 {
1237 int i;
1238
1239 if (mem->page_count == 0)
1240 return 0;
1241
1242 if (pg_start < intel_private.gtt_entries) {
1243 dev_info(&intel_private.pcidev->dev,
1244 "trying to disable local/stolen memory\n");
1245 return -EINVAL;
1246 }
1247
1248 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1249 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1250
1251 readl(intel_private.gtt+i-1);
1252
1253 agp_bridge->driver->tlb_flush(mem);
1254 return 0;
1255 }
1256
1257 /* Return the aperture size by just checking the resource length. The effect
1258 * described in the spec of the MSAC registers is just changing of the
1259 * resource size.
1260 */
1261 static int intel_i9xx_fetch_size(void)
1262 {
1263 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1264 int aper_size; /* size in megabytes */
1265 int i;
1266
1267 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1268
1269 for (i = 0; i < num_sizes; i++) {
1270 if (aper_size == intel_i830_sizes[i].size) {
1271 agp_bridge->current_size = intel_i830_sizes + i;
1272 agp_bridge->previous_size = agp_bridge->current_size;
1273 return aper_size;
1274 }
1275 }
1276
1277 return 0;
1278 }
1279
1280 /* The intel i915 automatically initializes the agp aperture during POST.
1281 * Use the memory already set aside for in the GTT.
1282 */
1283 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1284 {
1285 int page_order;
1286 struct aper_size_info_fixed *size;
1287 int num_entries;
1288 u32 temp, temp2;
1289 int gtt_map_size = 256 * 1024;
1290
1291 size = agp_bridge->current_size;
1292 page_order = size->page_order;
1293 num_entries = size->num_entries;
1294 agp_bridge->gatt_table_real = NULL;
1295
1296 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1297 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1298
1299 if (IS_G33)
1300 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1301 intel_private.gtt = ioremap(temp2, gtt_map_size);
1302 if (!intel_private.gtt)
1303 return -ENOMEM;
1304
1305 intel_private.gtt_total_size = gtt_map_size / 4;
1306
1307 temp &= 0xfff80000;
1308
1309 intel_private.registers = ioremap(temp, 128 * 4096);
1310 if (!intel_private.registers) {
1311 iounmap(intel_private.gtt);
1312 return -ENOMEM;
1313 }
1314
1315 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1316 global_cache_flush(); /* FIXME: ? */
1317
1318 /* we have to call this as early as possible after the MMIO base address is known */
1319 intel_i830_init_gtt_entries();
1320
1321 agp_bridge->gatt_table = NULL;
1322
1323 agp_bridge->gatt_bus_addr = temp;
1324
1325 return 0;
1326 }
1327
1328 /*
1329 * The i965 supports 36-bit physical addresses, but to keep
1330 * the format of the GTT the same, the bits that don't fit
1331 * in a 32-bit word are shifted down to bits 4..7.
1332 *
1333 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1334 * is always zero on 32-bit architectures, so no need to make
1335 * this conditional.
1336 */
1337 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1338 dma_addr_t addr, int type)
1339 {
1340 /* Shift high bits down */
1341 addr |= (addr >> 28) & 0xf0;
1342
1343 /* Type checking must be done elsewhere */
1344 return addr | bridge->driver->masks[type].mask;
1345 }
1346
1347 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1348 {
1349 switch (agp_bridge->dev->device) {
1350 case PCI_DEVICE_ID_INTEL_GM45_HB:
1351 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1352 case PCI_DEVICE_ID_INTEL_Q45_HB:
1353 case PCI_DEVICE_ID_INTEL_G45_HB:
1354 case PCI_DEVICE_ID_INTEL_G41_HB:
1355 case PCI_DEVICE_ID_INTEL_B43_HB:
1356 case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1357 case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1358 case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
1359 case PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB:
1360 *gtt_offset = *gtt_size = MB(2);
1361 break;
1362 default:
1363 *gtt_offset = *gtt_size = KB(512);
1364 }
1365 }
1366
1367 /* The intel i965 automatically initializes the agp aperture during POST.
1368 * Use the memory already set aside for in the GTT.
1369 */
1370 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1371 {
1372 int page_order;
1373 struct aper_size_info_fixed *size;
1374 int num_entries;
1375 u32 temp;
1376 int gtt_offset, gtt_size;
1377
1378 size = agp_bridge->current_size;
1379 page_order = size->page_order;
1380 num_entries = size->num_entries;
1381 agp_bridge->gatt_table_real = NULL;
1382
1383 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1384
1385 temp &= 0xfff00000;
1386
1387 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1388
1389 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1390
1391 if (!intel_private.gtt)
1392 return -ENOMEM;
1393
1394 intel_private.gtt_total_size = gtt_size / 4;
1395
1396 intel_private.registers = ioremap(temp, 128 * 4096);
1397 if (!intel_private.registers) {
1398 iounmap(intel_private.gtt);
1399 return -ENOMEM;
1400 }
1401
1402 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1403 global_cache_flush(); /* FIXME: ? */
1404
1405 /* we have to call this as early as possible after the MMIO base address is known */
1406 intel_i830_init_gtt_entries();
1407
1408 agp_bridge->gatt_table = NULL;
1409
1410 agp_bridge->gatt_bus_addr = temp;
1411
1412 return 0;
1413 }
1414
1415
1416 static int intel_fetch_size(void)
1417 {
1418 int i;
1419 u16 temp;
1420 struct aper_size_info_16 *values;
1421
1422 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1423 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1424
1425 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1426 if (temp == values[i].size_value) {
1427 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1428 agp_bridge->aperture_size_idx = i;
1429 return values[i].size;
1430 }
1431 }
1432
1433 return 0;
1434 }
1435
1436 static int __intel_8xx_fetch_size(u8 temp)
1437 {
1438 int i;
1439 struct aper_size_info_8 *values;
1440
1441 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1442
1443 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1444 if (temp == values[i].size_value) {
1445 agp_bridge->previous_size =
1446 agp_bridge->current_size = (void *) (values + i);
1447 agp_bridge->aperture_size_idx = i;
1448 return values[i].size;
1449 }
1450 }
1451 return 0;
1452 }
1453
1454 static int intel_8xx_fetch_size(void)
1455 {
1456 u8 temp;
1457
1458 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1459 return __intel_8xx_fetch_size(temp);
1460 }
1461
1462 static int intel_815_fetch_size(void)
1463 {
1464 u8 temp;
1465
1466 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1467 * one non-reserved bit, so mask the others out ... */
1468 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1469 temp &= (1 << 3);
1470
1471 return __intel_8xx_fetch_size(temp);
1472 }
1473
1474 static void intel_tlbflush(struct agp_memory *mem)
1475 {
1476 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1477 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1478 }
1479
1480
1481 static void intel_8xx_tlbflush(struct agp_memory *mem)
1482 {
1483 u32 temp;
1484 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1485 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1486 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1487 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1488 }
1489
1490
1491 static void intel_cleanup(void)
1492 {
1493 u16 temp;
1494 struct aper_size_info_16 *previous_size;
1495
1496 previous_size = A_SIZE_16(agp_bridge->previous_size);
1497 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1498 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1499 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1500 }
1501
1502
1503 static void intel_8xx_cleanup(void)
1504 {
1505 u16 temp;
1506 struct aper_size_info_8 *previous_size;
1507
1508 previous_size = A_SIZE_8(agp_bridge->previous_size);
1509 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1510 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1511 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1512 }
1513
1514
1515 static int intel_configure(void)
1516 {
1517 u32 temp;
1518 u16 temp2;
1519 struct aper_size_info_16 *current_size;
1520
1521 current_size = A_SIZE_16(agp_bridge->current_size);
1522
1523 /* aperture size */
1524 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1525
1526 /* address to map to */
1527 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1528 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1529
1530 /* attbase - aperture base */
1531 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1532
1533 /* agpctrl */
1534 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1535
1536 /* paccfg/nbxcfg */
1537 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1538 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1539 (temp2 & ~(1 << 10)) | (1 << 9));
1540 /* clear any possible error conditions */
1541 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1542 return 0;
1543 }
1544
1545 static int intel_815_configure(void)
1546 {
1547 u32 temp, addr;
1548 u8 temp2;
1549 struct aper_size_info_8 *current_size;
1550
1551 /* attbase - aperture base */
1552 /* the Intel 815 chipset spec. says that bits 29-31 in the
1553 * ATTBASE register are reserved -> try not to write them */
1554 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1555 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1556 return -EINVAL;
1557 }
1558
1559 current_size = A_SIZE_8(agp_bridge->current_size);
1560
1561 /* aperture size */
1562 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1563 current_size->size_value);
1564
1565 /* address to map to */
1566 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1567 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1568
1569 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1570 addr &= INTEL_815_ATTBASE_MASK;
1571 addr |= agp_bridge->gatt_bus_addr;
1572 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1573
1574 /* agpctrl */
1575 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1576
1577 /* apcont */
1578 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1579 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1580
1581 /* clear any possible error conditions */
1582 /* Oddness : this chipset seems to have no ERRSTS register ! */
1583 return 0;
1584 }
1585
1586 static void intel_820_tlbflush(struct agp_memory *mem)
1587 {
1588 return;
1589 }
1590
1591 static void intel_820_cleanup(void)
1592 {
1593 u8 temp;
1594 struct aper_size_info_8 *previous_size;
1595
1596 previous_size = A_SIZE_8(agp_bridge->previous_size);
1597 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1598 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1599 temp & ~(1 << 1));
1600 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1601 previous_size->size_value);
1602 }
1603
1604
1605 static int intel_820_configure(void)
1606 {
1607 u32 temp;
1608 u8 temp2;
1609 struct aper_size_info_8 *current_size;
1610
1611 current_size = A_SIZE_8(agp_bridge->current_size);
1612
1613 /* aperture size */
1614 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1615
1616 /* address to map to */
1617 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1618 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1619
1620 /* attbase - aperture base */
1621 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1622
1623 /* agpctrl */
1624 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1625
1626 /* global enable aperture access */
1627 /* This flag is not accessed through MCHCFG register as in */
1628 /* i850 chipset. */
1629 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1630 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1631 /* clear any possible AGP-related error conditions */
1632 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1633 return 0;
1634 }
1635
1636 static int intel_840_configure(void)
1637 {
1638 u32 temp;
1639 u16 temp2;
1640 struct aper_size_info_8 *current_size;
1641
1642 current_size = A_SIZE_8(agp_bridge->current_size);
1643
1644 /* aperture size */
1645 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1646
1647 /* address to map to */
1648 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1649 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1650
1651 /* attbase - aperture base */
1652 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1653
1654 /* agpctrl */
1655 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1656
1657 /* mcgcfg */
1658 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1659 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1660 /* clear any possible error conditions */
1661 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1662 return 0;
1663 }
1664
1665 static int intel_845_configure(void)
1666 {
1667 u32 temp;
1668 u8 temp2;
1669 struct aper_size_info_8 *current_size;
1670
1671 current_size = A_SIZE_8(agp_bridge->current_size);
1672
1673 /* aperture size */
1674 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1675
1676 if (agp_bridge->apbase_config != 0) {
1677 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1678 agp_bridge->apbase_config);
1679 } else {
1680 /* address to map to */
1681 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1682 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1683 agp_bridge->apbase_config = temp;
1684 }
1685
1686 /* attbase - aperture base */
1687 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1688
1689 /* agpctrl */
1690 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1691
1692 /* agpm */
1693 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1694 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1695 /* clear any possible error conditions */
1696 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1697
1698 intel_i830_setup_flush();
1699 return 0;
1700 }
1701
1702 static int intel_850_configure(void)
1703 {
1704 u32 temp;
1705 u16 temp2;
1706 struct aper_size_info_8 *current_size;
1707
1708 current_size = A_SIZE_8(agp_bridge->current_size);
1709
1710 /* aperture size */
1711 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1712
1713 /* address to map to */
1714 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1715 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1716
1717 /* attbase - aperture base */
1718 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1719
1720 /* agpctrl */
1721 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1722
1723 /* mcgcfg */
1724 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1725 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1726 /* clear any possible AGP-related error conditions */
1727 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1728 return 0;
1729 }
1730
1731 static int intel_860_configure(void)
1732 {
1733 u32 temp;
1734 u16 temp2;
1735 struct aper_size_info_8 *current_size;
1736
1737 current_size = A_SIZE_8(agp_bridge->current_size);
1738
1739 /* aperture size */
1740 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1741
1742 /* address to map to */
1743 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1744 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1745
1746 /* attbase - aperture base */
1747 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1748
1749 /* agpctrl */
1750 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1751
1752 /* mcgcfg */
1753 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1754 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1755 /* clear any possible AGP-related error conditions */
1756 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1757 return 0;
1758 }
1759
1760 static int intel_830mp_configure(void)
1761 {
1762 u32 temp;
1763 u16 temp2;
1764 struct aper_size_info_8 *current_size;
1765
1766 current_size = A_SIZE_8(agp_bridge->current_size);
1767
1768 /* aperture size */
1769 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1770
1771 /* address to map to */
1772 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1773 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1774
1775 /* attbase - aperture base */
1776 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1777
1778 /* agpctrl */
1779 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1780
1781 /* gmch */
1782 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1783 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1784 /* clear any possible AGP-related error conditions */
1785 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1786 return 0;
1787 }
1788
1789 static int intel_7505_configure(void)
1790 {
1791 u32 temp;
1792 u16 temp2;
1793 struct aper_size_info_8 *current_size;
1794
1795 current_size = A_SIZE_8(agp_bridge->current_size);
1796
1797 /* aperture size */
1798 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1799
1800 /* address to map to */
1801 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1802 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1803
1804 /* attbase - aperture base */
1805 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1806
1807 /* agpctrl */
1808 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1809
1810 /* mchcfg */
1811 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1812 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1813
1814 return 0;
1815 }
1816
1817 /* Setup function */
1818 static const struct gatt_mask intel_generic_masks[] =
1819 {
1820 {.mask = 0x00000017, .type = 0}
1821 };
1822
1823 static const struct aper_size_info_8 intel_815_sizes[2] =
1824 {
1825 {64, 16384, 4, 0},
1826 {32, 8192, 3, 8},
1827 };
1828
1829 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1830 {
1831 {256, 65536, 6, 0},
1832 {128, 32768, 5, 32},
1833 {64, 16384, 4, 48},
1834 {32, 8192, 3, 56},
1835 {16, 4096, 2, 60},
1836 {8, 2048, 1, 62},
1837 {4, 1024, 0, 63}
1838 };
1839
1840 static const struct aper_size_info_16 intel_generic_sizes[7] =
1841 {
1842 {256, 65536, 6, 0},
1843 {128, 32768, 5, 32},
1844 {64, 16384, 4, 48},
1845 {32, 8192, 3, 56},
1846 {16, 4096, 2, 60},
1847 {8, 2048, 1, 62},
1848 {4, 1024, 0, 63}
1849 };
1850
1851 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1852 {
1853 {256, 65536, 6, 0},
1854 {128, 32768, 5, 32},
1855 {64, 16384, 4, 48},
1856 {32, 8192, 3, 56}
1857 };
1858
1859 static const struct agp_bridge_driver intel_generic_driver = {
1860 .owner = THIS_MODULE,
1861 .aperture_sizes = intel_generic_sizes,
1862 .size_type = U16_APER_SIZE,
1863 .num_aperture_sizes = 7,
1864 .configure = intel_configure,
1865 .fetch_size = intel_fetch_size,
1866 .cleanup = intel_cleanup,
1867 .tlb_flush = intel_tlbflush,
1868 .mask_memory = agp_generic_mask_memory,
1869 .masks = intel_generic_masks,
1870 .agp_enable = agp_generic_enable,
1871 .cache_flush = global_cache_flush,
1872 .create_gatt_table = agp_generic_create_gatt_table,
1873 .free_gatt_table = agp_generic_free_gatt_table,
1874 .insert_memory = agp_generic_insert_memory,
1875 .remove_memory = agp_generic_remove_memory,
1876 .alloc_by_type = agp_generic_alloc_by_type,
1877 .free_by_type = agp_generic_free_by_type,
1878 .agp_alloc_page = agp_generic_alloc_page,
1879 .agp_alloc_pages = agp_generic_alloc_pages,
1880 .agp_destroy_page = agp_generic_destroy_page,
1881 .agp_destroy_pages = agp_generic_destroy_pages,
1882 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1883 };
1884
1885 static const struct agp_bridge_driver intel_810_driver = {
1886 .owner = THIS_MODULE,
1887 .aperture_sizes = intel_i810_sizes,
1888 .size_type = FIXED_APER_SIZE,
1889 .num_aperture_sizes = 2,
1890 .needs_scratch_page = true,
1891 .configure = intel_i810_configure,
1892 .fetch_size = intel_i810_fetch_size,
1893 .cleanup = intel_i810_cleanup,
1894 .tlb_flush = intel_i810_tlbflush,
1895 .mask_memory = intel_i810_mask_memory,
1896 .masks = intel_i810_masks,
1897 .agp_enable = intel_i810_agp_enable,
1898 .cache_flush = global_cache_flush,
1899 .create_gatt_table = agp_generic_create_gatt_table,
1900 .free_gatt_table = agp_generic_free_gatt_table,
1901 .insert_memory = intel_i810_insert_entries,
1902 .remove_memory = intel_i810_remove_entries,
1903 .alloc_by_type = intel_i810_alloc_by_type,
1904 .free_by_type = intel_i810_free_by_type,
1905 .agp_alloc_page = agp_generic_alloc_page,
1906 .agp_alloc_pages = agp_generic_alloc_pages,
1907 .agp_destroy_page = agp_generic_destroy_page,
1908 .agp_destroy_pages = agp_generic_destroy_pages,
1909 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1910 };
1911
1912 static const struct agp_bridge_driver intel_815_driver = {
1913 .owner = THIS_MODULE,
1914 .aperture_sizes = intel_815_sizes,
1915 .size_type = U8_APER_SIZE,
1916 .num_aperture_sizes = 2,
1917 .configure = intel_815_configure,
1918 .fetch_size = intel_815_fetch_size,
1919 .cleanup = intel_8xx_cleanup,
1920 .tlb_flush = intel_8xx_tlbflush,
1921 .mask_memory = agp_generic_mask_memory,
1922 .masks = intel_generic_masks,
1923 .agp_enable = agp_generic_enable,
1924 .cache_flush = global_cache_flush,
1925 .create_gatt_table = agp_generic_create_gatt_table,
1926 .free_gatt_table = agp_generic_free_gatt_table,
1927 .insert_memory = agp_generic_insert_memory,
1928 .remove_memory = agp_generic_remove_memory,
1929 .alloc_by_type = agp_generic_alloc_by_type,
1930 .free_by_type = agp_generic_free_by_type,
1931 .agp_alloc_page = agp_generic_alloc_page,
1932 .agp_alloc_pages = agp_generic_alloc_pages,
1933 .agp_destroy_page = agp_generic_destroy_page,
1934 .agp_destroy_pages = agp_generic_destroy_pages,
1935 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1936 };
1937
1938 static const struct agp_bridge_driver intel_830_driver = {
1939 .owner = THIS_MODULE,
1940 .aperture_sizes = intel_i830_sizes,
1941 .size_type = FIXED_APER_SIZE,
1942 .num_aperture_sizes = 4,
1943 .needs_scratch_page = true,
1944 .configure = intel_i830_configure,
1945 .fetch_size = intel_i830_fetch_size,
1946 .cleanup = intel_i830_cleanup,
1947 .tlb_flush = intel_i810_tlbflush,
1948 .mask_memory = intel_i810_mask_memory,
1949 .masks = intel_i810_masks,
1950 .agp_enable = intel_i810_agp_enable,
1951 .cache_flush = global_cache_flush,
1952 .create_gatt_table = intel_i830_create_gatt_table,
1953 .free_gatt_table = intel_i830_free_gatt_table,
1954 .insert_memory = intel_i830_insert_entries,
1955 .remove_memory = intel_i830_remove_entries,
1956 .alloc_by_type = intel_i830_alloc_by_type,
1957 .free_by_type = intel_i810_free_by_type,
1958 .agp_alloc_page = agp_generic_alloc_page,
1959 .agp_alloc_pages = agp_generic_alloc_pages,
1960 .agp_destroy_page = agp_generic_destroy_page,
1961 .agp_destroy_pages = agp_generic_destroy_pages,
1962 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1963 .chipset_flush = intel_i830_chipset_flush,
1964 };
1965
1966 static const struct agp_bridge_driver intel_820_driver = {
1967 .owner = THIS_MODULE,
1968 .aperture_sizes = intel_8xx_sizes,
1969 .size_type = U8_APER_SIZE,
1970 .num_aperture_sizes = 7,
1971 .configure = intel_820_configure,
1972 .fetch_size = intel_8xx_fetch_size,
1973 .cleanup = intel_820_cleanup,
1974 .tlb_flush = intel_820_tlbflush,
1975 .mask_memory = agp_generic_mask_memory,
1976 .masks = intel_generic_masks,
1977 .agp_enable = agp_generic_enable,
1978 .cache_flush = global_cache_flush,
1979 .create_gatt_table = agp_generic_create_gatt_table,
1980 .free_gatt_table = agp_generic_free_gatt_table,
1981 .insert_memory = agp_generic_insert_memory,
1982 .remove_memory = agp_generic_remove_memory,
1983 .alloc_by_type = agp_generic_alloc_by_type,
1984 .free_by_type = agp_generic_free_by_type,
1985 .agp_alloc_page = agp_generic_alloc_page,
1986 .agp_alloc_pages = agp_generic_alloc_pages,
1987 .agp_destroy_page = agp_generic_destroy_page,
1988 .agp_destroy_pages = agp_generic_destroy_pages,
1989 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1990 };
1991
1992 static const struct agp_bridge_driver intel_830mp_driver = {
1993 .owner = THIS_MODULE,
1994 .aperture_sizes = intel_830mp_sizes,
1995 .size_type = U8_APER_SIZE,
1996 .num_aperture_sizes = 4,
1997 .configure = intel_830mp_configure,
1998 .fetch_size = intel_8xx_fetch_size,
1999 .cleanup = intel_8xx_cleanup,
2000 .tlb_flush = intel_8xx_tlbflush,
2001 .mask_memory = agp_generic_mask_memory,
2002 .masks = intel_generic_masks,
2003 .agp_enable = agp_generic_enable,
2004 .cache_flush = global_cache_flush,
2005 .create_gatt_table = agp_generic_create_gatt_table,
2006 .free_gatt_table = agp_generic_free_gatt_table,
2007 .insert_memory = agp_generic_insert_memory,
2008 .remove_memory = agp_generic_remove_memory,
2009 .alloc_by_type = agp_generic_alloc_by_type,
2010 .free_by_type = agp_generic_free_by_type,
2011 .agp_alloc_page = agp_generic_alloc_page,
2012 .agp_alloc_pages = agp_generic_alloc_pages,
2013 .agp_destroy_page = agp_generic_destroy_page,
2014 .agp_destroy_pages = agp_generic_destroy_pages,
2015 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2016 };
2017
2018 static const struct agp_bridge_driver intel_840_driver = {
2019 .owner = THIS_MODULE,
2020 .aperture_sizes = intel_8xx_sizes,
2021 .size_type = U8_APER_SIZE,
2022 .num_aperture_sizes = 7,
2023 .configure = intel_840_configure,
2024 .fetch_size = intel_8xx_fetch_size,
2025 .cleanup = intel_8xx_cleanup,
2026 .tlb_flush = intel_8xx_tlbflush,
2027 .mask_memory = agp_generic_mask_memory,
2028 .masks = intel_generic_masks,
2029 .agp_enable = agp_generic_enable,
2030 .cache_flush = global_cache_flush,
2031 .create_gatt_table = agp_generic_create_gatt_table,
2032 .free_gatt_table = agp_generic_free_gatt_table,
2033 .insert_memory = agp_generic_insert_memory,
2034 .remove_memory = agp_generic_remove_memory,
2035 .alloc_by_type = agp_generic_alloc_by_type,
2036 .free_by_type = agp_generic_free_by_type,
2037 .agp_alloc_page = agp_generic_alloc_page,
2038 .agp_alloc_pages = agp_generic_alloc_pages,
2039 .agp_destroy_page = agp_generic_destroy_page,
2040 .agp_destroy_pages = agp_generic_destroy_pages,
2041 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2042 };
2043
2044 static const struct agp_bridge_driver intel_845_driver = {
2045 .owner = THIS_MODULE,
2046 .aperture_sizes = intel_8xx_sizes,
2047 .size_type = U8_APER_SIZE,
2048 .num_aperture_sizes = 7,
2049 .configure = intel_845_configure,
2050 .fetch_size = intel_8xx_fetch_size,
2051 .cleanup = intel_8xx_cleanup,
2052 .tlb_flush = intel_8xx_tlbflush,
2053 .mask_memory = agp_generic_mask_memory,
2054 .masks = intel_generic_masks,
2055 .agp_enable = agp_generic_enable,
2056 .cache_flush = global_cache_flush,
2057 .create_gatt_table = agp_generic_create_gatt_table,
2058 .free_gatt_table = agp_generic_free_gatt_table,
2059 .insert_memory = agp_generic_insert_memory,
2060 .remove_memory = agp_generic_remove_memory,
2061 .alloc_by_type = agp_generic_alloc_by_type,
2062 .free_by_type = agp_generic_free_by_type,
2063 .agp_alloc_page = agp_generic_alloc_page,
2064 .agp_alloc_pages = agp_generic_alloc_pages,
2065 .agp_destroy_page = agp_generic_destroy_page,
2066 .agp_destroy_pages = agp_generic_destroy_pages,
2067 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2068 .chipset_flush = intel_i830_chipset_flush,
2069 };
2070
2071 static const struct agp_bridge_driver intel_850_driver = {
2072 .owner = THIS_MODULE,
2073 .aperture_sizes = intel_8xx_sizes,
2074 .size_type = U8_APER_SIZE,
2075 .num_aperture_sizes = 7,
2076 .configure = intel_850_configure,
2077 .fetch_size = intel_8xx_fetch_size,
2078 .cleanup = intel_8xx_cleanup,
2079 .tlb_flush = intel_8xx_tlbflush,
2080 .mask_memory = agp_generic_mask_memory,
2081 .masks = intel_generic_masks,
2082 .agp_enable = agp_generic_enable,
2083 .cache_flush = global_cache_flush,
2084 .create_gatt_table = agp_generic_create_gatt_table,
2085 .free_gatt_table = agp_generic_free_gatt_table,
2086 .insert_memory = agp_generic_insert_memory,
2087 .remove_memory = agp_generic_remove_memory,
2088 .alloc_by_type = agp_generic_alloc_by_type,
2089 .free_by_type = agp_generic_free_by_type,
2090 .agp_alloc_page = agp_generic_alloc_page,
2091 .agp_alloc_pages = agp_generic_alloc_pages,
2092 .agp_destroy_page = agp_generic_destroy_page,
2093 .agp_destroy_pages = agp_generic_destroy_pages,
2094 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2095 };
2096
2097 static const struct agp_bridge_driver intel_860_driver = {
2098 .owner = THIS_MODULE,
2099 .aperture_sizes = intel_8xx_sizes,
2100 .size_type = U8_APER_SIZE,
2101 .num_aperture_sizes = 7,
2102 .configure = intel_860_configure,
2103 .fetch_size = intel_8xx_fetch_size,
2104 .cleanup = intel_8xx_cleanup,
2105 .tlb_flush = intel_8xx_tlbflush,
2106 .mask_memory = agp_generic_mask_memory,
2107 .masks = intel_generic_masks,
2108 .agp_enable = agp_generic_enable,
2109 .cache_flush = global_cache_flush,
2110 .create_gatt_table = agp_generic_create_gatt_table,
2111 .free_gatt_table = agp_generic_free_gatt_table,
2112 .insert_memory = agp_generic_insert_memory,
2113 .remove_memory = agp_generic_remove_memory,
2114 .alloc_by_type = agp_generic_alloc_by_type,
2115 .free_by_type = agp_generic_free_by_type,
2116 .agp_alloc_page = agp_generic_alloc_page,
2117 .agp_alloc_pages = agp_generic_alloc_pages,
2118 .agp_destroy_page = agp_generic_destroy_page,
2119 .agp_destroy_pages = agp_generic_destroy_pages,
2120 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2121 };
2122
2123 static const struct agp_bridge_driver intel_915_driver = {
2124 .owner = THIS_MODULE,
2125 .aperture_sizes = intel_i830_sizes,
2126 .size_type = FIXED_APER_SIZE,
2127 .num_aperture_sizes = 4,
2128 .needs_scratch_page = true,
2129 .configure = intel_i915_configure,
2130 .fetch_size = intel_i9xx_fetch_size,
2131 .cleanup = intel_i915_cleanup,
2132 .tlb_flush = intel_i810_tlbflush,
2133 .mask_memory = intel_i810_mask_memory,
2134 .masks = intel_i810_masks,
2135 .agp_enable = intel_i810_agp_enable,
2136 .cache_flush = global_cache_flush,
2137 .create_gatt_table = intel_i915_create_gatt_table,
2138 .free_gatt_table = intel_i830_free_gatt_table,
2139 .insert_memory = intel_i915_insert_entries,
2140 .remove_memory = intel_i915_remove_entries,
2141 .alloc_by_type = intel_i830_alloc_by_type,
2142 .free_by_type = intel_i810_free_by_type,
2143 .agp_alloc_page = agp_generic_alloc_page,
2144 .agp_alloc_pages = agp_generic_alloc_pages,
2145 .agp_destroy_page = agp_generic_destroy_page,
2146 .agp_destroy_pages = agp_generic_destroy_pages,
2147 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2148 .chipset_flush = intel_i915_chipset_flush,
2149 #ifdef USE_PCI_DMA_API
2150 .agp_map_page = intel_agp_map_page,
2151 .agp_unmap_page = intel_agp_unmap_page,
2152 .agp_map_memory = intel_agp_map_memory,
2153 .agp_unmap_memory = intel_agp_unmap_memory,
2154 #endif
2155 };
2156
2157 static const struct agp_bridge_driver intel_i965_driver = {
2158 .owner = THIS_MODULE,
2159 .aperture_sizes = intel_i830_sizes,
2160 .size_type = FIXED_APER_SIZE,
2161 .num_aperture_sizes = 4,
2162 .needs_scratch_page = true,
2163 .configure = intel_i915_configure,
2164 .fetch_size = intel_i9xx_fetch_size,
2165 .cleanup = intel_i915_cleanup,
2166 .tlb_flush = intel_i810_tlbflush,
2167 .mask_memory = intel_i965_mask_memory,
2168 .masks = intel_i810_masks,
2169 .agp_enable = intel_i810_agp_enable,
2170 .cache_flush = global_cache_flush,
2171 .create_gatt_table = intel_i965_create_gatt_table,
2172 .free_gatt_table = intel_i830_free_gatt_table,
2173 .insert_memory = intel_i915_insert_entries,
2174 .remove_memory = intel_i915_remove_entries,
2175 .alloc_by_type = intel_i830_alloc_by_type,
2176 .free_by_type = intel_i810_free_by_type,
2177 .agp_alloc_page = agp_generic_alloc_page,
2178 .agp_alloc_pages = agp_generic_alloc_pages,
2179 .agp_destroy_page = agp_generic_destroy_page,
2180 .agp_destroy_pages = agp_generic_destroy_pages,
2181 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2182 .chipset_flush = intel_i915_chipset_flush,
2183 #ifdef USE_PCI_DMA_API
2184 .agp_map_page = intel_agp_map_page,
2185 .agp_unmap_page = intel_agp_unmap_page,
2186 .agp_map_memory = intel_agp_map_memory,
2187 .agp_unmap_memory = intel_agp_unmap_memory,
2188 #endif
2189 };
2190
2191 static const struct agp_bridge_driver intel_7505_driver = {
2192 .owner = THIS_MODULE,
2193 .aperture_sizes = intel_8xx_sizes,
2194 .size_type = U8_APER_SIZE,
2195 .num_aperture_sizes = 7,
2196 .configure = intel_7505_configure,
2197 .fetch_size = intel_8xx_fetch_size,
2198 .cleanup = intel_8xx_cleanup,
2199 .tlb_flush = intel_8xx_tlbflush,
2200 .mask_memory = agp_generic_mask_memory,
2201 .masks = intel_generic_masks,
2202 .agp_enable = agp_generic_enable,
2203 .cache_flush = global_cache_flush,
2204 .create_gatt_table = agp_generic_create_gatt_table,
2205 .free_gatt_table = agp_generic_free_gatt_table,
2206 .insert_memory = agp_generic_insert_memory,
2207 .remove_memory = agp_generic_remove_memory,
2208 .alloc_by_type = agp_generic_alloc_by_type,
2209 .free_by_type = agp_generic_free_by_type,
2210 .agp_alloc_page = agp_generic_alloc_page,
2211 .agp_alloc_pages = agp_generic_alloc_pages,
2212 .agp_destroy_page = agp_generic_destroy_page,
2213 .agp_destroy_pages = agp_generic_destroy_pages,
2214 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2215 };
2216
2217 static const struct agp_bridge_driver intel_g33_driver = {
2218 .owner = THIS_MODULE,
2219 .aperture_sizes = intel_i830_sizes,
2220 .size_type = FIXED_APER_SIZE,
2221 .num_aperture_sizes = 4,
2222 .needs_scratch_page = true,
2223 .configure = intel_i915_configure,
2224 .fetch_size = intel_i9xx_fetch_size,
2225 .cleanup = intel_i915_cleanup,
2226 .tlb_flush = intel_i810_tlbflush,
2227 .mask_memory = intel_i965_mask_memory,
2228 .masks = intel_i810_masks,
2229 .agp_enable = intel_i810_agp_enable,
2230 .cache_flush = global_cache_flush,
2231 .create_gatt_table = intel_i915_create_gatt_table,
2232 .free_gatt_table = intel_i830_free_gatt_table,
2233 .insert_memory = intel_i915_insert_entries,
2234 .remove_memory = intel_i915_remove_entries,
2235 .alloc_by_type = intel_i830_alloc_by_type,
2236 .free_by_type = intel_i810_free_by_type,
2237 .agp_alloc_page = agp_generic_alloc_page,
2238 .agp_alloc_pages = agp_generic_alloc_pages,
2239 .agp_destroy_page = agp_generic_destroy_page,
2240 .agp_destroy_pages = agp_generic_destroy_pages,
2241 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2242 .chipset_flush = intel_i915_chipset_flush,
2243 #ifdef USE_PCI_DMA_API
2244 .agp_map_page = intel_agp_map_page,
2245 .agp_unmap_page = intel_agp_unmap_page,
2246 .agp_map_memory = intel_agp_map_memory,
2247 .agp_unmap_memory = intel_agp_unmap_memory,
2248 #endif
2249 };
2250
2251 static int find_gmch(u16 device)
2252 {
2253 struct pci_dev *gmch_device;
2254
2255 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2256 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2257 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2258 device, gmch_device);
2259 }
2260
2261 if (!gmch_device)
2262 return 0;
2263
2264 intel_private.pcidev = gmch_device;
2265 return 1;
2266 }
2267
2268 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2269 * driver and gmch_driver must be non-null, and find_gmch will determine
2270 * which one should be used if a gmch_chip_id is present.
2271 */
2272 static const struct intel_driver_description {
2273 unsigned int chip_id;
2274 unsigned int gmch_chip_id;
2275 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2276 char *name;
2277 const struct agp_bridge_driver *driver;
2278 const struct agp_bridge_driver *gmch_driver;
2279 } intel_agp_chipsets[] = {
2280 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2281 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2282 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2283 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2284 NULL, &intel_810_driver },
2285 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2286 NULL, &intel_810_driver },
2287 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2288 NULL, &intel_810_driver },
2289 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2290 &intel_815_driver, &intel_810_driver },
2291 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2292 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2293 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2294 &intel_830mp_driver, &intel_830_driver },
2295 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2296 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2297 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2298 &intel_845_driver, &intel_830_driver },
2299 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2300 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2301 &intel_845_driver, &intel_830_driver },
2302 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2303 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2304 &intel_845_driver, &intel_830_driver },
2305 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2306 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2307 &intel_845_driver, &intel_830_driver },
2308 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2309 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2310 NULL, &intel_915_driver },
2311 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2312 NULL, &intel_915_driver },
2313 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2314 NULL, &intel_915_driver },
2315 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2316 NULL, &intel_915_driver },
2317 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2318 NULL, &intel_915_driver },
2319 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2320 NULL, &intel_915_driver },
2321 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2322 NULL, &intel_i965_driver },
2323 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2324 NULL, &intel_i965_driver },
2325 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2326 NULL, &intel_i965_driver },
2327 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2328 NULL, &intel_i965_driver },
2329 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2330 NULL, &intel_i965_driver },
2331 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2332 NULL, &intel_i965_driver },
2333 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2334 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2335 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2336 NULL, &intel_g33_driver },
2337 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2338 NULL, &intel_g33_driver },
2339 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2340 NULL, &intel_g33_driver },
2341 { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2342 NULL, &intel_g33_driver },
2343 { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2344 NULL, &intel_g33_driver },
2345 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2346 "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2347 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2348 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2349 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2350 "Q45/Q43", NULL, &intel_i965_driver },
2351 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2352 "G45/G43", NULL, &intel_i965_driver },
2353 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2354 "B43", NULL, &intel_i965_driver },
2355 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2356 "G41", NULL, &intel_i965_driver },
2357 { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2358 "IGDNG/D", NULL, &intel_i965_driver },
2359 { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2360 "IGDNG/M", NULL, &intel_i965_driver },
2361 { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2362 "IGDNG/MA", NULL, &intel_i965_driver },
2363 { PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2364 "IGDNG/MC2", NULL, &intel_i965_driver },
2365 { 0, 0, 0, NULL, NULL, NULL }
2366 };
2367
2368 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2369 const struct pci_device_id *ent)
2370 {
2371 struct agp_bridge_data *bridge;
2372 u8 cap_ptr = 0;
2373 struct resource *r;
2374 int i;
2375
2376 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2377
2378 bridge = agp_alloc_bridge();
2379 if (!bridge)
2380 return -ENOMEM;
2381
2382 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2383 /* In case that multiple models of gfx chip may
2384 stand on same host bridge type, this can be
2385 sure we detect the right IGD. */
2386 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2387 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2388 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2389 bridge->driver =
2390 intel_agp_chipsets[i].gmch_driver;
2391 break;
2392 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2393 continue;
2394 } else {
2395 bridge->driver = intel_agp_chipsets[i].driver;
2396 break;
2397 }
2398 }
2399 }
2400
2401 if (intel_agp_chipsets[i].name == NULL) {
2402 if (cap_ptr)
2403 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2404 pdev->vendor, pdev->device);
2405 agp_put_bridge(bridge);
2406 return -ENODEV;
2407 }
2408
2409 if (bridge->driver == NULL) {
2410 /* bridge has no AGP and no IGD detected */
2411 if (cap_ptr)
2412 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2413 intel_agp_chipsets[i].gmch_chip_id);
2414 agp_put_bridge(bridge);
2415 return -ENODEV;
2416 }
2417
2418 bridge->dev = pdev;
2419 bridge->capndx = cap_ptr;
2420 bridge->dev_private_data = &intel_private;
2421
2422 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2423
2424 /*
2425 * The following fixes the case where the BIOS has "forgotten" to
2426 * provide an address range for the GART.
2427 * 20030610 - hamish@zot.org
2428 */
2429 r = &pdev->resource[0];
2430 if (!r->start && r->end) {
2431 if (pci_assign_resource(pdev, 0)) {
2432 dev_err(&pdev->dev, "can't assign resource 0\n");
2433 agp_put_bridge(bridge);
2434 return -ENODEV;
2435 }
2436 }
2437
2438 /*
2439 * If the device has not been properly setup, the following will catch
2440 * the problem and should stop the system from crashing.
2441 * 20030610 - hamish@zot.org
2442 */
2443 if (pci_enable_device(pdev)) {
2444 dev_err(&pdev->dev, "can't enable PCI device\n");
2445 agp_put_bridge(bridge);
2446 return -ENODEV;
2447 }
2448
2449 /* Fill in the mode register */
2450 if (cap_ptr) {
2451 pci_read_config_dword(pdev,
2452 bridge->capndx+PCI_AGP_STATUS,
2453 &bridge->mode);
2454 }
2455
2456 if (bridge->driver->mask_memory == intel_i965_mask_memory)
2457 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
2458 dev_err(&intel_private.pcidev->dev,
2459 "set gfx device dma mask 36bit failed!\n");
2460
2461 pci_set_drvdata(pdev, bridge);
2462 return agp_add_bridge(bridge);
2463 }
2464
2465 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2466 {
2467 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2468
2469 agp_remove_bridge(bridge);
2470
2471 if (intel_private.pcidev)
2472 pci_dev_put(intel_private.pcidev);
2473
2474 agp_put_bridge(bridge);
2475 }
2476
2477 #ifdef CONFIG_PM
2478 static int agp_intel_resume(struct pci_dev *pdev)
2479 {
2480 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2481 int ret_val;
2482
2483 if (bridge->driver == &intel_generic_driver)
2484 intel_configure();
2485 else if (bridge->driver == &intel_850_driver)
2486 intel_850_configure();
2487 else if (bridge->driver == &intel_845_driver)
2488 intel_845_configure();
2489 else if (bridge->driver == &intel_830mp_driver)
2490 intel_830mp_configure();
2491 else if (bridge->driver == &intel_915_driver)
2492 intel_i915_configure();
2493 else if (bridge->driver == &intel_830_driver)
2494 intel_i830_configure();
2495 else if (bridge->driver == &intel_810_driver)
2496 intel_i810_configure();
2497 else if (bridge->driver == &intel_i965_driver)
2498 intel_i915_configure();
2499
2500 ret_val = agp_rebind_memory();
2501 if (ret_val != 0)
2502 return ret_val;
2503
2504 return 0;
2505 }
2506 #endif
2507
2508 static struct pci_device_id agp_intel_pci_table[] = {
2509 #define ID(x) \
2510 { \
2511 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2512 .class_mask = ~0, \
2513 .vendor = PCI_VENDOR_ID_INTEL, \
2514 .device = x, \
2515 .subvendor = PCI_ANY_ID, \
2516 .subdevice = PCI_ANY_ID, \
2517 }
2518 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2519 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2520 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2521 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2522 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2523 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2524 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2525 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2526 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2527 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2528 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2529 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2530 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2531 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2532 ID(PCI_DEVICE_ID_INTEL_82854_HB),
2533 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2534 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2535 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2536 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2537 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2538 ID(PCI_DEVICE_ID_INTEL_7505_0),
2539 ID(PCI_DEVICE_ID_INTEL_7205_0),
2540 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2541 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2542 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2543 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2544 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2545 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2546 ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2547 ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2548 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2549 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2550 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2551 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2552 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2553 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2554 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2555 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2556 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2557 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2558 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2559 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2560 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2561 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2562 ID(PCI_DEVICE_ID_INTEL_B43_HB),
2563 ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2564 ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2565 ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),
2566 ID(PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB),
2567 { }
2568 };
2569
2570 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2571
2572 static struct pci_driver agp_intel_pci_driver = {
2573 .name = "agpgart-intel",
2574 .id_table = agp_intel_pci_table,
2575 .probe = agp_intel_probe,
2576 .remove = __devexit_p(agp_intel_remove),
2577 #ifdef CONFIG_PM
2578 .resume = agp_intel_resume,
2579 #endif
2580 };
2581
2582 static int __init agp_intel_init(void)
2583 {
2584 if (agp_off)
2585 return -EINVAL;
2586 return pci_register_driver(&agp_intel_pci_driver);
2587 }
2588
2589 static void __exit agp_intel_cleanup(void)
2590 {
2591 pci_unregister_driver(&agp_intel_pci_driver);
2592 }
2593
2594 module_init(agp_intel_init);
2595 module_exit(agp_intel_cleanup);
2596
2597 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2598 MODULE_LICENSE("GPL and additional rights");
Linux MOXA ART SoC ARM port