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init from v2.6.32.60
[mach-moxart.git] / drivers / gpu / drm / radeon / r300.c
blobd8c4f72eef8ed6eaaf9e3a53335162af0d8491da
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
35 #include "r300d.h"
36 #include "rv350d.h"
37 #include "r300_reg_safe.h"
38
39 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
40
41 /*
42 * rv370,rv380 PCIE GART
43 */
44 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
45
46 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
47 {
48 uint32_t tmp;
49 int i;
50
51 /* Workaround HW bug do flush 2 times */
52 for (i = 0; i < 2; i++) {
53 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
54 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
55 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
56 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
57 }
58 mb();
59 }
60
61 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
62 {
63 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
64
65 if (i < 0 || i > rdev->gart.num_gpu_pages) {
66 return -EINVAL;
67 }
68 addr = (lower_32_bits(addr) >> 8) |
69 ((upper_32_bits(addr) & 0xff) << 24) |
70 0xc;
71 /* on x86 we want this to be CPU endian, on powerpc
72 * on powerpc without HW swappers, it'll get swapped on way
73 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
74 writel(addr, ((void __iomem *)ptr) + (i * 4));
75 return 0;
76 }
77
78 int rv370_pcie_gart_init(struct radeon_device *rdev)
79 {
80 int r;
81
82 if (rdev->gart.table.vram.robj) {
83 WARN(1, "RV370 PCIE GART already initialized.\n");
84 return 0;
85 }
86 /* Initialize common gart structure */
87 r = radeon_gart_init(rdev);
88 if (r)
89 return r;
90 r = rv370_debugfs_pcie_gart_info_init(rdev);
91 if (r)
92 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
93 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
94 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
95 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
96 return radeon_gart_table_vram_alloc(rdev);
97 }
98
99 int rv370_pcie_gart_enable(struct radeon_device *rdev)
100 {
101 uint32_t table_addr;
102 uint32_t tmp;
103 int r;
104
105 if (rdev->gart.table.vram.robj == NULL) {
106 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
107 return -EINVAL;
108 }
109 r = radeon_gart_table_vram_pin(rdev);
110 if (r)
111 return r;
112 /* discard memory request outside of configured range */
113 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
114 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
115 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
116 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE;
117 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
118 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
119 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
120 table_addr = rdev->gart.table_addr;
121 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
122 /* FIXME: setup default page */
123 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
124 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
125 /* Clear error */
126 WREG32_PCIE(0x18, 0);
127 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
128 tmp |= RADEON_PCIE_TX_GART_EN;
129 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
130 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
131 rv370_pcie_gart_tlb_flush(rdev);
132 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
133 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
134 rdev->gart.ready = true;
135 return 0;
136 }
137
138 void rv370_pcie_gart_disable(struct radeon_device *rdev)
139 {
140 uint32_t tmp;
141
142 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
143 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
144 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
145 if (rdev->gart.table.vram.robj) {
146 radeon_object_kunmap(rdev->gart.table.vram.robj);
147 radeon_object_unpin(rdev->gart.table.vram.robj);
148 }
149 }
150
151 void rv370_pcie_gart_fini(struct radeon_device *rdev)
152 {
153 rv370_pcie_gart_disable(rdev);
154 radeon_gart_table_vram_free(rdev);
155 radeon_gart_fini(rdev);
156 }
157
158 void r300_fence_ring_emit(struct radeon_device *rdev,
159 struct radeon_fence *fence)
160 {
161 /* Who ever call radeon_fence_emit should call ring_lock and ask
162 * for enough space (today caller are ib schedule and buffer move) */
163 /* Write SC register so SC & US assert idle */
164 radeon_ring_write(rdev, PACKET0(0x43E0, 0));
165 radeon_ring_write(rdev, 0);
166 radeon_ring_write(rdev, PACKET0(0x43E4, 0));
167 radeon_ring_write(rdev, 0);
168 /* Flush 3D cache */
169 radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
170 radeon_ring_write(rdev, (2 << 0));
171 radeon_ring_write(rdev, PACKET0(0x4F18, 0));
172 radeon_ring_write(rdev, (1 << 0));
173 /* Wait until IDLE & CLEAN */
174 radeon_ring_write(rdev, PACKET0(0x1720, 0));
175 radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9));
176 /* Emit fence sequence & fire IRQ */
177 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
178 radeon_ring_write(rdev, fence->seq);
179 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
180 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
181 }
182
183 int r300_copy_dma(struct radeon_device *rdev,
184 uint64_t src_offset,
185 uint64_t dst_offset,
186 unsigned num_pages,
187 struct radeon_fence *fence)
188 {
189 uint32_t size;
190 uint32_t cur_size;
191 int i, num_loops;
192 int r = 0;
193
194 /* radeon pitch is /64 */
195 size = num_pages << PAGE_SHIFT;
196 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
197 r = radeon_ring_lock(rdev, num_loops * 4 + 64);
198 if (r) {
199 DRM_ERROR("radeon: moving bo (%d).\n", r);
200 return r;
201 }
202 /* Must wait for 2D idle & clean before DMA or hangs might happen */
203 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
204 radeon_ring_write(rdev, (1 << 16));
205 for (i = 0; i < num_loops; i++) {
206 cur_size = size;
207 if (cur_size > 0x1FFFFF) {
208 cur_size = 0x1FFFFF;
209 }
210 size -= cur_size;
211 radeon_ring_write(rdev, PACKET0(0x720, 2));
212 radeon_ring_write(rdev, src_offset);
213 radeon_ring_write(rdev, dst_offset);
214 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
215 src_offset += cur_size;
216 dst_offset += cur_size;
217 }
218 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
219 radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
220 if (fence) {
221 r = radeon_fence_emit(rdev, fence);
222 }
223 radeon_ring_unlock_commit(rdev);
224 return r;
225 }
226
227 void r300_ring_start(struct radeon_device *rdev)
228 {
229 unsigned gb_tile_config;
230 int r;
231
232 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
233 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
234 switch(rdev->num_gb_pipes) {
235 case 2:
236 gb_tile_config |= R300_PIPE_COUNT_R300;
237 break;
238 case 3:
239 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
240 break;
241 case 4:
242 gb_tile_config |= R300_PIPE_COUNT_R420;
243 break;
244 case 1:
245 default:
246 gb_tile_config |= R300_PIPE_COUNT_RV350;
247 break;
248 }
249
250 r = radeon_ring_lock(rdev, 64);
251 if (r) {
252 return;
253 }
254 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
255 radeon_ring_write(rdev,
256 RADEON_ISYNC_ANY2D_IDLE3D |
257 RADEON_ISYNC_ANY3D_IDLE2D |
258 RADEON_ISYNC_WAIT_IDLEGUI |
259 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
260 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
261 radeon_ring_write(rdev, gb_tile_config);
262 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
263 radeon_ring_write(rdev,
264 RADEON_WAIT_2D_IDLECLEAN |
265 RADEON_WAIT_3D_IDLECLEAN);
266 radeon_ring_write(rdev, PACKET0(0x170C, 0));
267 radeon_ring_write(rdev, 1 << 31);
268 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
269 radeon_ring_write(rdev, 0);
270 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
271 radeon_ring_write(rdev, 0);
272 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
273 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
274 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
275 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
276 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
277 radeon_ring_write(rdev,
278 RADEON_WAIT_2D_IDLECLEAN |
279 RADEON_WAIT_3D_IDLECLEAN);
280 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
281 radeon_ring_write(rdev, 0);
282 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
283 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
284 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
285 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
286 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
287 radeon_ring_write(rdev,
288 ((6 << R300_MS_X0_SHIFT) |
289 (6 << R300_MS_Y0_SHIFT) |
290 (6 << R300_MS_X1_SHIFT) |
291 (6 << R300_MS_Y1_SHIFT) |
292 (6 << R300_MS_X2_SHIFT) |
293 (6 << R300_MS_Y2_SHIFT) |
294 (6 << R300_MSBD0_Y_SHIFT) |
295 (6 << R300_MSBD0_X_SHIFT)));
296 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
297 radeon_ring_write(rdev,
298 ((6 << R300_MS_X3_SHIFT) |
299 (6 << R300_MS_Y3_SHIFT) |
300 (6 << R300_MS_X4_SHIFT) |
301 (6 << R300_MS_Y4_SHIFT) |
302 (6 << R300_MS_X5_SHIFT) |
303 (6 << R300_MS_Y5_SHIFT) |
304 (6 << R300_MSBD1_SHIFT)));
305 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
306 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
307 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
308 radeon_ring_write(rdev,
309 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
310 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
311 radeon_ring_write(rdev,
312 R300_GEOMETRY_ROUND_NEAREST |
313 R300_COLOR_ROUND_NEAREST);
314 radeon_ring_unlock_commit(rdev);
315 }
316
317 void r300_errata(struct radeon_device *rdev)
318 {
319 rdev->pll_errata = 0;
320
321 if (rdev->family == CHIP_R300 &&
322 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
323 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
324 }
325 }
326
327 int r300_mc_wait_for_idle(struct radeon_device *rdev)
328 {
329 unsigned i;
330 uint32_t tmp;
331
332 for (i = 0; i < rdev->usec_timeout; i++) {
333 /* read MC_STATUS */
334 tmp = RREG32(0x0150);
335 if (tmp & (1 << 4)) {
336 return 0;
337 }
338 DRM_UDELAY(1);
339 }
340 return -1;
341 }
342
343 void r300_gpu_init(struct radeon_device *rdev)
344 {
345 uint32_t gb_tile_config, tmp;
346
347 r100_hdp_reset(rdev);
348 /* FIXME: rv380 one pipes ? */
349 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
350 (rdev->family == CHIP_R350)) {
351 /* r300,r350 */
352 rdev->num_gb_pipes = 2;
353 } else {
354 /* rv350,rv370,rv380,r300 AD */
355 rdev->num_gb_pipes = 1;
356 }
357 rdev->num_z_pipes = 1;
358 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
359 switch (rdev->num_gb_pipes) {
360 case 2:
361 gb_tile_config |= R300_PIPE_COUNT_R300;
362 break;
363 case 3:
364 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
365 break;
366 case 4:
367 gb_tile_config |= R300_PIPE_COUNT_R420;
368 break;
369 default:
370 case 1:
371 gb_tile_config |= R300_PIPE_COUNT_RV350;
372 break;
373 }
374 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
375
376 if (r100_gui_wait_for_idle(rdev)) {
377 printk(KERN_WARNING "Failed to wait GUI idle while "
378 "programming pipes. Bad things might happen.\n");
379 }
380
381 tmp = RREG32(0x170C);
382 WREG32(0x170C, tmp | (1 << 31));
383
384 WREG32(R300_RB2D_DSTCACHE_MODE,
385 R300_DC_AUTOFLUSH_ENABLE |
386 R300_DC_DC_DISABLE_IGNORE_PE);
387
388 if (r100_gui_wait_for_idle(rdev)) {
389 printk(KERN_WARNING "Failed to wait GUI idle while "
390 "programming pipes. Bad things might happen.\n");
391 }
392 if (r300_mc_wait_for_idle(rdev)) {
393 printk(KERN_WARNING "Failed to wait MC idle while "
394 "programming pipes. Bad things might happen.\n");
395 }
396 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
397 rdev->num_gb_pipes, rdev->num_z_pipes);
398 }
399
400 int r300_ga_reset(struct radeon_device *rdev)
401 {
402 uint32_t tmp;
403 bool reinit_cp;
404 int i;
405
406 reinit_cp = rdev->cp.ready;
407 rdev->cp.ready = false;
408 for (i = 0; i < rdev->usec_timeout; i++) {
409 WREG32(RADEON_CP_CSQ_MODE, 0);
410 WREG32(RADEON_CP_CSQ_CNTL, 0);
411 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
412 (void)RREG32(RADEON_RBBM_SOFT_RESET);
413 udelay(200);
414 WREG32(RADEON_RBBM_SOFT_RESET, 0);
415 /* Wait to prevent race in RBBM_STATUS */
416 mdelay(1);
417 tmp = RREG32(RADEON_RBBM_STATUS);
418 if (tmp & ((1 << 20) | (1 << 26))) {
419 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
420 /* GA still busy soft reset it */
421 WREG32(0x429C, 0x200);
422 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
423 WREG32(0x43E0, 0);
424 WREG32(0x43E4, 0);
425 WREG32(0x24AC, 0);
426 }
427 /* Wait to prevent race in RBBM_STATUS */
428 mdelay(1);
429 tmp = RREG32(RADEON_RBBM_STATUS);
430 if (!(tmp & ((1 << 20) | (1 << 26)))) {
431 break;
432 }
433 }
434 for (i = 0; i < rdev->usec_timeout; i++) {
435 tmp = RREG32(RADEON_RBBM_STATUS);
436 if (!(tmp & ((1 << 20) | (1 << 26)))) {
437 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
438 tmp);
439 if (reinit_cp) {
440 return r100_cp_init(rdev, rdev->cp.ring_size);
441 }
442 return 0;
443 }
444 DRM_UDELAY(1);
445 }
446 tmp = RREG32(RADEON_RBBM_STATUS);
447 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
448 return -1;
449 }
450
451 int r300_gpu_reset(struct radeon_device *rdev)
452 {
453 uint32_t status;
454
455 /* reset order likely matter */
456 status = RREG32(RADEON_RBBM_STATUS);
457 /* reset HDP */
458 r100_hdp_reset(rdev);
459 /* reset rb2d */
460 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
461 r100_rb2d_reset(rdev);
462 }
463 /* reset GA */
464 if (status & ((1 << 20) | (1 << 26))) {
465 r300_ga_reset(rdev);
466 }
467 /* reset CP */
468 status = RREG32(RADEON_RBBM_STATUS);
469 if (status & (1 << 16)) {
470 r100_cp_reset(rdev);
471 }
472 /* Check if GPU is idle */
473 status = RREG32(RADEON_RBBM_STATUS);
474 if (status & (1 << 31)) {
475 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
476 return -1;
477 }
478 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
479 return 0;
480 }
481
482
483 /*
484 * r300,r350,rv350,rv380 VRAM info
485 */
486 void r300_vram_info(struct radeon_device *rdev)
487 {
488 uint32_t tmp;
489
490 /* DDR for all card after R300 & IGP */
491 rdev->mc.vram_is_ddr = true;
492 tmp = RREG32(RADEON_MEM_CNTL);
493 if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
494 rdev->mc.vram_width = 128;
495 } else {
496 rdev->mc.vram_width = 64;
497 }
498
499 r100_vram_init_sizes(rdev);
500 }
501
502 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
503 {
504 uint32_t link_width_cntl, mask;
505
506 if (rdev->flags & RADEON_IS_IGP)
507 return;
508
509 if (!(rdev->flags & RADEON_IS_PCIE))
510 return;
511
512 /* FIXME wait for idle */
513
514 switch (lanes) {
515 case 0:
516 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
517 break;
518 case 1:
519 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
520 break;
521 case 2:
522 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
523 break;
524 case 4:
525 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
526 break;
527 case 8:
528 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
529 break;
530 case 12:
531 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
532 break;
533 case 16:
534 default:
535 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
536 break;
537 }
538
539 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
540
541 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
542 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
543 return;
544
545 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
546 RADEON_PCIE_LC_RECONFIG_NOW |
547 RADEON_PCIE_LC_RECONFIG_LATER |
548 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
549 link_width_cntl |= mask;
550 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
551 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
552 RADEON_PCIE_LC_RECONFIG_NOW));
553
554 /* wait for lane set to complete */
555 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
556 while (link_width_cntl == 0xffffffff)
557 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
558
559 }
560
561 #if defined(CONFIG_DEBUG_FS)
562 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
563 {
564 struct drm_info_node *node = (struct drm_info_node *) m->private;
565 struct drm_device *dev = node->minor->dev;
566 struct radeon_device *rdev = dev->dev_private;
567 uint32_t tmp;
568
569 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
570 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
571 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
572 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
573 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
574 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
575 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
576 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
577 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
578 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
579 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
580 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
581 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
582 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
583 return 0;
584 }
585
586 static struct drm_info_list rv370_pcie_gart_info_list[] = {
587 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
588 };
589 #endif
590
591 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
592 {
593 #if defined(CONFIG_DEBUG_FS)
594 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
595 #else
596 return 0;
597 #endif
598 }
599
600 static int r300_packet0_check(struct radeon_cs_parser *p,
601 struct radeon_cs_packet *pkt,
602 unsigned idx, unsigned reg)
603 {
604 struct radeon_cs_reloc *reloc;
605 struct r100_cs_track *track;
606 volatile uint32_t *ib;
607 uint32_t tmp, tile_flags = 0;
608 unsigned i;
609 int r;
610 u32 idx_value;
611
612 ib = p->ib->ptr;
613 track = (struct r100_cs_track *)p->track;
614 idx_value = radeon_get_ib_value(p, idx);
615
616 switch(reg) {
617 case AVIVO_D1MODE_VLINE_START_END:
618 case RADEON_CRTC_GUI_TRIG_VLINE:
619 r = r100_cs_packet_parse_vline(p);
620 if (r) {
621 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
622 idx, reg);
623 r100_cs_dump_packet(p, pkt);
624 return r;
625 }
626 break;
627 case RADEON_DST_PITCH_OFFSET:
628 case RADEON_SRC_PITCH_OFFSET:
629 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
630 if (r)
631 return r;
632 break;
633 case R300_RB3D_COLOROFFSET0:
634 case R300_RB3D_COLOROFFSET1:
635 case R300_RB3D_COLOROFFSET2:
636 case R300_RB3D_COLOROFFSET3:
637 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
638 r = r100_cs_packet_next_reloc(p, &reloc);
639 if (r) {
640 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
641 idx, reg);
642 r100_cs_dump_packet(p, pkt);
643 return r;
644 }
645 track->cb[i].robj = reloc->robj;
646 track->cb[i].offset = idx_value;
647 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
648 break;
649 case R300_ZB_DEPTHOFFSET:
650 r = r100_cs_packet_next_reloc(p, &reloc);
651 if (r) {
652 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
653 idx, reg);
654 r100_cs_dump_packet(p, pkt);
655 return r;
656 }
657 track->zb.robj = reloc->robj;
658 track->zb.offset = idx_value;
659 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
660 break;
661 case R300_TX_OFFSET_0:
662 case R300_TX_OFFSET_0+4:
663 case R300_TX_OFFSET_0+8:
664 case R300_TX_OFFSET_0+12:
665 case R300_TX_OFFSET_0+16:
666 case R300_TX_OFFSET_0+20:
667 case R300_TX_OFFSET_0+24:
668 case R300_TX_OFFSET_0+28:
669 case R300_TX_OFFSET_0+32:
670 case R300_TX_OFFSET_0+36:
671 case R300_TX_OFFSET_0+40:
672 case R300_TX_OFFSET_0+44:
673 case R300_TX_OFFSET_0+48:
674 case R300_TX_OFFSET_0+52:
675 case R300_TX_OFFSET_0+56:
676 case R300_TX_OFFSET_0+60:
677 i = (reg - R300_TX_OFFSET_0) >> 2;
678 r = r100_cs_packet_next_reloc(p, &reloc);
679 if (r) {
680 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
681 idx, reg);
682 r100_cs_dump_packet(p, pkt);
683 return r;
684 }
685 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
686 track->textures[i].robj = reloc->robj;
687 break;
688 /* Tracked registers */
689 case 0x2084:
690 /* VAP_VF_CNTL */
691 track->vap_vf_cntl = idx_value;
692 break;
693 case 0x20B4:
694 /* VAP_VTX_SIZE */
695 track->vtx_size = idx_value & 0x7F;
696 break;
697 case 0x2134:
698 /* VAP_VF_MAX_VTX_INDX */
699 track->max_indx = idx_value & 0x00FFFFFFUL;
700 break;
701 case 0x43E4:
702 /* SC_SCISSOR1 */
703 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
704 if (p->rdev->family < CHIP_RV515) {
705 track->maxy -= 1440;
706 }
707 break;
708 case 0x4E00:
709 /* RB3D_CCTL */
710 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
711 break;
712 case 0x4E38:
713 case 0x4E3C:
714 case 0x4E40:
715 case 0x4E44:
716 /* RB3D_COLORPITCH0 */
717 /* RB3D_COLORPITCH1 */
718 /* RB3D_COLORPITCH2 */
719 /* RB3D_COLORPITCH3 */
720 r = r100_cs_packet_next_reloc(p, &reloc);
721 if (r) {
722 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
723 idx, reg);
724 r100_cs_dump_packet(p, pkt);
725 return r;
726 }
727
728 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
729 tile_flags |= R300_COLOR_TILE_ENABLE;
730 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
731 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
732
733 tmp = idx_value & ~(0x7 << 16);
734 tmp |= tile_flags;
735 ib[idx] = tmp;
736
737 i = (reg - 0x4E38) >> 2;
738 track->cb[i].pitch = idx_value & 0x3FFE;
739 switch (((idx_value >> 21) & 0xF)) {
740 case 9:
741 case 11:
742 case 12:
743 track->cb[i].cpp = 1;
744 break;
745 case 3:
746 case 4:
747 case 13:
748 case 15:
749 track->cb[i].cpp = 2;
750 break;
751 case 6:
752 track->cb[i].cpp = 4;
753 break;
754 case 10:
755 track->cb[i].cpp = 8;
756 break;
757 case 7:
758 track->cb[i].cpp = 16;
759 break;
760 default:
761 DRM_ERROR("Invalid color buffer format (%d) !\n",
762 ((idx_value >> 21) & 0xF));
763 return -EINVAL;
764 }
765 break;
766 case 0x4F00:
767 /* ZB_CNTL */
768 if (idx_value & 2) {
769 track->z_enabled = true;
770 } else {
771 track->z_enabled = false;
772 }
773 break;
774 case 0x4F10:
775 /* ZB_FORMAT */
776 switch ((idx_value & 0xF)) {
777 case 0:
778 case 1:
779 track->zb.cpp = 2;
780 break;
781 case 2:
782 track->zb.cpp = 4;
783 break;
784 default:
785 DRM_ERROR("Invalid z buffer format (%d) !\n",
786 (idx_value & 0xF));
787 return -EINVAL;
788 }
789 break;
790 case 0x4F24:
791 /* ZB_DEPTHPITCH */
792 r = r100_cs_packet_next_reloc(p, &reloc);
793 if (r) {
794 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
795 idx, reg);
796 r100_cs_dump_packet(p, pkt);
797 return r;
798 }
799
800 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
801 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
802 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
803 tile_flags |= R300_DEPTHMICROTILE_TILED;;
804
805 tmp = idx_value & ~(0x7 << 16);
806 tmp |= tile_flags;
807 ib[idx] = tmp;
808
809 track->zb.pitch = idx_value & 0x3FFC;
810 break;
811 case 0x4104:
812 for (i = 0; i < 16; i++) {
813 bool enabled;
814
815 enabled = !!(idx_value & (1 << i));
816 track->textures[i].enabled = enabled;
817 }
818 break;
819 case 0x44C0:
820 case 0x44C4:
821 case 0x44C8:
822 case 0x44CC:
823 case 0x44D0:
824 case 0x44D4:
825 case 0x44D8:
826 case 0x44DC:
827 case 0x44E0:
828 case 0x44E4:
829 case 0x44E8:
830 case 0x44EC:
831 case 0x44F0:
832 case 0x44F4:
833 case 0x44F8:
834 case 0x44FC:
835 /* TX_FORMAT1_[0-15] */
836 i = (reg - 0x44C0) >> 2;
837 tmp = (idx_value >> 25) & 0x3;
838 track->textures[i].tex_coord_type = tmp;
839 switch ((idx_value & 0x1F)) {
840 case R300_TX_FORMAT_X8:
841 case R300_TX_FORMAT_Y4X4:
842 case R300_TX_FORMAT_Z3Y3X2:
843 track->textures[i].cpp = 1;
844 break;
845 case R300_TX_FORMAT_X16:
846 case R300_TX_FORMAT_Y8X8:
847 case R300_TX_FORMAT_Z5Y6X5:
848 case R300_TX_FORMAT_Z6Y5X5:
849 case R300_TX_FORMAT_W4Z4Y4X4:
850 case R300_TX_FORMAT_W1Z5Y5X5:
851 case R300_TX_FORMAT_DXT1:
852 case R300_TX_FORMAT_D3DMFT_CxV8U8:
853 case R300_TX_FORMAT_B8G8_B8G8:
854 case R300_TX_FORMAT_G8R8_G8B8:
855 track->textures[i].cpp = 2;
856 break;
857 case R300_TX_FORMAT_Y16X16:
858 case R300_TX_FORMAT_Z11Y11X10:
859 case R300_TX_FORMAT_Z10Y11X11:
860 case R300_TX_FORMAT_W8Z8Y8X8:
861 case R300_TX_FORMAT_W2Z10Y10X10:
862 case 0x17:
863 case R300_TX_FORMAT_FL_I32:
864 case 0x1e:
865 case R300_TX_FORMAT_DXT3:
866 case R300_TX_FORMAT_DXT5:
867 track->textures[i].cpp = 4;
868 break;
869 case R300_TX_FORMAT_W16Z16Y16X16:
870 case R300_TX_FORMAT_FL_R16G16B16A16:
871 case R300_TX_FORMAT_FL_I32A32:
872 track->textures[i].cpp = 8;
873 break;
874 case R300_TX_FORMAT_FL_R32G32B32A32:
875 track->textures[i].cpp = 16;
876 break;
877 default:
878 DRM_ERROR("Invalid texture format %u\n",
879 (idx_value & 0x1F));
880 return -EINVAL;
881 break;
882 }
883 break;
884 case 0x4400:
885 case 0x4404:
886 case 0x4408:
887 case 0x440C:
888 case 0x4410:
889 case 0x4414:
890 case 0x4418:
891 case 0x441C:
892 case 0x4420:
893 case 0x4424:
894 case 0x4428:
895 case 0x442C:
896 case 0x4430:
897 case 0x4434:
898 case 0x4438:
899 case 0x443C:
900 /* TX_FILTER0_[0-15] */
901 i = (reg - 0x4400) >> 2;
902 tmp = idx_value & 0x7;
903 if (tmp == 2 || tmp == 4 || tmp == 6) {
904 track->textures[i].roundup_w = false;
905 }
906 tmp = (idx_value >> 3) & 0x7;
907 if (tmp == 2 || tmp == 4 || tmp == 6) {
908 track->textures[i].roundup_h = false;
909 }
910 break;
911 case 0x4500:
912 case 0x4504:
913 case 0x4508:
914 case 0x450C:
915 case 0x4510:
916 case 0x4514:
917 case 0x4518:
918 case 0x451C:
919 case 0x4520:
920 case 0x4524:
921 case 0x4528:
922 case 0x452C:
923 case 0x4530:
924 case 0x4534:
925 case 0x4538:
926 case 0x453C:
927 /* TX_FORMAT2_[0-15] */
928 i = (reg - 0x4500) >> 2;
929 tmp = idx_value & 0x3FFF;
930 track->textures[i].pitch = tmp + 1;
931 if (p->rdev->family >= CHIP_RV515) {
932 tmp = ((idx_value >> 15) & 1) << 11;
933 track->textures[i].width_11 = tmp;
934 tmp = ((idx_value >> 16) & 1) << 11;
935 track->textures[i].height_11 = tmp;
936 }
937 break;
938 case 0x4480:
939 case 0x4484:
940 case 0x4488:
941 case 0x448C:
942 case 0x4490:
943 case 0x4494:
944 case 0x4498:
945 case 0x449C:
946 case 0x44A0:
947 case 0x44A4:
948 case 0x44A8:
949 case 0x44AC:
950 case 0x44B0:
951 case 0x44B4:
952 case 0x44B8:
953 case 0x44BC:
954 /* TX_FORMAT0_[0-15] */
955 i = (reg - 0x4480) >> 2;
956 tmp = idx_value & 0x7FF;
957 track->textures[i].width = tmp + 1;
958 tmp = (idx_value >> 11) & 0x7FF;
959 track->textures[i].height = tmp + 1;
960 tmp = (idx_value >> 26) & 0xF;
961 track->textures[i].num_levels = tmp;
962 tmp = idx_value & (1 << 31);
963 track->textures[i].use_pitch = !!tmp;
964 tmp = (idx_value >> 22) & 0xF;
965 track->textures[i].txdepth = tmp;
966 break;
967 case R300_ZB_ZPASS_ADDR:
968 r = r100_cs_packet_next_reloc(p, &reloc);
969 if (r) {
970 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
971 idx, reg);
972 r100_cs_dump_packet(p, pkt);
973 return r;
974 }
975 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
976 break;
977 case 0x4be8:
978 /* valid register only on RV530 */
979 if (p->rdev->family == CHIP_RV530)
980 break;
981 /* fallthrough do not move */
982 default:
983 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
984 reg, idx);
985 return -EINVAL;
986 }
987 return 0;
988 }
989
990 static int r300_packet3_check(struct radeon_cs_parser *p,
991 struct radeon_cs_packet *pkt)
992 {
993 struct radeon_cs_reloc *reloc;
994 struct r100_cs_track *track;
995 volatile uint32_t *ib;
996 unsigned idx;
997 int r;
998
999 ib = p->ib->ptr;
1000 idx = pkt->idx + 1;
1001 track = (struct r100_cs_track *)p->track;
1002 switch(pkt->opcode) {
1003 case PACKET3_3D_LOAD_VBPNTR:
1004 r = r100_packet3_load_vbpntr(p, pkt, idx);
1005 if (r)
1006 return r;
1007 break;
1008 case PACKET3_INDX_BUFFER:
1009 r = r100_cs_packet_next_reloc(p, &reloc);
1010 if (r) {
1011 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1012 r100_cs_dump_packet(p, pkt);
1013 return r;
1014 }
1015 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1016 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1017 if (r) {
1018 return r;
1019 }
1020 break;
1021 /* Draw packet */
1022 case PACKET3_3D_DRAW_IMMD:
1023 /* Number of dwords is vtx_size * (num_vertices - 1)
1024 * PRIM_WALK must be equal to 3 vertex data in embedded
1025 * in cmd stream */
1026 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1027 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1028 return -EINVAL;
1029 }
1030 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1031 track->immd_dwords = pkt->count - 1;
1032 r = r100_cs_track_check(p->rdev, track);
1033 if (r) {
1034 return r;
1035 }
1036 break;
1037 case PACKET3_3D_DRAW_IMMD_2:
1038 /* Number of dwords is vtx_size * (num_vertices - 1)
1039 * PRIM_WALK must be equal to 3 vertex data in embedded
1040 * in cmd stream */
1041 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1042 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1043 return -EINVAL;
1044 }
1045 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1046 track->immd_dwords = pkt->count;
1047 r = r100_cs_track_check(p->rdev, track);
1048 if (r) {
1049 return r;
1050 }
1051 break;
1052 case PACKET3_3D_DRAW_VBUF:
1053 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1054 r = r100_cs_track_check(p->rdev, track);
1055 if (r) {
1056 return r;
1057 }
1058 break;
1059 case PACKET3_3D_DRAW_VBUF_2:
1060 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1061 r = r100_cs_track_check(p->rdev, track);
1062 if (r) {
1063 return r;
1064 }
1065 break;
1066 case PACKET3_3D_DRAW_INDX:
1067 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1068 r = r100_cs_track_check(p->rdev, track);
1069 if (r) {
1070 return r;
1071 }
1072 break;
1073 case PACKET3_3D_DRAW_INDX_2:
1074 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1075 r = r100_cs_track_check(p->rdev, track);
1076 if (r) {
1077 return r;
1078 }
1079 break;
1080 case PACKET3_NOP:
1081 break;
1082 default:
1083 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1084 return -EINVAL;
1085 }
1086 return 0;
1087 }
1088
1089 int r300_cs_parse(struct radeon_cs_parser *p)
1090 {
1091 struct radeon_cs_packet pkt;
1092 struct r100_cs_track *track;
1093 int r;
1094
1095 track = kzalloc(sizeof(*track), GFP_KERNEL);
1096 r100_cs_track_clear(p->rdev, track);
1097 p->track = track;
1098 do {
1099 r = r100_cs_packet_parse(p, &pkt, p->idx);
1100 if (r) {
1101 return r;
1102 }
1103 p->idx += pkt.count + 2;
1104 switch (pkt.type) {
1105 case PACKET_TYPE0:
1106 r = r100_cs_parse_packet0(p, &pkt,
1107 p->rdev->config.r300.reg_safe_bm,
1108 p->rdev->config.r300.reg_safe_bm_size,
1109 &r300_packet0_check);
1110 break;
1111 case PACKET_TYPE2:
1112 break;
1113 case PACKET_TYPE3:
1114 r = r300_packet3_check(p, &pkt);
1115 break;
1116 default:
1117 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1118 return -EINVAL;
1119 }
1120 if (r) {
1121 return r;
1122 }
1123 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1124 return 0;
1125 }
1126
1127 void r300_set_reg_safe(struct radeon_device *rdev)
1128 {
1129 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1130 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1131 }
1132
1133 void r300_mc_program(struct radeon_device *rdev)
1134 {
1135 struct r100_mc_save save;
1136 int r;
1137
1138 r = r100_debugfs_mc_info_init(rdev);
1139 if (r) {
1140 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1141 }
1142
1143 /* Stops all mc clients */
1144 r100_mc_stop(rdev, &save);
1145 if (rdev->flags & RADEON_IS_AGP) {
1146 WREG32(R_00014C_MC_AGP_LOCATION,
1147 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1148 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1149 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1150 WREG32(R_00015C_AGP_BASE_2,
1151 upper_32_bits(rdev->mc.agp_base) & 0xff);
1152 } else {
1153 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1154 WREG32(R_000170_AGP_BASE, 0);
1155 WREG32(R_00015C_AGP_BASE_2, 0);
1156 }
1157 /* Wait for mc idle */
1158 if (r300_mc_wait_for_idle(rdev))
1159 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1160 /* Program MC, should be a 32bits limited address space */
1161 WREG32(R_000148_MC_FB_LOCATION,
1162 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1163 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1164 r100_mc_resume(rdev, &save);
1165 }
1166
1167 void r300_clock_startup(struct radeon_device *rdev)
1168 {
1169 u32 tmp;
1170
1171 if (radeon_dynclks != -1 && radeon_dynclks)
1172 radeon_legacy_set_clock_gating(rdev, 1);
1173 /* We need to force on some of the block */
1174 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1175 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1176 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1177 tmp |= S_00000D_FORCE_VAP(1);
1178 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1179 }
1180
1181 static int r300_startup(struct radeon_device *rdev)
1182 {
1183 int r;
1184
1185 r300_mc_program(rdev);
1186 /* Resume clock */
1187 r300_clock_startup(rdev);
1188 /* Initialize GPU configuration (# pipes, ...) */
1189 r300_gpu_init(rdev);
1190 /* Initialize GART (initialize after TTM so we can allocate
1191 * memory through TTM but finalize after TTM) */
1192 if (rdev->flags & RADEON_IS_PCIE) {
1193 r = rv370_pcie_gart_enable(rdev);
1194 if (r)
1195 return r;
1196 }
1197 if (rdev->flags & RADEON_IS_PCI) {
1198 r = r100_pci_gart_enable(rdev);
1199 if (r)
1200 return r;
1201 }
1202 /* Enable IRQ */
1203 rdev->irq.sw_int = true;
1204 r100_irq_set(rdev);
1205 /* 1M ring buffer */
1206 r = r100_cp_init(rdev, 1024 * 1024);
1207 if (r) {
1208 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1209 return r;
1210 }
1211 r = r100_wb_init(rdev);
1212 if (r)
1213 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1214 r = r100_ib_init(rdev);
1215 if (r) {
1216 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1217 return r;
1218 }
1219 return 0;
1220 }
1221
1222 int r300_resume(struct radeon_device *rdev)
1223 {
1224 /* Make sur GART are not working */
1225 if (rdev->flags & RADEON_IS_PCIE)
1226 rv370_pcie_gart_disable(rdev);
1227 if (rdev->flags & RADEON_IS_PCI)
1228 r100_pci_gart_disable(rdev);
1229 /* Resume clock before doing reset */
1230 r300_clock_startup(rdev);
1231 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1232 if (radeon_gpu_reset(rdev)) {
1233 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1234 RREG32(R_000E40_RBBM_STATUS),
1235 RREG32(R_0007C0_CP_STAT));
1236 }
1237 /* post */
1238 radeon_combios_asic_init(rdev->ddev);
1239 /* Resume clock after posting */
1240 r300_clock_startup(rdev);
1241 return r300_startup(rdev);
1242 }
1243
1244 int r300_suspend(struct radeon_device *rdev)
1245 {
1246 r100_cp_disable(rdev);
1247 r100_wb_disable(rdev);
1248 r100_irq_disable(rdev);
1249 if (rdev->flags & RADEON_IS_PCIE)
1250 rv370_pcie_gart_disable(rdev);
1251 if (rdev->flags & RADEON_IS_PCI)
1252 r100_pci_gart_disable(rdev);
1253 return 0;
1254 }
1255
1256 void r300_fini(struct radeon_device *rdev)
1257 {
1258 r300_suspend(rdev);
1259 r100_cp_fini(rdev);
1260 r100_wb_fini(rdev);
1261 r100_ib_fini(rdev);
1262 radeon_gem_fini(rdev);
1263 if (rdev->flags & RADEON_IS_PCIE)
1264 rv370_pcie_gart_fini(rdev);
1265 if (rdev->flags & RADEON_IS_PCI)
1266 r100_pci_gart_fini(rdev);
1267 radeon_irq_kms_fini(rdev);
1268 radeon_fence_driver_fini(rdev);
1269 radeon_object_fini(rdev);
1270 radeon_atombios_fini(rdev);
1271 kfree(rdev->bios);
1272 rdev->bios = NULL;
1273 }
1274
1275 int r300_init(struct radeon_device *rdev)
1276 {
1277 int r;
1278
1279 /* Disable VGA */
1280 r100_vga_render_disable(rdev);
1281 /* Initialize scratch registers */
1282 radeon_scratch_init(rdev);
1283 /* Initialize surface registers */
1284 radeon_surface_init(rdev);
1285 /* TODO: disable VGA need to use VGA request */
1286 /* BIOS*/
1287 if (!radeon_get_bios(rdev)) {
1288 if (ASIC_IS_AVIVO(rdev))
1289 return -EINVAL;
1290 }
1291 if (rdev->is_atom_bios) {
1292 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1293 return -EINVAL;
1294 } else {
1295 r = radeon_combios_init(rdev);
1296 if (r)
1297 return r;
1298 }
1299 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1300 if (radeon_gpu_reset(rdev)) {
1301 dev_warn(rdev->dev,
1302 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1303 RREG32(R_000E40_RBBM_STATUS),
1304 RREG32(R_0007C0_CP_STAT));
1305 }
1306 /* check if cards are posted or not */
1307 if (!radeon_card_posted(rdev) && rdev->bios) {
1308 DRM_INFO("GPU not posted. posting now...\n");
1309 radeon_combios_asic_init(rdev->ddev);
1310 }
1311 /* Set asic errata */
1312 r300_errata(rdev);
1313 /* Initialize clocks */
1314 radeon_get_clock_info(rdev->ddev);
1315 /* Get vram informations */
1316 r300_vram_info(rdev);
1317 /* Initialize memory controller (also test AGP) */
1318 r = r420_mc_init(rdev);
1319 if (r)
1320 return r;
1321 /* Fence driver */
1322 r = radeon_fence_driver_init(rdev);
1323 if (r)
1324 return r;
1325 r = radeon_irq_kms_init(rdev);
1326 if (r)
1327 return r;
1328 /* Memory manager */
1329 r = radeon_object_init(rdev);
1330 if (r)
1331 return r;
1332 if (rdev->flags & RADEON_IS_PCIE) {
1333 r = rv370_pcie_gart_init(rdev);
1334 if (r)
1335 return r;
1336 }
1337 if (rdev->flags & RADEON_IS_PCI) {
1338 r = r100_pci_gart_init(rdev);
1339 if (r)
1340 return r;
1341 }
1342 r300_set_reg_safe(rdev);
1343 rdev->accel_working = true;
1344 r = r300_startup(rdev);
1345 if (r) {
1346 /* Somethings want wront with the accel init stop accel */
1347 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1348 r300_suspend(rdev);
1349 r100_cp_fini(rdev);
1350 r100_wb_fini(rdev);
1351 r100_ib_fini(rdev);
1352 if (rdev->flags & RADEON_IS_PCIE)
1353 rv370_pcie_gart_fini(rdev);
1354 if (rdev->flags & RADEON_IS_PCI)
1355 r100_pci_gart_fini(rdev);
1356 radeon_irq_kms_fini(rdev);
1357 rdev->accel_working = false;
1358 }
1359 return 0;
1360 }
Linux MOXA ART SoC ARM port