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init from v2.6.32.60
[mach-moxart.git] / drivers / gpu / drm / radeon / radeon_legacy_crtc.c
blob7547ec6418bb5edd53608fdabd155848c302eec6
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
30 #include "radeon.h"
31 #include "atom.h"
32
33 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
34 struct drm_display_mode *mode,
35 struct drm_display_mode *adjusted_mode)
36 {
37 struct drm_device *dev = crtc->dev;
38 struct radeon_device *rdev = dev->dev_private;
39 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40 int xres = mode->hdisplay;
41 int yres = mode->vdisplay;
42 bool hscale = true, vscale = true;
43 int hsync_wid;
44 int vsync_wid;
45 int hsync_start;
46 int blank_width;
47 u32 scale, inc, crtc_more_cntl;
48 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
49 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
50 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
51 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
52
53 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
54 (RADEON_VERT_STRETCH_RESERVED |
55 RADEON_VERT_AUTO_RATIO_INC);
56 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
57 (RADEON_HORZ_FP_LOOP_STRETCH |
58 RADEON_HORZ_AUTO_RATIO_INC);
59
60 crtc_more_cntl = 0;
61 if ((rdev->family == CHIP_RS100) ||
62 (rdev->family == CHIP_RS200)) {
63 /* This is to workaround the asic bug for RMX, some versions
64 of BIOS dosen't have this register initialized correctly. */
65 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
66 }
67
68
69 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
70 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
71
72 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
73 if (!hsync_wid)
74 hsync_wid = 1;
75 hsync_start = mode->crtc_hsync_start - 8;
76
77 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
78 | ((hsync_wid & 0x3f) << 16)
79 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
80 ? RADEON_CRTC_H_SYNC_POL
81 : 0));
82
83 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
84 | ((mode->crtc_vdisplay - 1) << 16));
85
86 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
87 if (!vsync_wid)
88 vsync_wid = 1;
89
90 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
91 | ((vsync_wid & 0x1f) << 16)
92 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
93 ? RADEON_CRTC_V_SYNC_POL
94 : 0));
95
96 fp_horz_vert_active = 0;
97
98 if (native_mode->hdisplay == 0 ||
99 native_mode->vdisplay == 0) {
100 hscale = false;
101 vscale = false;
102 } else {
103 if (xres > native_mode->hdisplay)
104 xres = native_mode->hdisplay;
105 if (yres > native_mode->vdisplay)
106 yres = native_mode->vdisplay;
107
108 if (xres == native_mode->hdisplay)
109 hscale = false;
110 if (yres == native_mode->vdisplay)
111 vscale = false;
112 }
113
114 switch (radeon_crtc->rmx_type) {
115 case RMX_FULL:
116 case RMX_ASPECT:
117 if (!hscale)
118 fp_horz_stretch |= ((xres/8-1) << 16);
119 else {
120 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
121 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
122 / native_mode->hdisplay + 1;
123 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
124 RADEON_HORZ_STRETCH_BLEND |
125 RADEON_HORZ_STRETCH_ENABLE |
126 ((native_mode->hdisplay/8-1) << 16));
127 }
128
129 if (!vscale)
130 fp_vert_stretch |= ((yres-1) << 12);
131 else {
132 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
133 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
134 / native_mode->vdisplay + 1;
135 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
136 RADEON_VERT_STRETCH_ENABLE |
137 RADEON_VERT_STRETCH_BLEND |
138 ((native_mode->vdisplay-1) << 12));
139 }
140 break;
141 case RMX_CENTER:
142 fp_horz_stretch |= ((xres/8-1) << 16);
143 fp_vert_stretch |= ((yres-1) << 12);
144
145 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
146 RADEON_CRTC_AUTO_VERT_CENTER_EN);
147
148 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
149 if (blank_width > 110)
150 blank_width = 110;
151
152 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
153 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
154
155 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
156 if (!hsync_wid)
157 hsync_wid = 1;
158
159 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
160 | ((hsync_wid & 0x3f) << 16)
161 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
162 ? RADEON_CRTC_H_SYNC_POL
163 : 0));
164
165 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
166 | ((mode->crtc_vdisplay - 1) << 16));
167
168 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
169 if (!vsync_wid)
170 vsync_wid = 1;
171
172 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
173 | ((vsync_wid & 0x1f) << 16)
174 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
175 ? RADEON_CRTC_V_SYNC_POL
176 : 0)));
177
178 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
179 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
180 break;
181 case RMX_OFF:
182 default:
183 fp_horz_stretch |= ((xres/8-1) << 16);
184 fp_vert_stretch |= ((yres-1) << 12);
185 break;
186 }
187
188 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
189 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
190 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
191 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
192 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
193 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
194 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
195 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
196 }
197
198 void radeon_restore_common_regs(struct drm_device *dev)
199 {
200 /* don't need this yet */
201 }
202
203 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
204 {
205 struct radeon_device *rdev = dev->dev_private;
206 int i = 0;
207
208 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
209 the cause yet, but this workaround will mask the problem for now.
210 Other chips usually will pass at the very first test, so the
211 workaround shouldn't have any effect on them. */
212 for (i = 0;
213 (i < 10000 &&
214 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
215 i++);
216 }
217
218 static void radeon_pll_write_update(struct drm_device *dev)
219 {
220 struct radeon_device *rdev = dev->dev_private;
221
222 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
223
224 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
225 RADEON_PPLL_ATOMIC_UPDATE_W,
226 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
227 }
228
229 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
230 {
231 struct radeon_device *rdev = dev->dev_private;
232 int i = 0;
233
234
235 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
236 the cause yet, but this workaround will mask the problem for now.
237 Other chips usually will pass at the very first test, so the
238 workaround shouldn't have any effect on them. */
239 for (i = 0;
240 (i < 10000 &&
241 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
242 i++);
243 }
244
245 static void radeon_pll2_write_update(struct drm_device *dev)
246 {
247 struct radeon_device *rdev = dev->dev_private;
248
249 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
250
251 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
252 RADEON_P2PLL_ATOMIC_UPDATE_W,
253 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
254 }
255
256 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
257 uint16_t fb_div)
258 {
259 unsigned int vcoFreq;
260
261 if (!ref_div)
262 return 1;
263
264 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
265
266 /*
267 * This is horribly crude: the VCO frequency range is divided into
268 * 3 parts, each part having a fixed PLL gain value.
269 */
270 if (vcoFreq >= 30000)
271 /*
272 * [300..max] MHz : 7
273 */
274 return 7;
275 else if (vcoFreq >= 18000)
276 /*
277 * [180..300) MHz : 4
278 */
279 return 4;
280 else
281 /*
282 * [0..180) MHz : 1
283 */
284 return 1;
285 }
286
287 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
288 {
289 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
290 struct drm_device *dev = crtc->dev;
291 struct radeon_device *rdev = dev->dev_private;
292 uint32_t mask;
293
294 if (radeon_crtc->crtc_id)
295 mask = (RADEON_CRTC2_DISP_DIS |
296 RADEON_CRTC2_VSYNC_DIS |
297 RADEON_CRTC2_HSYNC_DIS |
298 RADEON_CRTC2_DISP_REQ_EN_B);
299 else
300 mask = (RADEON_CRTC_DISPLAY_DIS |
301 RADEON_CRTC_VSYNC_DIS |
302 RADEON_CRTC_HSYNC_DIS);
303
304 switch (mode) {
305 case DRM_MODE_DPMS_ON:
306 if (radeon_crtc->crtc_id)
307 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
308 else {
309 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
310 RADEON_CRTC_DISP_REQ_EN_B));
311 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
312 }
313 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
314 radeon_crtc_load_lut(crtc);
315 break;
316 case DRM_MODE_DPMS_STANDBY:
317 case DRM_MODE_DPMS_SUSPEND:
318 case DRM_MODE_DPMS_OFF:
319 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
320 if (radeon_crtc->crtc_id)
321 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
322 else {
323 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
324 RADEON_CRTC_DISP_REQ_EN_B));
325 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
326 }
327 break;
328 }
329 }
330
331 /* properly set crtc bpp when using atombios */
332 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
333 {
334 struct drm_device *dev = crtc->dev;
335 struct radeon_device *rdev = dev->dev_private;
336 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
337 int format;
338 uint32_t crtc_gen_cntl;
339 uint32_t disp_merge_cntl;
340 uint32_t crtc_pitch;
341
342 switch (crtc->fb->bits_per_pixel) {
343 case 8:
344 format = 2;
345 break;
346 case 15: /* 555 */
347 format = 3;
348 break;
349 case 16: /* 565 */
350 format = 4;
351 break;
352 case 24: /* RGB */
353 format = 5;
354 break;
355 case 32: /* xRGB */
356 format = 6;
357 break;
358 default:
359 return;
360 }
361
362 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
363 ((crtc->fb->bits_per_pixel * 8) - 1)) /
364 (crtc->fb->bits_per_pixel * 8));
365 crtc_pitch |= crtc_pitch << 16;
366
367 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
368
369 switch (radeon_crtc->crtc_id) {
370 case 0:
371 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
372 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
373 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
374
375 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
376 crtc_gen_cntl |= (format << 8);
377 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
378 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
379 break;
380 case 1:
381 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
382 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
383 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
384
385 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
386 crtc_gen_cntl |= (format << 8);
387 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
388 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
389 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
390 break;
391 }
392 }
393
394 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
395 struct drm_framebuffer *old_fb)
396 {
397 struct drm_device *dev = crtc->dev;
398 struct radeon_device *rdev = dev->dev_private;
399 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
400 struct radeon_framebuffer *radeon_fb;
401 struct drm_gem_object *obj;
402 uint64_t base;
403 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
404 uint32_t crtc_pitch, pitch_pixels;
405 uint32_t tiling_flags;
406 int format;
407 uint32_t gen_cntl_reg, gen_cntl_val;
408
409 DRM_DEBUG("\n");
410
411 radeon_fb = to_radeon_framebuffer(crtc->fb);
412
413 switch (crtc->fb->bits_per_pixel) {
414 case 8:
415 format = 2;
416 break;
417 case 15: /* 555 */
418 format = 3;
419 break;
420 case 16: /* 565 */
421 format = 4;
422 break;
423 case 24: /* RGB */
424 format = 5;
425 break;
426 case 32: /* xRGB */
427 format = 6;
428 break;
429 default:
430 return false;
431 }
432
433 obj = radeon_fb->obj;
434 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
435 return -EINVAL;
436 }
437 /* if scanout was in GTT this really wouldn't work */
438 /* crtc offset is from display base addr not FB location */
439 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
440
441 base -= radeon_crtc->legacy_display_base_addr;
442
443 crtc_offset_cntl = 0;
444
445 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
446 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
447 ((crtc->fb->bits_per_pixel * 8) - 1)) /
448 (crtc->fb->bits_per_pixel * 8));
449 crtc_pitch |= crtc_pitch << 16;
450
451 radeon_object_get_tiling_flags(obj->driver_private,
452 &tiling_flags, NULL);
453 if (tiling_flags & RADEON_TILING_MICRO)
454 DRM_ERROR("trying to scanout microtiled buffer\n");
455
456 if (tiling_flags & RADEON_TILING_MACRO) {
457 if (ASIC_IS_R300(rdev))
458 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
459 R300_CRTC_MICRO_TILE_BUFFER_DIS |
460 R300_CRTC_MACRO_TILE_EN);
461 else
462 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
463 } else {
464 if (ASIC_IS_R300(rdev))
465 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
466 R300_CRTC_MICRO_TILE_BUFFER_DIS |
467 R300_CRTC_MACRO_TILE_EN);
468 else
469 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
470 }
471
472 if (tiling_flags & RADEON_TILING_MACRO) {
473 if (ASIC_IS_R300(rdev)) {
474 crtc_tile_x0_y0 = x | (y << 16);
475 base &= ~0x7ff;
476 } else {
477 int byteshift = crtc->fb->bits_per_pixel >> 4;
478 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
479 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
480 crtc_offset_cntl |= (y % 16);
481 }
482 } else {
483 int offset = y * pitch_pixels + x;
484 switch (crtc->fb->bits_per_pixel) {
485 case 8:
486 offset *= 1;
487 break;
488 case 15:
489 case 16:
490 offset *= 2;
491 break;
492 case 24:
493 offset *= 3;
494 break;
495 case 32:
496 offset *= 4;
497 break;
498 default:
499 return false;
500 }
501 base += offset;
502 }
503
504 base &= ~7;
505
506 if (radeon_crtc->crtc_id == 1)
507 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
508 else
509 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
510
511 gen_cntl_val = RREG32(gen_cntl_reg);
512 gen_cntl_val &= ~(0xf << 8);
513 gen_cntl_val |= (format << 8);
514 WREG32(gen_cntl_reg, gen_cntl_val);
515
516 crtc_offset = (u32)base;
517
518 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
519
520 if (ASIC_IS_R300(rdev)) {
521 if (radeon_crtc->crtc_id)
522 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
523 else
524 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
525 }
526 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
527 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
528 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
529
530 if (old_fb && old_fb != crtc->fb) {
531 radeon_fb = to_radeon_framebuffer(old_fb);
532 radeon_gem_object_unpin(radeon_fb->obj);
533 }
534
535 /* Bytes per pixel may have changed */
536 radeon_bandwidth_update(rdev);
537
538 return 0;
539 }
540
541 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
542 {
543 struct drm_device *dev = crtc->dev;
544 struct radeon_device *rdev = dev->dev_private;
545 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
546 struct drm_encoder *encoder;
547 int format;
548 int hsync_start;
549 int hsync_wid;
550 int vsync_wid;
551 uint32_t crtc_h_total_disp;
552 uint32_t crtc_h_sync_strt_wid;
553 uint32_t crtc_v_total_disp;
554 uint32_t crtc_v_sync_strt_wid;
555 bool is_tv = false;
556
557 DRM_DEBUG("\n");
558 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
559 if (encoder->crtc == crtc) {
560 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
561 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
562 is_tv = true;
563 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
564 break;
565 }
566 }
567 }
568
569 switch (crtc->fb->bits_per_pixel) {
570 case 8:
571 format = 2;
572 break;
573 case 15: /* 555 */
574 format = 3;
575 break;
576 case 16: /* 565 */
577 format = 4;
578 break;
579 case 24: /* RGB */
580 format = 5;
581 break;
582 case 32: /* xRGB */
583 format = 6;
584 break;
585 default:
586 return false;
587 }
588
589 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
590 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
591
592 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
593 if (!hsync_wid)
594 hsync_wid = 1;
595 hsync_start = mode->crtc_hsync_start - 8;
596
597 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
598 | ((hsync_wid & 0x3f) << 16)
599 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
600 ? RADEON_CRTC_H_SYNC_POL
601 : 0));
602
603 /* This works for double scan mode. */
604 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
605 | ((mode->crtc_vdisplay - 1) << 16));
606
607 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
608 if (!vsync_wid)
609 vsync_wid = 1;
610
611 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
612 | ((vsync_wid & 0x1f) << 16)
613 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
614 ? RADEON_CRTC_V_SYNC_POL
615 : 0));
616
617 /* TODO -> Dell Server */
618 if (0) {
619 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
620 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
621 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
622 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
623
624 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
625 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
626
627 /* For CRT on DAC2, don't turn it on if BIOS didn't
628 enable it, even it's detected.
629 */
630 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
631 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
632 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
633
634 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
635 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
636 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
637 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
638 }
639
640 if (radeon_crtc->crtc_id) {
641 uint32_t crtc2_gen_cntl;
642 uint32_t disp2_merge_cntl;
643
644 /* check to see if TV DAC is enabled for another crtc and keep it enabled */
645 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
646 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
647 else
648 crtc2_gen_cntl = 0;
649
650 crtc2_gen_cntl |= ((format << 8)
651 | RADEON_CRTC2_VSYNC_DIS
652 | RADEON_CRTC2_HSYNC_DIS
653 | RADEON_CRTC2_DISP_DIS
654 | RADEON_CRTC2_DISP_REQ_EN_B
655 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
656 ? RADEON_CRTC2_DBL_SCAN_EN
657 : 0)
658 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
659 ? RADEON_CRTC2_CSYNC_EN
660 : 0)
661 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
662 ? RADEON_CRTC2_INTERLACE_EN
663 : 0));
664
665 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
666 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
667
668 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
669 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
670
671 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
672 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
673 } else {
674 uint32_t crtc_gen_cntl;
675 uint32_t crtc_ext_cntl;
676 uint32_t disp_merge_cntl;
677
678 crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
679 | (format << 8)
680 | RADEON_CRTC_DISP_REQ_EN_B
681 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
682 ? RADEON_CRTC_DBL_SCAN_EN
683 : 0)
684 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
685 ? RADEON_CRTC_CSYNC_EN
686 : 0)
687 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
688 ? RADEON_CRTC_INTERLACE_EN
689 : 0));
690
691 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
692 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
693 RADEON_CRTC_VSYNC_DIS |
694 RADEON_CRTC_HSYNC_DIS |
695 RADEON_CRTC_DISPLAY_DIS);
696
697 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
698 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
699
700 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
701 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
702 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
703 }
704
705 if (is_tv)
706 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
707 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
708 &crtc_v_sync_strt_wid);
709
710 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
711 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
712 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
713 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
714
715 return true;
716 }
717
718 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
719 {
720 struct drm_device *dev = crtc->dev;
721 struct radeon_device *rdev = dev->dev_private;
722 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
723 struct drm_encoder *encoder;
724 uint32_t feedback_div = 0;
725 uint32_t frac_fb_div = 0;
726 uint32_t reference_div = 0;
727 uint32_t post_divider = 0;
728 uint32_t freq = 0;
729 uint8_t pll_gain;
730 int pll_flags = RADEON_PLL_LEGACY;
731 bool use_bios_divs = false;
732 /* PLL registers */
733 uint32_t pll_ref_div = 0;
734 uint32_t pll_fb_post_div = 0;
735 uint32_t htotal_cntl = 0;
736 bool is_tv = false;
737 struct radeon_pll *pll;
738
739 struct {
740 int divider;
741 int bitvalue;
742 } *post_div, post_divs[] = {
743 /* From RAGE 128 VR/RAGE 128 GL Register
744 * Reference Manual (Technical Reference
745 * Manual P/N RRG-G04100-C Rev. 0.04), page
746 * 3-17 (PLL_DIV_[3:0]).
747 */
748 { 1, 0 }, /* VCLK_SRC */
749 { 2, 1 }, /* VCLK_SRC/2 */
750 { 4, 2 }, /* VCLK_SRC/4 */
751 { 8, 3 }, /* VCLK_SRC/8 */
752 { 3, 4 }, /* VCLK_SRC/3 */
753 { 16, 5 }, /* VCLK_SRC/16 */
754 { 6, 6 }, /* VCLK_SRC/6 */
755 { 12, 7 }, /* VCLK_SRC/12 */
756 { 0, 0 }
757 };
758
759 if (radeon_crtc->crtc_id)
760 pll = &rdev->clock.p2pll;
761 else
762 pll = &rdev->clock.p1pll;
763
764 if (mode->clock > 200000) /* range limits??? */
765 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
766 else
767 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
768
769 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
770 if (encoder->crtc == crtc) {
771 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
772
773 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
774 is_tv = true;
775 break;
776 }
777
778 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
779 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
780 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
781 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
782 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
783 if (lvds) {
784 if (lvds->use_bios_dividers) {
785 pll_ref_div = lvds->panel_ref_divider;
786 pll_fb_post_div = (lvds->panel_fb_divider |
787 (lvds->panel_post_divider << 16));
788 htotal_cntl = 0;
789 use_bios_divs = true;
790 }
791 }
792 pll_flags |= RADEON_PLL_USE_REF_DIV;
793 }
794 }
795 }
796
797 DRM_DEBUG("\n");
798
799 if (!use_bios_divs) {
800 radeon_compute_pll(pll, mode->clock,
801 &freq, &feedback_div, &frac_fb_div,
802 &reference_div, &post_divider,
803 pll_flags);
804
805 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
806 if (post_div->divider == post_divider)
807 break;
808 }
809
810 if (!post_div->divider)
811 post_div = &post_divs[0];
812
813 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
814 (unsigned)freq,
815 feedback_div,
816 reference_div,
817 post_divider);
818
819 pll_ref_div = reference_div;
820 #if defined(__powerpc__) && (0) /* TODO */
821 /* apparently programming this otherwise causes a hang??? */
822 if (info->MacModel == RADEON_MAC_IBOOK)
823 pll_fb_post_div = 0x000600ad;
824 else
825 #endif
826 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
827
828 htotal_cntl = mode->htotal & 0x7;
829
830 }
831
832 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
833 pll_ref_div & 0x3ff,
834 pll_fb_post_div & 0x7ff);
835
836 if (radeon_crtc->crtc_id) {
837 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
838 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
839 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
840
841 if (is_tv) {
842 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
843 &pll_ref_div, &pll_fb_post_div,
844 &pixclks_cntl);
845 }
846
847 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
848 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
849 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
850
851 WREG32_PLL_P(RADEON_P2PLL_CNTL,
852 RADEON_P2PLL_RESET
853 | RADEON_P2PLL_ATOMIC_UPDATE_EN
854 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
855 ~(RADEON_P2PLL_RESET
856 | RADEON_P2PLL_ATOMIC_UPDATE_EN
857 | RADEON_P2PLL_PVG_MASK));
858
859 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
860 pll_ref_div,
861 ~RADEON_P2PLL_REF_DIV_MASK);
862
863 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
864 pll_fb_post_div,
865 ~RADEON_P2PLL_FB0_DIV_MASK);
866
867 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
868 pll_fb_post_div,
869 ~RADEON_P2PLL_POST0_DIV_MASK);
870
871 radeon_pll2_write_update(dev);
872 radeon_pll2_wait_for_read_update_complete(dev);
873
874 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
875
876 WREG32_PLL_P(RADEON_P2PLL_CNTL,
877 0,
878 ~(RADEON_P2PLL_RESET
879 | RADEON_P2PLL_SLEEP
880 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
881
882 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
883 (unsigned)pll_ref_div,
884 (unsigned)pll_fb_post_div,
885 (unsigned)htotal_cntl,
886 RREG32_PLL(RADEON_P2PLL_CNTL));
887 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
888 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
889 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
890 (unsigned)((pll_fb_post_div &
891 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
892
893 mdelay(50); /* Let the clock to lock */
894
895 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
896 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
897 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
898
899 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
900 } else {
901 uint32_t pixclks_cntl;
902
903
904 if (is_tv) {
905 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
906 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
907 &pll_fb_post_div, &pixclks_cntl);
908 }
909
910 if (rdev->flags & RADEON_IS_MOBILITY) {
911 /* A temporal workaround for the occational blanking on certain laptop panels.
912 This appears to related to the PLL divider registers (fail to lock?).
913 It occurs even when all dividers are the same with their old settings.
914 In this case we really don't need to fiddle with PLL registers.
915 By doing this we can avoid the blanking problem with some panels.
916 */
917 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
918 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
919 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
920 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
921 RADEON_PLL_DIV_SEL,
922 ~(RADEON_PLL_DIV_SEL));
923 r100_pll_errata_after_index(rdev);
924 return;
925 }
926 }
927
928 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
929 RADEON_VCLK_SRC_SEL_CPUCLK,
930 ~(RADEON_VCLK_SRC_SEL_MASK));
931 WREG32_PLL_P(RADEON_PPLL_CNTL,
932 RADEON_PPLL_RESET
933 | RADEON_PPLL_ATOMIC_UPDATE_EN
934 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
935 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
936 ~(RADEON_PPLL_RESET
937 | RADEON_PPLL_ATOMIC_UPDATE_EN
938 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
939 | RADEON_PPLL_PVG_MASK));
940
941 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
942 RADEON_PLL_DIV_SEL,
943 ~(RADEON_PLL_DIV_SEL));
944 r100_pll_errata_after_index(rdev);
945
946 if (ASIC_IS_R300(rdev) ||
947 (rdev->family == CHIP_RS300) ||
948 (rdev->family == CHIP_RS400) ||
949 (rdev->family == CHIP_RS480)) {
950 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
951 /* When restoring console mode, use saved PPLL_REF_DIV
952 * setting.
953 */
954 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
955 pll_ref_div,
956 0);
957 } else {
958 /* R300 uses ref_div_acc field as real ref divider */
959 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
960 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
961 ~R300_PPLL_REF_DIV_ACC_MASK);
962 }
963 } else
964 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
965 pll_ref_div,
966 ~RADEON_PPLL_REF_DIV_MASK);
967
968 WREG32_PLL_P(RADEON_PPLL_DIV_3,
969 pll_fb_post_div,
970 ~RADEON_PPLL_FB3_DIV_MASK);
971
972 WREG32_PLL_P(RADEON_PPLL_DIV_3,
973 pll_fb_post_div,
974 ~RADEON_PPLL_POST3_DIV_MASK);
975
976 radeon_pll_write_update(dev);
977 radeon_pll_wait_for_read_update_complete(dev);
978
979 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
980
981 WREG32_PLL_P(RADEON_PPLL_CNTL,
982 0,
983 ~(RADEON_PPLL_RESET
984 | RADEON_PPLL_SLEEP
985 | RADEON_PPLL_ATOMIC_UPDATE_EN
986 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
987
988 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
989 pll_ref_div,
990 pll_fb_post_div,
991 (unsigned)htotal_cntl,
992 RREG32_PLL(RADEON_PPLL_CNTL));
993 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
994 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
995 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
996 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
997
998 mdelay(50); /* Let the clock to lock */
999
1000 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1001 RADEON_VCLK_SRC_SEL_PPLLCLK,
1002 ~(RADEON_VCLK_SRC_SEL_MASK));
1003
1004 if (is_tv)
1005 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1006 }
1007 }
1008
1009 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1010 struct drm_display_mode *mode,
1011 struct drm_display_mode *adjusted_mode)
1012 {
1013 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1014 return false;
1015 return true;
1016 }
1017
1018 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1019 struct drm_display_mode *mode,
1020 struct drm_display_mode *adjusted_mode,
1021 int x, int y, struct drm_framebuffer *old_fb)
1022 {
1023 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1024
1025 /* TODO TV */
1026 radeon_crtc_set_base(crtc, x, y, old_fb);
1027 radeon_set_crtc_timing(crtc, adjusted_mode);
1028 radeon_set_pll(crtc, adjusted_mode);
1029 if (radeon_crtc->crtc_id == 0) {
1030 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
1031 } else {
1032 if (radeon_crtc->rmx_type != RMX_OFF) {
1033 /* FIXME: only first crtc has rmx what should we
1034 * do ?
1035 */
1036 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1037 }
1038 }
1039 return 0;
1040 }
1041
1042 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1043 {
1044 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1045 }
1046
1047 static void radeon_crtc_commit(struct drm_crtc *crtc)
1048 {
1049 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1050 }
1051
1052 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1053 .dpms = radeon_crtc_dpms,
1054 .mode_fixup = radeon_crtc_mode_fixup,
1055 .mode_set = radeon_crtc_mode_set,
1056 .mode_set_base = radeon_crtc_set_base,
1057 .prepare = radeon_crtc_prepare,
1058 .commit = radeon_crtc_commit,
1059 .load_lut = radeon_crtc_load_lut,
1060 };
1061
1062
1063 void radeon_legacy_init_crtc(struct drm_device *dev,
1064 struct radeon_crtc *radeon_crtc)
1065 {
1066 if (radeon_crtc->crtc_id == 1)
1067 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1068 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1069 }
Linux MOXA ART SoC ARM port