drivers/net/benet/be.h

   1 /*
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 #ifndef BE_H
  19 #define BE_H
  20
  21 #include <linux/pci.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/version.h>
  24 #include <linux/delay.h>
  25 #include <net/tcp.h>
  26 #include <net/ip.h>
  27 #include <net/ipv6.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/firmware.h>
  32
  33 #include "be_hw.h"
  34
  35 #define DRV_VER                 "2.101.205"
  36 #define DRV_NAME                "be2net"
  37 #define BE_NAME                 "ServerEngines BladeEngine2 10Gbps NIC"
  38 #define BE3_NAME                "ServerEngines BladeEngine3 10Gbps NIC"
  39 #define OC_NAME                 "Emulex OneConnect 10Gbps NIC"
  40 #define OC_NAME1                "Emulex OneConnect 10Gbps NIC (be3)"
  41 #define DRV_DESC                BE_NAME "Driver"
  42
  43 #define BE_VENDOR_ID            0x19a2
  44 #define BE_DEVICE_ID1           0x211
  45 #define BE_DEVICE_ID2           0x221
  46 #define OC_DEVICE_ID1           0x700
  47 #define OC_DEVICE_ID2           0x701
  48 #define OC_DEVICE_ID3           0x710
  49
  50 static inline char *nic_name(struct pci_dev *pdev)
  51 {
  52         switch (pdev->device) {
  53         case OC_DEVICE_ID1:
  54         case OC_DEVICE_ID2:
  55                 return OC_NAME;
  56         case OC_DEVICE_ID3:
  57                 return OC_NAME1;
  58         case BE_DEVICE_ID2:
  59                 return BE3_NAME;
  60         default:
  61                 return BE_NAME;
  62         }
  63 }
  64
  65 /* Number of bytes of an RX frame that are copied to skb->data */
  66 #define BE_HDR_LEN              64
  67 #define BE_MAX_JUMBO_FRAME_SIZE 9018
  68 #define BE_MIN_MTU              256
  69
  70 #define BE_NUM_VLANS_SUPPORTED  64
  71 #define BE_MAX_EQD              96
  72 #define BE_MAX_TX_FRAG_COUNT    30
  73
  74 #define EVNT_Q_LEN              1024
  75 #define TX_Q_LEN                2048
  76 #define TX_CQ_LEN               1024
  77 #define RX_Q_LEN                1024    /* Does not support any other value */
  78 #define RX_CQ_LEN               1024
  79 #define MCC_Q_LEN               128     /* total size not to exceed 8 pages */
  80 #define MCC_CQ_LEN              256
  81
  82 #define BE_NAPI_WEIGHT          64
  83 #define MAX_RX_POST             BE_NAPI_WEIGHT /* Frags posted at a time */
  84 #define RX_FRAGS_REFILL_WM      (RX_Q_LEN - MAX_RX_POST)
  85
  86 #define FW_VER_LEN              32
  87
  88 struct be_dma_mem {
  89         void *va;
  90         dma_addr_t dma;
  91         u32 size;
  92 };
  93
  94 struct be_queue_info {
  95         struct be_dma_mem dma_mem;
  96         u16 len;
  97         u16 entry_size; /* Size of an element in the queue */
  98         u16 id;
  99         u16 tail, head;
 100         bool created;
 101         atomic_t used;  /* Number of valid elements in the queue */
 102 };
 103
 104 static inline u32 MODULO(u16 val, u16 limit)
 105 {
 106         BUG_ON(limit & (limit - 1));
 107         return val & (limit - 1);
 108 }
 109
 110 static inline void index_adv(u16 *index, u16 val, u16 limit)
 111 {
 112         *index = MODULO((*index + val), limit);
 113 }
 114
 115 static inline void index_inc(u16 *index, u16 limit)
 116 {
 117         *index = MODULO((*index + 1), limit);
 118 }
 119
 120 static inline void *queue_head_node(struct be_queue_info *q)
 121 {
 122         return q->dma_mem.va + q->head * q->entry_size;
 123 }
 124
 125 static inline void *queue_tail_node(struct be_queue_info *q)
 126 {
 127         return q->dma_mem.va + q->tail * q->entry_size;
 128 }
 129
 130 static inline void queue_head_inc(struct be_queue_info *q)
 131 {
 132         index_inc(&q->head, q->len);
 133 }
 134
 135 static inline void queue_tail_inc(struct be_queue_info *q)
 136 {
 137         index_inc(&q->tail, q->len);
 138 }
 139
 140 struct be_eq_obj {
 141         struct be_queue_info q;
 142         char desc[32];
 143
 144         /* Adaptive interrupt coalescing (AIC) info */
 145         bool enable_aic;
 146         u16 min_eqd;            /* in usecs */
 147         u16 max_eqd;            /* in usecs */
 148         u16 cur_eqd;            /* in usecs */
 149
 150         struct napi_struct napi;
 151 };
 152
 153 struct be_mcc_obj {
 154         struct be_queue_info q;
 155         struct be_queue_info cq;
 156 };
 157
 158 struct be_drvr_stats {
 159         u32 be_tx_reqs;         /* number of TX requests initiated */
 160         u32 be_tx_stops;        /* number of times TX Q was stopped */
 161         u32 be_fwd_reqs;        /* number of send reqs through forwarding i/f */
 162         u32 be_tx_wrbs;         /* number of tx WRBs used */
 163         u32 be_tx_events;       /* number of tx completion events  */
 164         u32 be_tx_compl;        /* number of tx completion entries processed */
 165         ulong be_tx_jiffies;
 166         u64 be_tx_bytes;
 167         u64 be_tx_bytes_prev;
 168         u64 be_tx_pkts;
 169         u32 be_tx_rate;
 170
 171         u32 cache_barrier[16];
 172
 173         u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
 174         u32 be_polls;           /* number of times NAPI called poll function */
 175         u32 be_rx_events;       /* number of ucast rx completion events  */
 176         u32 be_rx_compl;        /* number of rx completion entries processed */
 177         ulong be_rx_jiffies;
 178         u64 be_rx_bytes;
 179         u64 be_rx_bytes_prev;
 180         u64 be_rx_pkts;
 181         u32 be_rx_rate;
 182         /* number of non ether type II frames dropped where
 183          * frame len > length field of Mac Hdr */
 184         u32 be_802_3_dropped_frames;
 185         /* number of non ether type II frames malformed where
 186          * in frame len < length field of Mac Hdr */
 187         u32 be_802_3_malformed_frames;
 188         u32 be_rxcp_err;        /* Num rx completion entries w/ err set. */
 189         ulong rx_fps_jiffies;   /* jiffies at last FPS calc */
 190         u32 be_rx_frags;
 191         u32 be_prev_rx_frags;
 192         u32 be_rx_fps;          /* Rx frags per second */
 193 };
 194
 195 struct be_stats_obj {
 196         struct be_drvr_stats drvr_stats;
 197         struct net_device_stats net_stats;
 198         struct be_dma_mem cmd;
 199 };
 200
 201 struct be_tx_obj {
 202         struct be_queue_info q;
 203         struct be_queue_info cq;
 204         /* Remember the skbs that were transmitted */
 205         struct sk_buff *sent_skb_list[TX_Q_LEN];
 206 };
 207
 208 /* Struct to remember the pages posted for rx frags */
 209 struct be_rx_page_info {
 210         struct page *page;
 211         dma_addr_t bus;
 212         u16 page_offset;
 213         bool last_page_user;
 214 };
 215
 216 struct be_rx_obj {
 217         struct be_queue_info q;
 218         struct be_queue_info cq;
 219         struct be_rx_page_info page_info_tbl[RX_Q_LEN];
 220 };
 221
 222 #define BE_NUM_MSIX_VECTORS             2       /* 1 each for Tx and Rx */
 223 struct be_adapter {
 224         struct pci_dev *pdev;
 225         struct net_device *netdev;
 226
 227         u8 __iomem *csr;
 228         u8 __iomem *db;         /* Door Bell */
 229         u8 __iomem *pcicfg;     /* PCI config space */
 230
 231         spinlock_t mbox_lock;   /* For serializing mbox cmds to BE card */
 232         struct be_dma_mem mbox_mem;
 233         /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
 234          * is stored for freeing purpose */
 235         struct be_dma_mem mbox_mem_alloced;
 236
 237         struct be_mcc_obj mcc_obj;
 238         spinlock_t mcc_lock;    /* For serializing mcc cmds to BE card */
 239         spinlock_t mcc_cq_lock;
 240
 241         struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
 242         bool msix_enabled;
 243         bool isr_registered;
 244
 245         /* TX Rings */
 246         struct be_eq_obj tx_eq;
 247         struct be_tx_obj tx_obj;
 248
 249         u32 cache_line_break[8];
 250
 251         /* Rx rings */
 252         struct be_eq_obj rx_eq;
 253         struct be_rx_obj rx_obj;
 254         u32 big_page_size;      /* Compounded page size shared by rx wrbs */
 255         bool rx_post_starved;   /* Zero rx frags have been posted to BE */
 256
 257         struct vlan_group *vlan_grp;
 258         u16 num_vlans;
 259         u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
 260
 261         struct be_stats_obj stats;
 262         /* Work queue used to perform periodic tasks like getting statistics */
 263         struct delayed_work work;
 264
 265         /* Ethtool knobs and info */
 266         bool rx_csum;           /* BE card must perform rx-checksumming */
 267         char fw_ver[FW_VER_LEN];
 268         u32 if_handle;          /* Used to configure filtering */
 269         u32 pmac_id;            /* MAC addr handle used by BE card */
 270
 271         bool link_up;
 272         u32 port_num;
 273         bool promiscuous;
 274         u32 cap;
 275         u32 rx_fc;              /* Rx flow control */
 276         u32 tx_fc;              /* Tx flow control */
 277         u8 generation;          /* BladeEngine ASIC generation */
 278 };
 279
 280 /* BladeEngine Generation numbers */
 281 #define BE_GEN2 2
 282 #define BE_GEN3 3
 283
 284 extern const struct ethtool_ops be_ethtool_ops;
 285
 286 #define drvr_stats(adapter)             (&adapter->stats.drvr_stats)
 287
 288 static inline unsigned int be_pci_func(struct be_adapter *adapter)
 289 {
 290         return PCI_FUNC(adapter->pdev->devfn);
 291 }
 292
 293 #define BE_SET_NETDEV_OPS(netdev, ops)  (netdev->netdev_ops = ops)
 294
 295 #define PAGE_SHIFT_4K           12
 296 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 297
 298 /* Returns number of pages spanned by the data starting at the given addr */
 299 #define PAGES_4K_SPANNED(_address, size)                                \
 300                 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 301                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 302
 303 /* Byte offset into the page corresponding to given address */
 304 #define OFFSET_IN_PAGE(addr)                                            \
 305                  ((size_t)(addr) & (PAGE_SIZE_4K-1))
 306
 307 /* Returns bit offset within a DWORD of a bitfield */
 308 #define AMAP_BIT_OFFSET(_struct, field)                                 \
 309                 (((size_t)&(((_struct *)0)->field))%32)
 310
 311 /* Returns the bit mask of the field that is NOT shifted into location. */
 312 static inline u32 amap_mask(u32 bitsize)
 313 {
 314         return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
 315 }
 316
 317 static inline void
 318 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
 319 {
 320         u32 *dw = (u32 *) ptr + dw_offset;
 321         *dw &= ~(mask << offset);
 322         *dw |= (mask & value) << offset;
 323 }
 324
 325 #define AMAP_SET_BITS(_struct, field, ptr, val)                         \
 326                 amap_set(ptr,                                           \
 327                         offsetof(_struct, field)/32,                    \
 328                         amap_mask(sizeof(((_struct *)0)->field)),       \
 329                         AMAP_BIT_OFFSET(_struct, field),                \
 330                         val)
 331
 332 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
 333 {
 334         u32 *dw = (u32 *) ptr;
 335         return mask & (*(dw + dw_offset) >> offset);
 336 }
 337
 338 #define AMAP_GET_BITS(_struct, field, ptr)                              \
 339                 amap_get(ptr,                                           \
 340                         offsetof(_struct, field)/32,                    \
 341                         amap_mask(sizeof(((_struct *)0)->field)),       \
 342                         AMAP_BIT_OFFSET(_struct, field))
 343
 344 #define be_dws_cpu_to_le(wrb, len)      swap_dws(wrb, len)
 345 #define be_dws_le_to_cpu(wrb, len)      swap_dws(wrb, len)
 346 static inline void swap_dws(void *wrb, int len)
 347 {
 348 #ifdef __BIG_ENDIAN
 349         u32 *dw = wrb;
 350         BUG_ON(len % 4);
 351         do {
 352                 *dw = cpu_to_le32(*dw);
 353                 dw++;
 354                 len -= 4;
 355         } while (len);
 356 #endif                          /* __BIG_ENDIAN */
 357 }
 358
 359 static inline u8 is_tcp_pkt(struct sk_buff *skb)
 360 {
 361         u8 val = 0;
 362
 363         if (ip_hdr(skb)->version == 4)
 364                 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
 365         else if (ip_hdr(skb)->version == 6)
 366                 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
 367
 368         return val;
 369 }
 370
 371 static inline u8 is_udp_pkt(struct sk_buff *skb)
 372 {
 373         u8 val = 0;
 374
 375         if (ip_hdr(skb)->version == 4)
 376                 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
 377         else if (ip_hdr(skb)->version == 6)
 378                 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
 379
 380         return val;
 381 }
 382
 383 extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
 384                 u16 num_popped);
 385 extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
 386 extern void netdev_stats_update(struct be_adapter *adapter);
 387 extern int be_load_fw(struct be_adapter *adapter, u8 *func);
 388 #endif                          /* BE_H */