drivers/net/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0x0,
  55 /* The client does not have sufficient privileges to execute the command */
  56         MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
  57 /* A parameter in the command was invalid. */
  58         MCC_STATUS_INVALID_PARAMETER = 0x2,
  59 /* There are insufficient chip resources to execute the command */
  60         MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
  61 /* The command is completing because the queue was getting flushed */
  62         MCC_STATUS_QUEUE_FLUSHING = 0x4,
  63 /* The command is completing with a DMA error */
  64         MCC_STATUS_DMA_FAILED = 0x5,
  65         MCC_STATUS_NOT_SUPPORTED = 66
  66 };
  67
  68 #define CQE_STATUS_COMPL_MASK           0xFFFF
  69 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  70 #define CQE_STATUS_EXTD_MASK            0xFFFF
  71 #define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
  72
  73 struct be_mcc_compl {
  74         u32 status;             /* dword 0 */
  75         u32 tag0;               /* dword 1 */
  76         u32 tag1;               /* dword 2 */
  77         u32 flags;              /* dword 3 */
  78 };
  79
  80 /* When the async bit of mcc_compl is set, the last 4 bytes of
  81  * mcc_compl is interpreted as follows:
  82  */
  83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  84 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  85 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  86 struct be_async_event_trailer {
  87         u32 code;
  88 };
  89
  90 enum {
  91         ASYNC_EVENT_LINK_DOWN   = 0x0,
  92         ASYNC_EVENT_LINK_UP     = 0x1
  93 };
  94
  95 /* When the event code of an async trailer is link-state, the mcc_compl
  96  * must be interpreted as follows
  97  */
  98 struct be_async_event_link_state {
  99         u8 physical_port;
 100         u8 port_link_status;
 101         u8 port_duplex;
 102         u8 port_speed;
 103         u8 port_fault;
 104         u8 rsvd0[7];
 105         struct be_async_event_trailer trailer;
 106 } __packed;
 107
 108 struct be_mcc_mailbox {
 109         struct be_mcc_wrb wrb;
 110         struct be_mcc_compl compl;
 111 };
 112
 113 #define CMD_SUBSYSTEM_COMMON    0x1
 114 #define CMD_SUBSYSTEM_ETH       0x3
 115
 116 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 117 #define OPCODE_COMMON_NTWK_MAC_SET                      2
 118 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 119 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 120 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 121 #define OPCODE_COMMON_WRITE_FLASHROM                    7
 122 #define OPCODE_COMMON_CQ_CREATE                         12
 123 #define OPCODE_COMMON_EQ_CREATE                         13
 124 #define OPCODE_COMMON_MCC_CREATE                        21
 125 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
 126 #define OPCODE_COMMON_GET_FW_VERSION                    35
 127 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 128 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 129 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 130 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 131 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 132 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 133 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 134 #define OPCODE_COMMON_MCC_DESTROY                       53
 135 #define OPCODE_COMMON_CQ_DESTROY                        54
 136 #define OPCODE_COMMON_EQ_DESTROY                        55
 137 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 138 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 139 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 140 #define OPCODE_COMMON_FUNCTION_RESET                    61
 141
 142 #define OPCODE_ETH_ACPI_CONFIG                          2
 143 #define OPCODE_ETH_PROMISCUOUS                          3
 144 #define OPCODE_ETH_GET_STATISTICS                       4
 145 #define OPCODE_ETH_TX_CREATE                            7
 146 #define OPCODE_ETH_RX_CREATE                            8
 147 #define OPCODE_ETH_TX_DESTROY                           9
 148 #define OPCODE_ETH_RX_DESTROY                           10
 149
 150 struct be_cmd_req_hdr {
 151         u8 opcode;              /* dword 0 */
 152         u8 subsystem;           /* dword 0 */
 153         u8 port_number;         /* dword 0 */
 154         u8 domain;              /* dword 0 */
 155         u32 timeout;            /* dword 1 */
 156         u32 request_length;     /* dword 2 */
 157         u8 version;             /* dword 3 */
 158         u8 rsvd[3];             /* dword 3 */
 159 };
 160
 161 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 162 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 163 struct be_cmd_resp_hdr {
 164         u32 info;               /* dword 0 */
 165         u32 status;             /* dword 1 */
 166         u32 response_length;    /* dword 2 */
 167         u32 actual_resp_len;    /* dword 3 */
 168 };
 169
 170 struct phys_addr {
 171         u32 lo;
 172         u32 hi;
 173 };
 174
 175 /**************************
 176  * BE Command definitions *
 177  **************************/
 178
 179 /* Pseudo amap definition in which each bit of the actual structure is defined
 180  * as a byte: used to calculate offset/shift/mask of each field */
 181 struct amap_eq_context {
 182         u8 cidx[13];            /* dword 0*/
 183         u8 rsvd0[3];            /* dword 0*/
 184         u8 epidx[13];           /* dword 0*/
 185         u8 valid;               /* dword 0*/
 186         u8 rsvd1;               /* dword 0*/
 187         u8 size;                /* dword 0*/
 188         u8 pidx[13];            /* dword 1*/
 189         u8 rsvd2[3];            /* dword 1*/
 190         u8 pd[10];              /* dword 1*/
 191         u8 count[3];            /* dword 1*/
 192         u8 solevent;            /* dword 1*/
 193         u8 stalled;             /* dword 1*/
 194         u8 armed;               /* dword 1*/
 195         u8 rsvd3[4];            /* dword 2*/
 196         u8 func[8];             /* dword 2*/
 197         u8 rsvd4;               /* dword 2*/
 198         u8 delaymult[10];       /* dword 2*/
 199         u8 rsvd5[2];            /* dword 2*/
 200         u8 phase[2];            /* dword 2*/
 201         u8 nodelay;             /* dword 2*/
 202         u8 rsvd6[4];            /* dword 2*/
 203         u8 rsvd7[32];           /* dword 3*/
 204 } __packed;
 205
 206 struct be_cmd_req_eq_create {
 207         struct be_cmd_req_hdr hdr;
 208         u16 num_pages;          /* sword */
 209         u16 rsvd0;              /* sword */
 210         u8 context[sizeof(struct amap_eq_context) / 8];
 211         struct phys_addr pages[8];
 212 } __packed;
 213
 214 struct be_cmd_resp_eq_create {
 215         struct be_cmd_resp_hdr resp_hdr;
 216         u16 eq_id;              /* sword */
 217         u16 rsvd0;              /* sword */
 218 } __packed;
 219
 220 /******************** Mac query ***************************/
 221 enum {
 222         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 223         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 224         MAC_ADDRESS_TYPE_PD = 0x2,
 225         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 226 };
 227
 228 struct mac_addr {
 229         u16 size_of_struct;
 230         u8 addr[ETH_ALEN];
 231 } __packed;
 232
 233 struct be_cmd_req_mac_query {
 234         struct be_cmd_req_hdr hdr;
 235         u8 type;
 236         u8 permanent;
 237         u16 if_id;
 238 } __packed;
 239
 240 struct be_cmd_resp_mac_query {
 241         struct be_cmd_resp_hdr hdr;
 242         struct mac_addr mac;
 243 };
 244
 245 /******************** PMac Add ***************************/
 246 struct be_cmd_req_pmac_add {
 247         struct be_cmd_req_hdr hdr;
 248         u32 if_id;
 249         u8 mac_address[ETH_ALEN];
 250         u8 rsvd0[2];
 251 } __packed;
 252
 253 struct be_cmd_resp_pmac_add {
 254         struct be_cmd_resp_hdr hdr;
 255         u32 pmac_id;
 256 };
 257
 258 /******************** PMac Del ***************************/
 259 struct be_cmd_req_pmac_del {
 260         struct be_cmd_req_hdr hdr;
 261         u32 if_id;
 262         u32 pmac_id;
 263 };
 264
 265 /******************** Create CQ ***************************/
 266 /* Pseudo amap definition in which each bit of the actual structure is defined
 267  * as a byte: used to calculate offset/shift/mask of each field */
 268 struct amap_cq_context {
 269         u8 cidx[11];            /* dword 0*/
 270         u8 rsvd0;               /* dword 0*/
 271         u8 coalescwm[2];        /* dword 0*/
 272         u8 nodelay;             /* dword 0*/
 273         u8 epidx[11];           /* dword 0*/
 274         u8 rsvd1;               /* dword 0*/
 275         u8 count[2];            /* dword 0*/
 276         u8 valid;               /* dword 0*/
 277         u8 solevent;            /* dword 0*/
 278         u8 eventable;           /* dword 0*/
 279         u8 pidx[11];            /* dword 1*/
 280         u8 rsvd2;               /* dword 1*/
 281         u8 pd[10];              /* dword 1*/
 282         u8 eqid[8];             /* dword 1*/
 283         u8 stalled;             /* dword 1*/
 284         u8 armed;               /* dword 1*/
 285         u8 rsvd3[4];            /* dword 2*/
 286         u8 func[8];             /* dword 2*/
 287         u8 rsvd4[20];           /* dword 2*/
 288         u8 rsvd5[32];           /* dword 3*/
 289 } __packed;
 290
 291 struct be_cmd_req_cq_create {
 292         struct be_cmd_req_hdr hdr;
 293         u16 num_pages;
 294         u16 rsvd0;
 295         u8 context[sizeof(struct amap_cq_context) / 8];
 296         struct phys_addr pages[8];
 297 } __packed;
 298
 299 struct be_cmd_resp_cq_create {
 300         struct be_cmd_resp_hdr hdr;
 301         u16 cq_id;
 302         u16 rsvd0;
 303 } __packed;
 304
 305 /******************** Create MCCQ ***************************/
 306 /* Pseudo amap definition in which each bit of the actual structure is defined
 307  * as a byte: used to calculate offset/shift/mask of each field */
 308 struct amap_mcc_context {
 309         u8 con_index[14];
 310         u8 rsvd0[2];
 311         u8 ring_size[4];
 312         u8 fetch_wrb;
 313         u8 fetch_r2t;
 314         u8 cq_id[10];
 315         u8 prod_index[14];
 316         u8 fid[8];
 317         u8 pdid[9];
 318         u8 valid;
 319         u8 rsvd1[32];
 320         u8 rsvd2[32];
 321 } __packed;
 322
 323 struct be_cmd_req_mcc_create {
 324         struct be_cmd_req_hdr hdr;
 325         u16 num_pages;
 326         u16 rsvd0;
 327         u8 context[sizeof(struct amap_mcc_context) / 8];
 328         struct phys_addr pages[8];
 329 } __packed;
 330
 331 struct be_cmd_resp_mcc_create {
 332         struct be_cmd_resp_hdr hdr;
 333         u16 id;
 334         u16 rsvd0;
 335 } __packed;
 336
 337 /******************** Create TxQ ***************************/
 338 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 339 #define BE_ULP1_NUM                             1
 340
 341 /* Pseudo amap definition in which each bit of the actual structure is defined
 342  * as a byte: used to calculate offset/shift/mask of each field */
 343 struct amap_tx_context {
 344         u8 rsvd0[16];           /* dword 0 */
 345         u8 tx_ring_size[4];     /* dword 0 */
 346         u8 rsvd1[26];           /* dword 0 */
 347         u8 pci_func_id[8];      /* dword 1 */
 348         u8 rsvd2[9];            /* dword 1 */
 349         u8 ctx_valid;           /* dword 1 */
 350         u8 cq_id_send[16];      /* dword 2 */
 351         u8 rsvd3[16];           /* dword 2 */
 352         u8 rsvd4[32];           /* dword 3 */
 353         u8 rsvd5[32];           /* dword 4 */
 354         u8 rsvd6[32];           /* dword 5 */
 355         u8 rsvd7[32];           /* dword 6 */
 356         u8 rsvd8[32];           /* dword 7 */
 357         u8 rsvd9[32];           /* dword 8 */
 358         u8 rsvd10[32];          /* dword 9 */
 359         u8 rsvd11[32];          /* dword 10 */
 360         u8 rsvd12[32];          /* dword 11 */
 361         u8 rsvd13[32];          /* dword 12 */
 362         u8 rsvd14[32];          /* dword 13 */
 363         u8 rsvd15[32];          /* dword 14 */
 364         u8 rsvd16[32];          /* dword 15 */
 365 } __packed;
 366
 367 struct be_cmd_req_eth_tx_create {
 368         struct be_cmd_req_hdr hdr;
 369         u8 num_pages;
 370         u8 ulp_num;
 371         u8 type;
 372         u8 bound_port;
 373         u8 context[sizeof(struct amap_tx_context) / 8];
 374         struct phys_addr pages[8];
 375 } __packed;
 376
 377 struct be_cmd_resp_eth_tx_create {
 378         struct be_cmd_resp_hdr hdr;
 379         u16 cid;
 380         u16 rsvd0;
 381 } __packed;
 382
 383 /******************** Create RxQ ***************************/
 384 struct be_cmd_req_eth_rx_create {
 385         struct be_cmd_req_hdr hdr;
 386         u16 cq_id;
 387         u8 frag_size;
 388         u8 num_pages;
 389         struct phys_addr pages[2];
 390         u32 interface_id;
 391         u16 max_frame_size;
 392         u16 rsvd0;
 393         u32 rss_queue;
 394 } __packed;
 395
 396 struct be_cmd_resp_eth_rx_create {
 397         struct be_cmd_resp_hdr hdr;
 398         u16 id;
 399         u8 cpu_id;
 400         u8 rsvd0;
 401 } __packed;
 402
 403 /******************** Q Destroy  ***************************/
 404 /* Type of Queue to be destroyed */
 405 enum {
 406         QTYPE_EQ = 1,
 407         QTYPE_CQ,
 408         QTYPE_TXQ,
 409         QTYPE_RXQ,
 410         QTYPE_MCCQ
 411 };
 412
 413 struct be_cmd_req_q_destroy {
 414         struct be_cmd_req_hdr hdr;
 415         u16 id;
 416         u16 bypass_flush;       /* valid only for rx q destroy */
 417 } __packed;
 418
 419 /************ I/f Create (it's actually I/f Config Create)**********/
 420
 421 /* Capability flags for the i/f */
 422 enum be_if_flags {
 423         BE_IF_FLAGS_RSS = 0x4,
 424         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 425         BE_IF_FLAGS_BROADCAST = 0x10,
 426         BE_IF_FLAGS_UNTAGGED = 0x20,
 427         BE_IF_FLAGS_ULP = 0x40,
 428         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 429         BE_IF_FLAGS_VLAN = 0x100,
 430         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 431         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 432         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
 433 };
 434
 435 /* An RX interface is an object with one or more MAC addresses and
 436  * filtering capabilities. */
 437 struct be_cmd_req_if_create {
 438         struct be_cmd_req_hdr hdr;
 439         u32 version;            /* ignore currntly */
 440         u32 capability_flags;
 441         u32 enable_flags;
 442         u8 mac_addr[ETH_ALEN];
 443         u8 rsvd0;
 444         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 445         u32 vlan_tag;    /* not used currently */
 446 } __packed;
 447
 448 struct be_cmd_resp_if_create {
 449         struct be_cmd_resp_hdr hdr;
 450         u32 interface_id;
 451         u32 pmac_id;
 452 };
 453
 454 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 455 struct be_cmd_req_if_destroy {
 456         struct be_cmd_req_hdr hdr;
 457         u32 interface_id;
 458 };
 459
 460 /*************** HW Stats Get **********************************/
 461 struct be_port_rxf_stats {
 462         u32 rx_bytes_lsd;       /* dword 0*/
 463         u32 rx_bytes_msd;       /* dword 1*/
 464         u32 rx_total_frames;    /* dword 2*/
 465         u32 rx_unicast_frames;  /* dword 3*/
 466         u32 rx_multicast_frames;        /* dword 4*/
 467         u32 rx_broadcast_frames;        /* dword 5*/
 468         u32 rx_crc_errors;      /* dword 6*/
 469         u32 rx_alignment_symbol_errors; /* dword 7*/
 470         u32 rx_pause_frames;    /* dword 8*/
 471         u32 rx_control_frames;  /* dword 9*/
 472         u32 rx_in_range_errors; /* dword 10*/
 473         u32 rx_out_range_errors;        /* dword 11*/
 474         u32 rx_frame_too_long;  /* dword 12*/
 475         u32 rx_address_match_errors;    /* dword 13*/
 476         u32 rx_vlan_mismatch;   /* dword 14*/
 477         u32 rx_dropped_too_small;       /* dword 15*/
 478         u32 rx_dropped_too_short;       /* dword 16*/
 479         u32 rx_dropped_header_too_small;        /* dword 17*/
 480         u32 rx_dropped_tcp_length;      /* dword 18*/
 481         u32 rx_dropped_runt;    /* dword 19*/
 482         u32 rx_64_byte_packets; /* dword 20*/
 483         u32 rx_65_127_byte_packets;     /* dword 21*/
 484         u32 rx_128_256_byte_packets;    /* dword 22*/
 485         u32 rx_256_511_byte_packets;    /* dword 23*/
 486         u32 rx_512_1023_byte_packets;   /* dword 24*/
 487         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 488         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 489         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 490         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 491         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 492         u32 rx_ip_checksum_errs;        /* dword 30*/
 493         u32 rx_tcp_checksum_errs;       /* dword 31*/
 494         u32 rx_udp_checksum_errs;       /* dword 32*/
 495         u32 rx_non_rss_packets; /* dword 33*/
 496         u32 rx_ipv4_packets;    /* dword 34*/
 497         u32 rx_ipv6_packets;    /* dword 35*/
 498         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 499         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 500         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 501         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 502         u32 rx_chute1_packets;  /* dword 40*/
 503         u32 rx_chute2_packets;  /* dword 41*/
 504         u32 rx_chute3_packets;  /* dword 42*/
 505         u32 rx_management_packets;      /* dword 43*/
 506         u32 rx_switched_unicast_packets;        /* dword 44*/
 507         u32 rx_switched_multicast_packets;      /* dword 45*/
 508         u32 rx_switched_broadcast_packets;      /* dword 46*/
 509         u32 tx_bytes_lsd;       /* dword 47*/
 510         u32 tx_bytes_msd;       /* dword 48*/
 511         u32 tx_unicastframes;   /* dword 49*/
 512         u32 tx_multicastframes; /* dword 50*/
 513         u32 tx_broadcastframes; /* dword 51*/
 514         u32 tx_pauseframes;     /* dword 52*/
 515         u32 tx_controlframes;   /* dword 53*/
 516         u32 tx_64_byte_packets; /* dword 54*/
 517         u32 tx_65_127_byte_packets;     /* dword 55*/
 518         u32 tx_128_256_byte_packets;    /* dword 56*/
 519         u32 tx_256_511_byte_packets;    /* dword 57*/
 520         u32 tx_512_1023_byte_packets;   /* dword 58*/
 521         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 522         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 523         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 524         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 525         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 526         u32 rx_fifo_overflow;   /* dword 64*/
 527         u32 rx_input_fifo_overflow;     /* dword 65*/
 528 };
 529
 530 struct be_rxf_stats {
 531         struct be_port_rxf_stats port[2];
 532         u32 rx_drops_no_pbuf;   /* dword 132*/
 533         u32 rx_drops_no_txpb;   /* dword 133*/
 534         u32 rx_drops_no_erx_descr;      /* dword 134*/
 535         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 536         u32 management_rx_port_packets; /* dword 136*/
 537         u32 management_rx_port_bytes;   /* dword 137*/
 538         u32 management_rx_port_pause_frames;    /* dword 138*/
 539         u32 management_rx_port_errors;  /* dword 139*/
 540         u32 management_tx_port_packets; /* dword 140*/
 541         u32 management_tx_port_bytes;   /* dword 141*/
 542         u32 management_tx_port_pause;   /* dword 142*/
 543         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 544         u32 rx_drops_too_many_frags;    /* dword 144*/
 545         u32 rx_drops_invalid_ring;      /* dword 145*/
 546         u32 forwarded_packets;  /* dword 146*/
 547         u32 rx_drops_mtu;       /* dword 147*/
 548         u32 rsvd0[15];
 549 };
 550
 551 struct be_erx_stats {
 552         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 553         u32 debug_wdma_sent_hold;          /* dword 44*/
 554         u32 debug_wdma_pbfree_sent_hold;   /* dword 45*/
 555         u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
 556         u32 debug_pmem_pbuf_dealloc;       /* dword 47*/
 557 };
 558
 559 struct be_hw_stats {
 560         struct be_rxf_stats rxf;
 561         u32 rsvd[48];
 562         struct be_erx_stats erx;
 563 };
 564
 565 struct be_cmd_req_get_stats {
 566         struct be_cmd_req_hdr hdr;
 567         u8 rsvd[sizeof(struct be_hw_stats)];
 568 };
 569
 570 struct be_cmd_resp_get_stats {
 571         struct be_cmd_resp_hdr hdr;
 572         struct be_hw_stats hw_stats;
 573 };
 574
 575 struct be_cmd_req_vlan_config {
 576         struct be_cmd_req_hdr hdr;
 577         u8 interface_id;
 578         u8 promiscuous;
 579         u8 untagged;
 580         u8 num_vlan;
 581         u16 normal_vlan[64];
 582 } __packed;
 583
 584 struct be_cmd_req_promiscuous_config {
 585         struct be_cmd_req_hdr hdr;
 586         u8 port0_promiscuous;
 587         u8 port1_promiscuous;
 588         u16 rsvd0;
 589 } __packed;
 590
 591 struct macaddr {
 592         u8 byte[ETH_ALEN];
 593 };
 594
 595 struct be_cmd_req_mcast_mac_config {
 596         struct be_cmd_req_hdr hdr;
 597         u16 num_mac;
 598         u8 promiscuous;
 599         u8 interface_id;
 600         struct macaddr mac[32];
 601 } __packed;
 602
 603 static inline struct be_hw_stats *
 604 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
 605 {
 606         return &cmd->hw_stats;
 607 }
 608
 609 /******************** Link Status Query *******************/
 610 struct be_cmd_req_link_status {
 611         struct be_cmd_req_hdr hdr;
 612         u32 rsvd;
 613 };
 614
 615 enum {
 616         PHY_LINK_DUPLEX_NONE = 0x0,
 617         PHY_LINK_DUPLEX_HALF = 0x1,
 618         PHY_LINK_DUPLEX_FULL = 0x2
 619 };
 620
 621 enum {
 622         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 623         PHY_LINK_SPEED_10MBPS = 0x1,
 624         PHY_LINK_SPEED_100MBPS = 0x2,
 625         PHY_LINK_SPEED_1GBPS = 0x3,
 626         PHY_LINK_SPEED_10GBPS = 0x4
 627 };
 628
 629 struct be_cmd_resp_link_status {
 630         struct be_cmd_resp_hdr hdr;
 631         u8 physical_port;
 632         u8 mac_duplex;
 633         u8 mac_speed;
 634         u8 mac_fault;
 635         u8 mgmt_mac_duplex;
 636         u8 mgmt_mac_speed;
 637         u16 rsvd0;
 638 } __packed;
 639
 640 /******************** Get FW Version *******************/
 641 struct be_cmd_req_get_fw_version {
 642         struct be_cmd_req_hdr hdr;
 643         u8 rsvd0[FW_VER_LEN];
 644         u8 rsvd1[FW_VER_LEN];
 645 } __packed;
 646
 647 struct be_cmd_resp_get_fw_version {
 648         struct be_cmd_resp_hdr hdr;
 649         u8 firmware_version_string[FW_VER_LEN];
 650         u8 fw_on_flash_version_string[FW_VER_LEN];
 651 } __packed;
 652
 653 /******************** Set Flow Contrl *******************/
 654 struct be_cmd_req_set_flow_control {
 655         struct be_cmd_req_hdr hdr;
 656         u16 tx_flow_control;
 657         u16 rx_flow_control;
 658 } __packed;
 659
 660 /******************** Get Flow Contrl *******************/
 661 struct be_cmd_req_get_flow_control {
 662         struct be_cmd_req_hdr hdr;
 663         u32 rsvd;
 664 };
 665
 666 struct be_cmd_resp_get_flow_control {
 667         struct be_cmd_resp_hdr hdr;
 668         u16 tx_flow_control;
 669         u16 rx_flow_control;
 670 } __packed;
 671
 672 /******************** Modify EQ Delay *******************/
 673 struct be_cmd_req_modify_eq_delay {
 674         struct be_cmd_req_hdr hdr;
 675         u32 num_eq;
 676         struct {
 677                 u32 eq_id;
 678                 u32 phase;
 679                 u32 delay_multiplier;
 680         } delay[8];
 681 } __packed;
 682
 683 struct be_cmd_resp_modify_eq_delay {
 684         struct be_cmd_resp_hdr hdr;
 685         u32 rsvd0;
 686 } __packed;
 687
 688 /******************** Get FW Config *******************/
 689 struct be_cmd_req_query_fw_cfg {
 690         struct be_cmd_req_hdr hdr;
 691         u32 rsvd[30];
 692 };
 693
 694 struct be_cmd_resp_query_fw_cfg {
 695         struct be_cmd_resp_hdr hdr;
 696         u32 be_config_number;
 697         u32 asic_revision;
 698         u32 phys_port;
 699         u32 function_cap;
 700         u32 rsvd[26];
 701 };
 702
 703 /****************** Firmware Flash ******************/
 704 struct flashrom_params {
 705         u32 op_code;
 706         u32 op_type;
 707         u32 data_buf_size;
 708         u32 offset;
 709         u8 data_buf[4];
 710 };
 711
 712 struct be_cmd_write_flashrom {
 713         struct be_cmd_req_hdr hdr;
 714         struct flashrom_params params;
 715 };
 716
 717 extern int be_pci_fnum_get(struct be_adapter *adapter);
 718 extern int be_cmd_POST(struct be_adapter *adapter);
 719 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 720                         u8 type, bool permanent, u32 if_handle);
 721 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 722                         u32 if_id, u32 *pmac_id);
 723 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
 724 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
 725                         u32 en_flags, u8 *mac, bool pmac_invalid,
 726                         u32 *if_handle, u32 *pmac_id);
 727 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
 728 extern int be_cmd_eq_create(struct be_adapter *adapter,
 729                         struct be_queue_info *eq, int eq_delay);
 730 extern int be_cmd_cq_create(struct be_adapter *adapter,
 731                         struct be_queue_info *cq, struct be_queue_info *eq,
 732                         bool sol_evts, bool no_delay,
 733                         int num_cqe_dma_coalesce);
 734 extern int be_cmd_mccq_create(struct be_adapter *adapter,
 735                         struct be_queue_info *mccq,
 736                         struct be_queue_info *cq);
 737 extern int be_cmd_txq_create(struct be_adapter *adapter,
 738                         struct be_queue_info *txq,
 739                         struct be_queue_info *cq);
 740 extern int be_cmd_rxq_create(struct be_adapter *adapter,
 741                         struct be_queue_info *rxq, u16 cq_id,
 742                         u16 frag_size, u16 max_frame_size, u32 if_id,
 743                         u32 rss);
 744 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 745                         int type);
 746 extern int be_cmd_link_status_query(struct be_adapter *adapter,
 747                         bool *link_up);
 748 extern int be_cmd_reset(struct be_adapter *adapter);
 749 extern int be_cmd_get_stats(struct be_adapter *adapter,
 750                         struct be_dma_mem *nonemb_cmd);
 751 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
 752
 753 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
 754 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
 755                         u16 *vtag_array, u32 num, bool untagged,
 756                         bool promiscuous);
 757 extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
 758                         u8 port_num, bool en);
 759 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
 760                         struct dev_mc_list *mc_list, u32 mc_count);
 761 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
 762                         u32 tx_fc, u32 rx_fc);
 763 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
 764                         u32 *tx_fc, u32 *rx_fc);
 765 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
 766                         u32 *port_num, u32 *cap);
 767 extern int be_cmd_reset_function(struct be_adapter *adapter);
 768 extern int be_process_mcc(struct be_adapter *adapter);
 769 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
 770                         struct be_dma_mem *cmd, u32 flash_oper,
 771                         u32 flash_opcode, u32 buf_size);