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init from v2.6.32.60
[mach-moxart.git] / drivers / net / bnx2.c
blob4874b2bd6bbd6ffc501fc7263486b9bf705e332a
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
40 #define BCM_VLAN 1
41 #endif
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/firmware.h>
50 #include <linux/log2.h>
51 #include <linux/list.h>
52
53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54 #define BCM_CNIC 1
55 #include "cnic_if.h"
56 #endif
57 #include "bnx2.h"
58 #include "bnx2_fw.h"
59
60 #define DRV_MODULE_NAME "bnx2"
61 #define PFX DRV_MODULE_NAME ": "
62 #define DRV_MODULE_VERSION "2.0.2"
63 #define DRV_MODULE_RELDATE "Aug 21, 2009"
64 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j3.fw"
65 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
66 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j3.fw"
67 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j3.fw"
68 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j3.fw"
69
70 #define RUN_AT(x) (jiffies + (x))
71
72 /* Time in jiffies before concluding the transmitter is hung. */
73 #define TX_TIMEOUT (5*HZ)
74
75 static char version[] __devinitdata =
76 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
77
78 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
79 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
80 MODULE_LICENSE("GPL");
81 MODULE_VERSION(DRV_MODULE_VERSION);
82 MODULE_FIRMWARE(FW_MIPS_FILE_06);
83 MODULE_FIRMWARE(FW_RV2P_FILE_06);
84 MODULE_FIRMWARE(FW_MIPS_FILE_09);
85 MODULE_FIRMWARE(FW_RV2P_FILE_09);
86 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
87
88 static int disable_msi = 0;
89
90 module_param(disable_msi, int, 0);
91 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
92
93 typedef enum {
94 BCM5706 = 0,
95 NC370T,
96 NC370I,
97 BCM5706S,
98 NC370F,
99 BCM5708,
100 BCM5708S,
101 BCM5709,
102 BCM5709S,
103 BCM5716,
104 BCM5716S,
105 } board_t;
106
107 /* indexed by board_t, above */
108 static struct {
109 char *name;
110 } board_info[] __devinitdata = {
111 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
112 { "HP NC370T Multifunction Gigabit Server Adapter" },
113 { "HP NC370i Multifunction Gigabit Server Adapter" },
114 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
115 { "HP NC370F Multifunction Gigabit Server Adapter" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
117 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
119 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
121 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
122 };
123
124 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
141 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
143 { PCI_VENDOR_ID_BROADCOM, 0x163b,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
145 { PCI_VENDOR_ID_BROADCOM, 0x163c,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
147 { 0, }
148 };
149
150 static const struct flash_spec flash_table[] =
151 {
152 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
153 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
154 /* Slow EEPROM */
155 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
156 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
157 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
158 "EEPROM - slow"},
159 /* Expansion entry 0001 */
160 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
161 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
162 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
163 "Entry 0001"},
164 /* Saifun SA25F010 (non-buffered flash) */
165 /* strap, cfg1, & write1 need updates */
166 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
168 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
169 "Non-buffered flash (128kB)"},
170 /* Saifun SA25F020 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
175 "Non-buffered flash (256kB)"},
176 /* Expansion entry 0100 */
177 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
179 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
180 "Entry 0100"},
181 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
182 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
184 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
185 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
186 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
187 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
189 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
190 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
191 /* Saifun SA25F005 (non-buffered flash) */
192 /* strap, cfg1, & write1 need updates */
193 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
195 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
196 "Non-buffered flash (64kB)"},
197 /* Fast EEPROM */
198 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
199 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
200 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
201 "EEPROM - fast"},
202 /* Expansion entry 1001 */
203 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
204 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
205 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 "Entry 1001"},
207 /* Expansion entry 1010 */
208 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
210 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
211 "Entry 1010"},
212 /* ATMEL AT45DB011B (buffered flash) */
213 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
214 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
215 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
216 "Buffered flash (128kB)"},
217 /* Expansion entry 1100 */
218 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
221 "Entry 1100"},
222 /* Expansion entry 1101 */
223 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
226 "Entry 1101"},
227 /* Ateml Expansion entry 1110 */
228 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
230 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
231 "Entry 1110 (Atmel)"},
232 /* ATMEL AT45DB021B (buffered flash) */
233 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
234 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
235 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
236 "Buffered flash (256kB)"},
237 };
238
239 static const struct flash_spec flash_5709 = {
240 .flags = BNX2_NV_BUFFERED,
241 .page_bits = BCM5709_FLASH_PAGE_BITS,
242 .page_size = BCM5709_FLASH_PAGE_SIZE,
243 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
244 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
245 .name = "5709 Buffered flash (256kB)",
246 };
247
248 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
249
250 static void bnx2_init_napi(struct bnx2 *bp);
251 static void bnx2_del_napi(struct bnx2 *bp);
252
253 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
254 {
255 u32 diff;
256
257 smp_mb();
258
259 /* The ring uses 256 indices for 255 entries, one of them
260 * needs to be skipped.
261 */
262 diff = txr->tx_prod - txr->tx_cons;
263 if (unlikely(diff >= TX_DESC_CNT)) {
264 diff &= 0xffff;
265 if (diff == TX_DESC_CNT)
266 diff = MAX_TX_DESC_CNT;
267 }
268 return (bp->tx_ring_size - diff);
269 }
270
271 static u32
272 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
273 {
274 u32 val;
275
276 spin_lock_bh(&bp->indirect_lock);
277 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
278 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
279 spin_unlock_bh(&bp->indirect_lock);
280 return val;
281 }
282
283 static void
284 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
285 {
286 spin_lock_bh(&bp->indirect_lock);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
288 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
289 spin_unlock_bh(&bp->indirect_lock);
290 }
291
292 static void
293 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
294 {
295 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
296 }
297
298 static u32
299 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
300 {
301 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
302 }
303
304 static void
305 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
306 {
307 offset += cid_addr;
308 spin_lock_bh(&bp->indirect_lock);
309 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
310 int i;
311
312 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
313 REG_WR(bp, BNX2_CTX_CTX_CTRL,
314 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
315 for (i = 0; i < 5; i++) {
316 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
317 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
318 break;
319 udelay(5);
320 }
321 } else {
322 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
323 REG_WR(bp, BNX2_CTX_DATA, val);
324 }
325 spin_unlock_bh(&bp->indirect_lock);
326 }
327
328 #ifdef BCM_CNIC
329 static int
330 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
331 {
332 struct bnx2 *bp = netdev_priv(dev);
333 struct drv_ctl_io *io = &info->data.io;
334
335 switch (info->cmd) {
336 case DRV_CTL_IO_WR_CMD:
337 bnx2_reg_wr_ind(bp, io->offset, io->data);
338 break;
339 case DRV_CTL_IO_RD_CMD:
340 io->data = bnx2_reg_rd_ind(bp, io->offset);
341 break;
342 case DRV_CTL_CTX_WR_CMD:
343 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
344 break;
345 default:
346 return -EINVAL;
347 }
348 return 0;
349 }
350
351 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
352 {
353 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
354 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
355 int sb_id;
356
357 if (bp->flags & BNX2_FLAG_USING_MSIX) {
358 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
359 bnapi->cnic_present = 0;
360 sb_id = bp->irq_nvecs;
361 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
362 } else {
363 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
364 bnapi->cnic_tag = bnapi->last_status_idx;
365 bnapi->cnic_present = 1;
366 sb_id = 0;
367 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
368 }
369
370 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
371 cp->irq_arr[0].status_blk = (void *)
372 ((unsigned long) bnapi->status_blk.msi +
373 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
374 cp->irq_arr[0].status_blk_num = sb_id;
375 cp->num_irq = 1;
376 }
377
378 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
379 void *data)
380 {
381 struct bnx2 *bp = netdev_priv(dev);
382 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
383
384 if (ops == NULL)
385 return -EINVAL;
386
387 if (cp->drv_state & CNIC_DRV_STATE_REGD)
388 return -EBUSY;
389
390 bp->cnic_data = data;
391 rcu_assign_pointer(bp->cnic_ops, ops);
392
393 cp->num_irq = 0;
394 cp->drv_state = CNIC_DRV_STATE_REGD;
395
396 bnx2_setup_cnic_irq_info(bp);
397
398 return 0;
399 }
400
401 static int bnx2_unregister_cnic(struct net_device *dev)
402 {
403 struct bnx2 *bp = netdev_priv(dev);
404 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
405 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
406
407 mutex_lock(&bp->cnic_lock);
408 cp->drv_state = 0;
409 bnapi->cnic_present = 0;
410 rcu_assign_pointer(bp->cnic_ops, NULL);
411 mutex_unlock(&bp->cnic_lock);
412 synchronize_rcu();
413 return 0;
414 }
415
416 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
417 {
418 struct bnx2 *bp = netdev_priv(dev);
419 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
420
421 cp->drv_owner = THIS_MODULE;
422 cp->chip_id = bp->chip_id;
423 cp->pdev = bp->pdev;
424 cp->io_base = bp->regview;
425 cp->drv_ctl = bnx2_drv_ctl;
426 cp->drv_register_cnic = bnx2_register_cnic;
427 cp->drv_unregister_cnic = bnx2_unregister_cnic;
428
429 return cp;
430 }
431 EXPORT_SYMBOL(bnx2_cnic_probe);
432
433 static void
434 bnx2_cnic_stop(struct bnx2 *bp)
435 {
436 struct cnic_ops *c_ops;
437 struct cnic_ctl_info info;
438
439 mutex_lock(&bp->cnic_lock);
440 c_ops = bp->cnic_ops;
441 if (c_ops) {
442 info.cmd = CNIC_CTL_STOP_CMD;
443 c_ops->cnic_ctl(bp->cnic_data, &info);
444 }
445 mutex_unlock(&bp->cnic_lock);
446 }
447
448 static void
449 bnx2_cnic_start(struct bnx2 *bp)
450 {
451 struct cnic_ops *c_ops;
452 struct cnic_ctl_info info;
453
454 mutex_lock(&bp->cnic_lock);
455 c_ops = bp->cnic_ops;
456 if (c_ops) {
457 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
458 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
459
460 bnapi->cnic_tag = bnapi->last_status_idx;
461 }
462 info.cmd = CNIC_CTL_START_CMD;
463 c_ops->cnic_ctl(bp->cnic_data, &info);
464 }
465 mutex_unlock(&bp->cnic_lock);
466 }
467
468 #else
469
470 static void
471 bnx2_cnic_stop(struct bnx2 *bp)
472 {
473 }
474
475 static void
476 bnx2_cnic_start(struct bnx2 *bp)
477 {
478 }
479
480 #endif
481
482 static int
483 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
484 {
485 u32 val1;
486 int i, ret;
487
488 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
489 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
490 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
491
492 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
493 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
494
495 udelay(40);
496 }
497
498 val1 = (bp->phy_addr << 21) | (reg << 16) |
499 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
500 BNX2_EMAC_MDIO_COMM_START_BUSY;
501 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
502
503 for (i = 0; i < 50; i++) {
504 udelay(10);
505
506 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
507 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
508 udelay(5);
509
510 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
511 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
512
513 break;
514 }
515 }
516
517 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
518 *val = 0x0;
519 ret = -EBUSY;
520 }
521 else {
522 *val = val1;
523 ret = 0;
524 }
525
526 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
527 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
528 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
529
530 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
531 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
532
533 udelay(40);
534 }
535
536 return ret;
537 }
538
539 static int
540 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
541 {
542 u32 val1;
543 int i, ret;
544
545 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
546 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
547 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
548
549 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
550 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
551
552 udelay(40);
553 }
554
555 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
556 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
557 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
558 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
559
560 for (i = 0; i < 50; i++) {
561 udelay(10);
562
563 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
564 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
565 udelay(5);
566 break;
567 }
568 }
569
570 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
571 ret = -EBUSY;
572 else
573 ret = 0;
574
575 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
576 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
577 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
578
579 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
580 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
581
582 udelay(40);
583 }
584
585 return ret;
586 }
587
588 static void
589 bnx2_disable_int(struct bnx2 *bp)
590 {
591 int i;
592 struct bnx2_napi *bnapi;
593
594 for (i = 0; i < bp->irq_nvecs; i++) {
595 bnapi = &bp->bnx2_napi[i];
596 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
597 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
598 }
599 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
600 }
601
602 static void
603 bnx2_enable_int(struct bnx2 *bp)
604 {
605 int i;
606 struct bnx2_napi *bnapi;
607
608 for (i = 0; i < bp->irq_nvecs; i++) {
609 bnapi = &bp->bnx2_napi[i];
610
611 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
612 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
613 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
614 bnapi->last_status_idx);
615
616 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
617 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
618 bnapi->last_status_idx);
619 }
620 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
621 }
622
623 static void
624 bnx2_disable_int_sync(struct bnx2 *bp)
625 {
626 int i;
627
628 atomic_inc(&bp->intr_sem);
629 if (!netif_running(bp->dev))
630 return;
631
632 bnx2_disable_int(bp);
633 for (i = 0; i < bp->irq_nvecs; i++)
634 synchronize_irq(bp->irq_tbl[i].vector);
635 }
636
637 static void
638 bnx2_napi_disable(struct bnx2 *bp)
639 {
640 int i;
641
642 for (i = 0; i < bp->irq_nvecs; i++)
643 napi_disable(&bp->bnx2_napi[i].napi);
644 }
645
646 static void
647 bnx2_napi_enable(struct bnx2 *bp)
648 {
649 int i;
650
651 for (i = 0; i < bp->irq_nvecs; i++)
652 napi_enable(&bp->bnx2_napi[i].napi);
653 }
654
655 static void
656 bnx2_netif_stop(struct bnx2 *bp)
657 {
658 bnx2_cnic_stop(bp);
659 bnx2_disable_int_sync(bp);
660 if (netif_running(bp->dev)) {
661 bnx2_napi_disable(bp);
662 netif_tx_disable(bp->dev);
663 bp->dev->trans_start = jiffies; /* prevent tx timeout */
664 }
665 }
666
667 static void
668 bnx2_netif_start(struct bnx2 *bp)
669 {
670 if (atomic_dec_and_test(&bp->intr_sem)) {
671 if (netif_running(bp->dev)) {
672 netif_tx_wake_all_queues(bp->dev);
673 bnx2_napi_enable(bp);
674 bnx2_enable_int(bp);
675 bnx2_cnic_start(bp);
676 }
677 }
678 }
679
680 static void
681 bnx2_free_tx_mem(struct bnx2 *bp)
682 {
683 int i;
684
685 for (i = 0; i < bp->num_tx_rings; i++) {
686 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
687 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
688
689 if (txr->tx_desc_ring) {
690 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
691 txr->tx_desc_ring,
692 txr->tx_desc_mapping);
693 txr->tx_desc_ring = NULL;
694 }
695 kfree(txr->tx_buf_ring);
696 txr->tx_buf_ring = NULL;
697 }
698 }
699
700 static void
701 bnx2_free_rx_mem(struct bnx2 *bp)
702 {
703 int i;
704
705 for (i = 0; i < bp->num_rx_rings; i++) {
706 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
707 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
708 int j;
709
710 for (j = 0; j < bp->rx_max_ring; j++) {
711 if (rxr->rx_desc_ring[j])
712 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
713 rxr->rx_desc_ring[j],
714 rxr->rx_desc_mapping[j]);
715 rxr->rx_desc_ring[j] = NULL;
716 }
717 vfree(rxr->rx_buf_ring);
718 rxr->rx_buf_ring = NULL;
719
720 for (j = 0; j < bp->rx_max_pg_ring; j++) {
721 if (rxr->rx_pg_desc_ring[j])
722 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
723 rxr->rx_pg_desc_ring[j],
724 rxr->rx_pg_desc_mapping[j]);
725 rxr->rx_pg_desc_ring[j] = NULL;
726 }
727 vfree(rxr->rx_pg_ring);
728 rxr->rx_pg_ring = NULL;
729 }
730 }
731
732 static int
733 bnx2_alloc_tx_mem(struct bnx2 *bp)
734 {
735 int i;
736
737 for (i = 0; i < bp->num_tx_rings; i++) {
738 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
739 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
740
741 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
742 if (txr->tx_buf_ring == NULL)
743 return -ENOMEM;
744
745 txr->tx_desc_ring =
746 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
747 &txr->tx_desc_mapping);
748 if (txr->tx_desc_ring == NULL)
749 return -ENOMEM;
750 }
751 return 0;
752 }
753
754 static int
755 bnx2_alloc_rx_mem(struct bnx2 *bp)
756 {
757 int i;
758
759 for (i = 0; i < bp->num_rx_rings; i++) {
760 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
761 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
762 int j;
763
764 rxr->rx_buf_ring =
765 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
766 if (rxr->rx_buf_ring == NULL)
767 return -ENOMEM;
768
769 memset(rxr->rx_buf_ring, 0,
770 SW_RXBD_RING_SIZE * bp->rx_max_ring);
771
772 for (j = 0; j < bp->rx_max_ring; j++) {
773 rxr->rx_desc_ring[j] =
774 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
775 &rxr->rx_desc_mapping[j]);
776 if (rxr->rx_desc_ring[j] == NULL)
777 return -ENOMEM;
778
779 }
780
781 if (bp->rx_pg_ring_size) {
782 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
783 bp->rx_max_pg_ring);
784 if (rxr->rx_pg_ring == NULL)
785 return -ENOMEM;
786
787 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
788 bp->rx_max_pg_ring);
789 }
790
791 for (j = 0; j < bp->rx_max_pg_ring; j++) {
792 rxr->rx_pg_desc_ring[j] =
793 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
794 &rxr->rx_pg_desc_mapping[j]);
795 if (rxr->rx_pg_desc_ring[j] == NULL)
796 return -ENOMEM;
797
798 }
799 }
800 return 0;
801 }
802
803 static void
804 bnx2_free_mem(struct bnx2 *bp)
805 {
806 int i;
807 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
808
809 bnx2_free_tx_mem(bp);
810 bnx2_free_rx_mem(bp);
811
812 for (i = 0; i < bp->ctx_pages; i++) {
813 if (bp->ctx_blk[i]) {
814 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
815 bp->ctx_blk[i],
816 bp->ctx_blk_mapping[i]);
817 bp->ctx_blk[i] = NULL;
818 }
819 }
820 if (bnapi->status_blk.msi) {
821 pci_free_consistent(bp->pdev, bp->status_stats_size,
822 bnapi->status_blk.msi,
823 bp->status_blk_mapping);
824 bnapi->status_blk.msi = NULL;
825 bp->stats_blk = NULL;
826 }
827 }
828
829 static int
830 bnx2_alloc_mem(struct bnx2 *bp)
831 {
832 int i, status_blk_size, err;
833 struct bnx2_napi *bnapi;
834 void *status_blk;
835
836 /* Combine status and statistics blocks into one allocation. */
837 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
838 if (bp->flags & BNX2_FLAG_MSIX_CAP)
839 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
840 BNX2_SBLK_MSIX_ALIGN_SIZE);
841 bp->status_stats_size = status_blk_size +
842 sizeof(struct statistics_block);
843
844 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
845 &bp->status_blk_mapping);
846 if (status_blk == NULL)
847 goto alloc_mem_err;
848
849 memset(status_blk, 0, bp->status_stats_size);
850
851 bnapi = &bp->bnx2_napi[0];
852 bnapi->status_blk.msi = status_blk;
853 bnapi->hw_tx_cons_ptr =
854 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
855 bnapi->hw_rx_cons_ptr =
856 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
857 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
858 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
859 struct status_block_msix *sblk;
860
861 bnapi = &bp->bnx2_napi[i];
862
863 sblk = (void *) (status_blk +
864 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
865 bnapi->status_blk.msix = sblk;
866 bnapi->hw_tx_cons_ptr =
867 &sblk->status_tx_quick_consumer_index;
868 bnapi->hw_rx_cons_ptr =
869 &sblk->status_rx_quick_consumer_index;
870 bnapi->int_num = i << 24;
871 }
872 }
873
874 bp->stats_blk = status_blk + status_blk_size;
875
876 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
877
878 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
879 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
880 if (bp->ctx_pages == 0)
881 bp->ctx_pages = 1;
882 for (i = 0; i < bp->ctx_pages; i++) {
883 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
884 BCM_PAGE_SIZE,
885 &bp->ctx_blk_mapping[i]);
886 if (bp->ctx_blk[i] == NULL)
887 goto alloc_mem_err;
888 }
889 }
890
891 err = bnx2_alloc_rx_mem(bp);
892 if (err)
893 goto alloc_mem_err;
894
895 err = bnx2_alloc_tx_mem(bp);
896 if (err)
897 goto alloc_mem_err;
898
899 return 0;
900
901 alloc_mem_err:
902 bnx2_free_mem(bp);
903 return -ENOMEM;
904 }
905
906 static void
907 bnx2_report_fw_link(struct bnx2 *bp)
908 {
909 u32 fw_link_status = 0;
910
911 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
912 return;
913
914 if (bp->link_up) {
915 u32 bmsr;
916
917 switch (bp->line_speed) {
918 case SPEED_10:
919 if (bp->duplex == DUPLEX_HALF)
920 fw_link_status = BNX2_LINK_STATUS_10HALF;
921 else
922 fw_link_status = BNX2_LINK_STATUS_10FULL;
923 break;
924 case SPEED_100:
925 if (bp->duplex == DUPLEX_HALF)
926 fw_link_status = BNX2_LINK_STATUS_100HALF;
927 else
928 fw_link_status = BNX2_LINK_STATUS_100FULL;
929 break;
930 case SPEED_1000:
931 if (bp->duplex == DUPLEX_HALF)
932 fw_link_status = BNX2_LINK_STATUS_1000HALF;
933 else
934 fw_link_status = BNX2_LINK_STATUS_1000FULL;
935 break;
936 case SPEED_2500:
937 if (bp->duplex == DUPLEX_HALF)
938 fw_link_status = BNX2_LINK_STATUS_2500HALF;
939 else
940 fw_link_status = BNX2_LINK_STATUS_2500FULL;
941 break;
942 }
943
944 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
945
946 if (bp->autoneg) {
947 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
948
949 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
950 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
951
952 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
953 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
954 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
955 else
956 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
957 }
958 }
959 else
960 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
961
962 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
963 }
964
965 static char *
966 bnx2_xceiver_str(struct bnx2 *bp)
967 {
968 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
969 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
970 "Copper"));
971 }
972
973 static void
974 bnx2_report_link(struct bnx2 *bp)
975 {
976 if (bp->link_up) {
977 netif_carrier_on(bp->dev);
978 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
979 bnx2_xceiver_str(bp));
980
981 printk("%d Mbps ", bp->line_speed);
982
983 if (bp->duplex == DUPLEX_FULL)
984 printk("full duplex");
985 else
986 printk("half duplex");
987
988 if (bp->flow_ctrl) {
989 if (bp->flow_ctrl & FLOW_CTRL_RX) {
990 printk(", receive ");
991 if (bp->flow_ctrl & FLOW_CTRL_TX)
992 printk("& transmit ");
993 }
994 else {
995 printk(", transmit ");
996 }
997 printk("flow control ON");
998 }
999 printk("\n");
1000 }
1001 else {
1002 netif_carrier_off(bp->dev);
1003 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
1004 bnx2_xceiver_str(bp));
1005 }
1006
1007 bnx2_report_fw_link(bp);
1008 }
1009
1010 static void
1011 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1012 {
1013 u32 local_adv, remote_adv;
1014
1015 bp->flow_ctrl = 0;
1016 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1017 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1018
1019 if (bp->duplex == DUPLEX_FULL) {
1020 bp->flow_ctrl = bp->req_flow_ctrl;
1021 }
1022 return;
1023 }
1024
1025 if (bp->duplex != DUPLEX_FULL) {
1026 return;
1027 }
1028
1029 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1030 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1031 u32 val;
1032
1033 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1034 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1035 bp->flow_ctrl |= FLOW_CTRL_TX;
1036 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1037 bp->flow_ctrl |= FLOW_CTRL_RX;
1038 return;
1039 }
1040
1041 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1042 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1043
1044 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1045 u32 new_local_adv = 0;
1046 u32 new_remote_adv = 0;
1047
1048 if (local_adv & ADVERTISE_1000XPAUSE)
1049 new_local_adv |= ADVERTISE_PAUSE_CAP;
1050 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1051 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1052 if (remote_adv & ADVERTISE_1000XPAUSE)
1053 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1054 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1055 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1056
1057 local_adv = new_local_adv;
1058 remote_adv = new_remote_adv;
1059 }
1060
1061 /* See Table 28B-3 of 802.3ab-1999 spec. */
1062 if (local_adv & ADVERTISE_PAUSE_CAP) {
1063 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1064 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1065 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1066 }
1067 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1068 bp->flow_ctrl = FLOW_CTRL_RX;
1069 }
1070 }
1071 else {
1072 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1073 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1074 }
1075 }
1076 }
1077 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1078 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1079 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1080
1081 bp->flow_ctrl = FLOW_CTRL_TX;
1082 }
1083 }
1084 }
1085
1086 static int
1087 bnx2_5709s_linkup(struct bnx2 *bp)
1088 {
1089 u32 val, speed;
1090
1091 bp->link_up = 1;
1092
1093 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1094 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1095 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1096
1097 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1098 bp->line_speed = bp->req_line_speed;
1099 bp->duplex = bp->req_duplex;
1100 return 0;
1101 }
1102 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1103 switch (speed) {
1104 case MII_BNX2_GP_TOP_AN_SPEED_10:
1105 bp->line_speed = SPEED_10;
1106 break;
1107 case MII_BNX2_GP_TOP_AN_SPEED_100:
1108 bp->line_speed = SPEED_100;
1109 break;
1110 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1111 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1112 bp->line_speed = SPEED_1000;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1115 bp->line_speed = SPEED_2500;
1116 break;
1117 }
1118 if (val & MII_BNX2_GP_TOP_AN_FD)
1119 bp->duplex = DUPLEX_FULL;
1120 else
1121 bp->duplex = DUPLEX_HALF;
1122 return 0;
1123 }
1124
1125 static int
1126 bnx2_5708s_linkup(struct bnx2 *bp)
1127 {
1128 u32 val;
1129
1130 bp->link_up = 1;
1131 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1132 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1133 case BCM5708S_1000X_STAT1_SPEED_10:
1134 bp->line_speed = SPEED_10;
1135 break;
1136 case BCM5708S_1000X_STAT1_SPEED_100:
1137 bp->line_speed = SPEED_100;
1138 break;
1139 case BCM5708S_1000X_STAT1_SPEED_1G:
1140 bp->line_speed = SPEED_1000;
1141 break;
1142 case BCM5708S_1000X_STAT1_SPEED_2G5:
1143 bp->line_speed = SPEED_2500;
1144 break;
1145 }
1146 if (val & BCM5708S_1000X_STAT1_FD)
1147 bp->duplex = DUPLEX_FULL;
1148 else
1149 bp->duplex = DUPLEX_HALF;
1150
1151 return 0;
1152 }
1153
1154 static int
1155 bnx2_5706s_linkup(struct bnx2 *bp)
1156 {
1157 u32 bmcr, local_adv, remote_adv, common;
1158
1159 bp->link_up = 1;
1160 bp->line_speed = SPEED_1000;
1161
1162 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1163 if (bmcr & BMCR_FULLDPLX) {
1164 bp->duplex = DUPLEX_FULL;
1165 }
1166 else {
1167 bp->duplex = DUPLEX_HALF;
1168 }
1169
1170 if (!(bmcr & BMCR_ANENABLE)) {
1171 return 0;
1172 }
1173
1174 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1175 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1176
1177 common = local_adv & remote_adv;
1178 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1179
1180 if (common & ADVERTISE_1000XFULL) {
1181 bp->duplex = DUPLEX_FULL;
1182 }
1183 else {
1184 bp->duplex = DUPLEX_HALF;
1185 }
1186 }
1187
1188 return 0;
1189 }
1190
1191 static int
1192 bnx2_copper_linkup(struct bnx2 *bp)
1193 {
1194 u32 bmcr;
1195
1196 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1197 if (bmcr & BMCR_ANENABLE) {
1198 u32 local_adv, remote_adv, common;
1199
1200 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1201 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1202
1203 common = local_adv & (remote_adv >> 2);
1204 if (common & ADVERTISE_1000FULL) {
1205 bp->line_speed = SPEED_1000;
1206 bp->duplex = DUPLEX_FULL;
1207 }
1208 else if (common & ADVERTISE_1000HALF) {
1209 bp->line_speed = SPEED_1000;
1210 bp->duplex = DUPLEX_HALF;
1211 }
1212 else {
1213 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1214 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1215
1216 common = local_adv & remote_adv;
1217 if (common & ADVERTISE_100FULL) {
1218 bp->line_speed = SPEED_100;
1219 bp->duplex = DUPLEX_FULL;
1220 }
1221 else if (common & ADVERTISE_100HALF) {
1222 bp->line_speed = SPEED_100;
1223 bp->duplex = DUPLEX_HALF;
1224 }
1225 else if (common & ADVERTISE_10FULL) {
1226 bp->line_speed = SPEED_10;
1227 bp->duplex = DUPLEX_FULL;
1228 }
1229 else if (common & ADVERTISE_10HALF) {
1230 bp->line_speed = SPEED_10;
1231 bp->duplex = DUPLEX_HALF;
1232 }
1233 else {
1234 bp->line_speed = 0;
1235 bp->link_up = 0;
1236 }
1237 }
1238 }
1239 else {
1240 if (bmcr & BMCR_SPEED100) {
1241 bp->line_speed = SPEED_100;
1242 }
1243 else {
1244 bp->line_speed = SPEED_10;
1245 }
1246 if (bmcr & BMCR_FULLDPLX) {
1247 bp->duplex = DUPLEX_FULL;
1248 }
1249 else {
1250 bp->duplex = DUPLEX_HALF;
1251 }
1252 }
1253
1254 return 0;
1255 }
1256
1257 static void
1258 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1259 {
1260 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1261
1262 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1263 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1264 val |= 0x02 << 8;
1265
1266 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1267 u32 lo_water, hi_water;
1268
1269 if (bp->flow_ctrl & FLOW_CTRL_TX)
1270 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1271 else
1272 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1273 if (lo_water >= bp->rx_ring_size)
1274 lo_water = 0;
1275
1276 hi_water = bp->rx_ring_size / 4;
1277
1278 if (hi_water <= lo_water)
1279 lo_water = 0;
1280
1281 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1282 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1283
1284 if (hi_water > 0xf)
1285 hi_water = 0xf;
1286 else if (hi_water == 0)
1287 lo_water = 0;
1288 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1289 }
1290 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1291 }
1292
1293 static void
1294 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1295 {
1296 int i;
1297 u32 cid;
1298
1299 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1300 if (i == 1)
1301 cid = RX_RSS_CID;
1302 bnx2_init_rx_context(bp, cid);
1303 }
1304 }
1305
1306 static void
1307 bnx2_set_mac_link(struct bnx2 *bp)
1308 {
1309 u32 val;
1310
1311 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1312 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1313 (bp->duplex == DUPLEX_HALF)) {
1314 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1315 }
1316
1317 /* Configure the EMAC mode register. */
1318 val = REG_RD(bp, BNX2_EMAC_MODE);
1319
1320 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1321 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1322 BNX2_EMAC_MODE_25G_MODE);
1323
1324 if (bp->link_up) {
1325 switch (bp->line_speed) {
1326 case SPEED_10:
1327 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1328 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1329 break;
1330 }
1331 /* fall through */
1332 case SPEED_100:
1333 val |= BNX2_EMAC_MODE_PORT_MII;
1334 break;
1335 case SPEED_2500:
1336 val |= BNX2_EMAC_MODE_25G_MODE;
1337 /* fall through */
1338 case SPEED_1000:
1339 val |= BNX2_EMAC_MODE_PORT_GMII;
1340 break;
1341 }
1342 }
1343 else {
1344 val |= BNX2_EMAC_MODE_PORT_GMII;
1345 }
1346
1347 /* Set the MAC to operate in the appropriate duplex mode. */
1348 if (bp->duplex == DUPLEX_HALF)
1349 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1350 REG_WR(bp, BNX2_EMAC_MODE, val);
1351
1352 /* Enable/disable rx PAUSE. */
1353 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1354
1355 if (bp->flow_ctrl & FLOW_CTRL_RX)
1356 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1357 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1358
1359 /* Enable/disable tx PAUSE. */
1360 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1361 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1362
1363 if (bp->flow_ctrl & FLOW_CTRL_TX)
1364 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1365 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1366
1367 /* Acknowledge the interrupt. */
1368 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1369
1370 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1371 bnx2_init_all_rx_contexts(bp);
1372 }
1373
1374 static void
1375 bnx2_enable_bmsr1(struct bnx2 *bp)
1376 {
1377 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1378 (CHIP_NUM(bp) == CHIP_NUM_5709))
1379 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1380 MII_BNX2_BLK_ADDR_GP_STATUS);
1381 }
1382
1383 static void
1384 bnx2_disable_bmsr1(struct bnx2 *bp)
1385 {
1386 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1387 (CHIP_NUM(bp) == CHIP_NUM_5709))
1388 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1389 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1390 }
1391
1392 static int
1393 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1394 {
1395 u32 up1;
1396 int ret = 1;
1397
1398 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1399 return 0;
1400
1401 if (bp->autoneg & AUTONEG_SPEED)
1402 bp->advertising |= ADVERTISED_2500baseX_Full;
1403
1404 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1405 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1406
1407 bnx2_read_phy(bp, bp->mii_up1, &up1);
1408 if (!(up1 & BCM5708S_UP1_2G5)) {
1409 up1 |= BCM5708S_UP1_2G5;
1410 bnx2_write_phy(bp, bp->mii_up1, up1);
1411 ret = 0;
1412 }
1413
1414 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1415 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1416 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1417
1418 return ret;
1419 }
1420
1421 static int
1422 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1423 {
1424 u32 up1;
1425 int ret = 0;
1426
1427 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1428 return 0;
1429
1430 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1431 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1432
1433 bnx2_read_phy(bp, bp->mii_up1, &up1);
1434 if (up1 & BCM5708S_UP1_2G5) {
1435 up1 &= ~BCM5708S_UP1_2G5;
1436 bnx2_write_phy(bp, bp->mii_up1, up1);
1437 ret = 1;
1438 }
1439
1440 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1441 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1442 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1443
1444 return ret;
1445 }
1446
1447 static void
1448 bnx2_enable_forced_2g5(struct bnx2 *bp)
1449 {
1450 u32 bmcr;
1451
1452 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1453 return;
1454
1455 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1456 u32 val;
1457
1458 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1459 MII_BNX2_BLK_ADDR_SERDES_DIG);
1460 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1461 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1462 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1463 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1464
1465 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1466 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1467 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1468
1469 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1470 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1471 bmcr |= BCM5708S_BMCR_FORCE_2500;
1472 }
1473
1474 if (bp->autoneg & AUTONEG_SPEED) {
1475 bmcr &= ~BMCR_ANENABLE;
1476 if (bp->req_duplex == DUPLEX_FULL)
1477 bmcr |= BMCR_FULLDPLX;
1478 }
1479 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1480 }
1481
1482 static void
1483 bnx2_disable_forced_2g5(struct bnx2 *bp)
1484 {
1485 u32 bmcr;
1486
1487 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1488 return;
1489
1490 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1491 u32 val;
1492
1493 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1494 MII_BNX2_BLK_ADDR_SERDES_DIG);
1495 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1496 val &= ~MII_BNX2_SD_MISC1_FORCE;
1497 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1498
1499 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1500 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1501 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1502
1503 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1504 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1505 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1506 }
1507
1508 if (bp->autoneg & AUTONEG_SPEED)
1509 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1510 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1511 }
1512
1513 static void
1514 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1515 {
1516 u32 val;
1517
1518 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1519 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1520 if (start)
1521 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1522 else
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1524 }
1525
1526 static int
1527 bnx2_set_link(struct bnx2 *bp)
1528 {
1529 u32 bmsr;
1530 u8 link_up;
1531
1532 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1533 bp->link_up = 1;
1534 return 0;
1535 }
1536
1537 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1538 return 0;
1539
1540 link_up = bp->link_up;
1541
1542 bnx2_enable_bmsr1(bp);
1543 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1544 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1545 bnx2_disable_bmsr1(bp);
1546
1547 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1548 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1549 u32 val, an_dbg;
1550
1551 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1552 bnx2_5706s_force_link_dn(bp, 0);
1553 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1554 }
1555 val = REG_RD(bp, BNX2_EMAC_STATUS);
1556
1557 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1558 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1559 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1560
1561 if ((val & BNX2_EMAC_STATUS_LINK) &&
1562 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1563 bmsr |= BMSR_LSTATUS;
1564 else
1565 bmsr &= ~BMSR_LSTATUS;
1566 }
1567
1568 if (bmsr & BMSR_LSTATUS) {
1569 bp->link_up = 1;
1570
1571 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1572 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1573 bnx2_5706s_linkup(bp);
1574 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1575 bnx2_5708s_linkup(bp);
1576 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1577 bnx2_5709s_linkup(bp);
1578 }
1579 else {
1580 bnx2_copper_linkup(bp);
1581 }
1582 bnx2_resolve_flow_ctrl(bp);
1583 }
1584 else {
1585 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1586 (bp->autoneg & AUTONEG_SPEED))
1587 bnx2_disable_forced_2g5(bp);
1588
1589 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1590 u32 bmcr;
1591
1592 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1593 bmcr |= BMCR_ANENABLE;
1594 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1595
1596 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1597 }
1598 bp->link_up = 0;
1599 }
1600
1601 if (bp->link_up != link_up) {
1602 bnx2_report_link(bp);
1603 }
1604
1605 bnx2_set_mac_link(bp);
1606
1607 return 0;
1608 }
1609
1610 static int
1611 bnx2_reset_phy(struct bnx2 *bp)
1612 {
1613 int i;
1614 u32 reg;
1615
1616 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1617
1618 #define PHY_RESET_MAX_WAIT 100
1619 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1620 udelay(10);
1621
1622 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1623 if (!(reg & BMCR_RESET)) {
1624 udelay(20);
1625 break;
1626 }
1627 }
1628 if (i == PHY_RESET_MAX_WAIT) {
1629 return -EBUSY;
1630 }
1631 return 0;
1632 }
1633
1634 static u32
1635 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1636 {
1637 u32 adv = 0;
1638
1639 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1640 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1641
1642 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1643 adv = ADVERTISE_1000XPAUSE;
1644 }
1645 else {
1646 adv = ADVERTISE_PAUSE_CAP;
1647 }
1648 }
1649 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1650 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1651 adv = ADVERTISE_1000XPSE_ASYM;
1652 }
1653 else {
1654 adv = ADVERTISE_PAUSE_ASYM;
1655 }
1656 }
1657 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1658 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1659 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1660 }
1661 else {
1662 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1663 }
1664 }
1665 return adv;
1666 }
1667
1668 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1669
1670 static int
1671 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1672 __releases(&bp->phy_lock)
1673 __acquires(&bp->phy_lock)
1674 {
1675 u32 speed_arg = 0, pause_adv;
1676
1677 pause_adv = bnx2_phy_get_pause_adv(bp);
1678
1679 if (bp->autoneg & AUTONEG_SPEED) {
1680 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1681 if (bp->advertising & ADVERTISED_10baseT_Half)
1682 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1683 if (bp->advertising & ADVERTISED_10baseT_Full)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1685 if (bp->advertising & ADVERTISED_100baseT_Half)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1687 if (bp->advertising & ADVERTISED_100baseT_Full)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1689 if (bp->advertising & ADVERTISED_1000baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1691 if (bp->advertising & ADVERTISED_2500baseX_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1693 } else {
1694 if (bp->req_line_speed == SPEED_2500)
1695 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1696 else if (bp->req_line_speed == SPEED_1000)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1698 else if (bp->req_line_speed == SPEED_100) {
1699 if (bp->req_duplex == DUPLEX_FULL)
1700 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1701 else
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1703 } else if (bp->req_line_speed == SPEED_10) {
1704 if (bp->req_duplex == DUPLEX_FULL)
1705 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1706 else
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1708 }
1709 }
1710
1711 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1712 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1713 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1715
1716 if (port == PORT_TP)
1717 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1718 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1719
1720 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1721
1722 spin_unlock_bh(&bp->phy_lock);
1723 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1724 spin_lock_bh(&bp->phy_lock);
1725
1726 return 0;
1727 }
1728
1729 static int
1730 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1731 __releases(&bp->phy_lock)
1732 __acquires(&bp->phy_lock)
1733 {
1734 u32 adv, bmcr;
1735 u32 new_adv = 0;
1736
1737 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1738 return (bnx2_setup_remote_phy(bp, port));
1739
1740 if (!(bp->autoneg & AUTONEG_SPEED)) {
1741 u32 new_bmcr;
1742 int force_link_down = 0;
1743
1744 if (bp->req_line_speed == SPEED_2500) {
1745 if (!bnx2_test_and_enable_2g5(bp))
1746 force_link_down = 1;
1747 } else if (bp->req_line_speed == SPEED_1000) {
1748 if (bnx2_test_and_disable_2g5(bp))
1749 force_link_down = 1;
1750 }
1751 bnx2_read_phy(bp, bp->mii_adv, &adv);
1752 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1753
1754 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1755 new_bmcr = bmcr & ~BMCR_ANENABLE;
1756 new_bmcr |= BMCR_SPEED1000;
1757
1758 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1759 if (bp->req_line_speed == SPEED_2500)
1760 bnx2_enable_forced_2g5(bp);
1761 else if (bp->req_line_speed == SPEED_1000) {
1762 bnx2_disable_forced_2g5(bp);
1763 new_bmcr &= ~0x2000;
1764 }
1765
1766 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1767 if (bp->req_line_speed == SPEED_2500)
1768 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1769 else
1770 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1771 }
1772
1773 if (bp->req_duplex == DUPLEX_FULL) {
1774 adv |= ADVERTISE_1000XFULL;
1775 new_bmcr |= BMCR_FULLDPLX;
1776 }
1777 else {
1778 adv |= ADVERTISE_1000XHALF;
1779 new_bmcr &= ~BMCR_FULLDPLX;
1780 }
1781 if ((new_bmcr != bmcr) || (force_link_down)) {
1782 /* Force a link down visible on the other side */
1783 if (bp->link_up) {
1784 bnx2_write_phy(bp, bp->mii_adv, adv &
1785 ~(ADVERTISE_1000XFULL |
1786 ADVERTISE_1000XHALF));
1787 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1788 BMCR_ANRESTART | BMCR_ANENABLE);
1789
1790 bp->link_up = 0;
1791 netif_carrier_off(bp->dev);
1792 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1793 bnx2_report_link(bp);
1794 }
1795 bnx2_write_phy(bp, bp->mii_adv, adv);
1796 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1797 } else {
1798 bnx2_resolve_flow_ctrl(bp);
1799 bnx2_set_mac_link(bp);
1800 }
1801 return 0;
1802 }
1803
1804 bnx2_test_and_enable_2g5(bp);
1805
1806 if (bp->advertising & ADVERTISED_1000baseT_Full)
1807 new_adv |= ADVERTISE_1000XFULL;
1808
1809 new_adv |= bnx2_phy_get_pause_adv(bp);
1810
1811 bnx2_read_phy(bp, bp->mii_adv, &adv);
1812 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1813
1814 bp->serdes_an_pending = 0;
1815 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1816 /* Force a link down visible on the other side */
1817 if (bp->link_up) {
1818 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1819 spin_unlock_bh(&bp->phy_lock);
1820 msleep(20);
1821 spin_lock_bh(&bp->phy_lock);
1822 }
1823
1824 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1825 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1826 BMCR_ANENABLE);
1827 /* Speed up link-up time when the link partner
1828 * does not autonegotiate which is very common
1829 * in blade servers. Some blade servers use
1830 * IPMI for kerboard input and it's important
1831 * to minimize link disruptions. Autoneg. involves
1832 * exchanging base pages plus 3 next pages and
1833 * normally completes in about 120 msec.
1834 */
1835 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1836 bp->serdes_an_pending = 1;
1837 mod_timer(&bp->timer, jiffies + bp->current_interval);
1838 } else {
1839 bnx2_resolve_flow_ctrl(bp);
1840 bnx2_set_mac_link(bp);
1841 }
1842
1843 return 0;
1844 }
1845
1846 #define ETHTOOL_ALL_FIBRE_SPEED \
1847 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1848 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1849 (ADVERTISED_1000baseT_Full)
1850
1851 #define ETHTOOL_ALL_COPPER_SPEED \
1852 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1853 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1854 ADVERTISED_1000baseT_Full)
1855
1856 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1857 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1858
1859 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1860
1861 static void
1862 bnx2_set_default_remote_link(struct bnx2 *bp)
1863 {
1864 u32 link;
1865
1866 if (bp->phy_port == PORT_TP)
1867 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1868 else
1869 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1870
1871 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1872 bp->req_line_speed = 0;
1873 bp->autoneg |= AUTONEG_SPEED;
1874 bp->advertising = ADVERTISED_Autoneg;
1875 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1876 bp->advertising |= ADVERTISED_10baseT_Half;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1878 bp->advertising |= ADVERTISED_10baseT_Full;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1880 bp->advertising |= ADVERTISED_100baseT_Half;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1882 bp->advertising |= ADVERTISED_100baseT_Full;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1884 bp->advertising |= ADVERTISED_1000baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1886 bp->advertising |= ADVERTISED_2500baseX_Full;
1887 } else {
1888 bp->autoneg = 0;
1889 bp->advertising = 0;
1890 bp->req_duplex = DUPLEX_FULL;
1891 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1892 bp->req_line_speed = SPEED_10;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1894 bp->req_duplex = DUPLEX_HALF;
1895 }
1896 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1897 bp->req_line_speed = SPEED_100;
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1899 bp->req_duplex = DUPLEX_HALF;
1900 }
1901 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1902 bp->req_line_speed = SPEED_1000;
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1904 bp->req_line_speed = SPEED_2500;
1905 }
1906 }
1907
1908 static void
1909 bnx2_set_default_link(struct bnx2 *bp)
1910 {
1911 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1912 bnx2_set_default_remote_link(bp);
1913 return;
1914 }
1915
1916 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1917 bp->req_line_speed = 0;
1918 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1919 u32 reg;
1920
1921 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1922
1923 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1924 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1925 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1926 bp->autoneg = 0;
1927 bp->req_line_speed = bp->line_speed = SPEED_1000;
1928 bp->req_duplex = DUPLEX_FULL;
1929 }
1930 } else
1931 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1932 }
1933
1934 static void
1935 bnx2_send_heart_beat(struct bnx2 *bp)
1936 {
1937 u32 msg;
1938 u32 addr;
1939
1940 spin_lock(&bp->indirect_lock);
1941 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1942 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1943 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1944 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1945 spin_unlock(&bp->indirect_lock);
1946 }
1947
1948 static void
1949 bnx2_remote_phy_event(struct bnx2 *bp)
1950 {
1951 u32 msg;
1952 u8 link_up = bp->link_up;
1953 u8 old_port;
1954
1955 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1956
1957 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1958 bnx2_send_heart_beat(bp);
1959
1960 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1961
1962 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1963 bp->link_up = 0;
1964 else {
1965 u32 speed;
1966
1967 bp->link_up = 1;
1968 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1969 bp->duplex = DUPLEX_FULL;
1970 switch (speed) {
1971 case BNX2_LINK_STATUS_10HALF:
1972 bp->duplex = DUPLEX_HALF;
1973 case BNX2_LINK_STATUS_10FULL:
1974 bp->line_speed = SPEED_10;
1975 break;
1976 case BNX2_LINK_STATUS_100HALF:
1977 bp->duplex = DUPLEX_HALF;
1978 case BNX2_LINK_STATUS_100BASE_T4:
1979 case BNX2_LINK_STATUS_100FULL:
1980 bp->line_speed = SPEED_100;
1981 break;
1982 case BNX2_LINK_STATUS_1000HALF:
1983 bp->duplex = DUPLEX_HALF;
1984 case BNX2_LINK_STATUS_1000FULL:
1985 bp->line_speed = SPEED_1000;
1986 break;
1987 case BNX2_LINK_STATUS_2500HALF:
1988 bp->duplex = DUPLEX_HALF;
1989 case BNX2_LINK_STATUS_2500FULL:
1990 bp->line_speed = SPEED_2500;
1991 break;
1992 default:
1993 bp->line_speed = 0;
1994 break;
1995 }
1996
1997 bp->flow_ctrl = 0;
1998 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1999 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2000 if (bp->duplex == DUPLEX_FULL)
2001 bp->flow_ctrl = bp->req_flow_ctrl;
2002 } else {
2003 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2004 bp->flow_ctrl |= FLOW_CTRL_TX;
2005 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2006 bp->flow_ctrl |= FLOW_CTRL_RX;
2007 }
2008
2009 old_port = bp->phy_port;
2010 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2011 bp->phy_port = PORT_FIBRE;
2012 else
2013 bp->phy_port = PORT_TP;
2014
2015 if (old_port != bp->phy_port)
2016 bnx2_set_default_link(bp);
2017
2018 }
2019 if (bp->link_up != link_up)
2020 bnx2_report_link(bp);
2021
2022 bnx2_set_mac_link(bp);
2023 }
2024
2025 static int
2026 bnx2_set_remote_link(struct bnx2 *bp)
2027 {
2028 u32 evt_code;
2029
2030 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2031 switch (evt_code) {
2032 case BNX2_FW_EVT_CODE_LINK_EVENT:
2033 bnx2_remote_phy_event(bp);
2034 break;
2035 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2036 default:
2037 bnx2_send_heart_beat(bp);
2038 break;
2039 }
2040 return 0;
2041 }
2042
2043 static int
2044 bnx2_setup_copper_phy(struct bnx2 *bp)
2045 __releases(&bp->phy_lock)
2046 __acquires(&bp->phy_lock)
2047 {
2048 u32 bmcr;
2049 u32 new_bmcr;
2050
2051 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2052
2053 if (bp->autoneg & AUTONEG_SPEED) {
2054 u32 adv_reg, adv1000_reg;
2055 u32 new_adv_reg = 0;
2056 u32 new_adv1000_reg = 0;
2057
2058 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2059 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2060 ADVERTISE_PAUSE_ASYM);
2061
2062 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2063 adv1000_reg &= PHY_ALL_1000_SPEED;
2064
2065 if (bp->advertising & ADVERTISED_10baseT_Half)
2066 new_adv_reg |= ADVERTISE_10HALF;
2067 if (bp->advertising & ADVERTISED_10baseT_Full)
2068 new_adv_reg |= ADVERTISE_10FULL;
2069 if (bp->advertising & ADVERTISED_100baseT_Half)
2070 new_adv_reg |= ADVERTISE_100HALF;
2071 if (bp->advertising & ADVERTISED_100baseT_Full)
2072 new_adv_reg |= ADVERTISE_100FULL;
2073 if (bp->advertising & ADVERTISED_1000baseT_Full)
2074 new_adv1000_reg |= ADVERTISE_1000FULL;
2075
2076 new_adv_reg |= ADVERTISE_CSMA;
2077
2078 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2079
2080 if ((adv1000_reg != new_adv1000_reg) ||
2081 (adv_reg != new_adv_reg) ||
2082 ((bmcr & BMCR_ANENABLE) == 0)) {
2083
2084 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2085 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2086 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2087 BMCR_ANENABLE);
2088 }
2089 else if (bp->link_up) {
2090 /* Flow ctrl may have changed from auto to forced */
2091 /* or vice-versa. */
2092
2093 bnx2_resolve_flow_ctrl(bp);
2094 bnx2_set_mac_link(bp);
2095 }
2096 return 0;
2097 }
2098
2099 new_bmcr = 0;
2100 if (bp->req_line_speed == SPEED_100) {
2101 new_bmcr |= BMCR_SPEED100;
2102 }
2103 if (bp->req_duplex == DUPLEX_FULL) {
2104 new_bmcr |= BMCR_FULLDPLX;
2105 }
2106 if (new_bmcr != bmcr) {
2107 u32 bmsr;
2108
2109 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2110 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2111
2112 if (bmsr & BMSR_LSTATUS) {
2113 /* Force link down */
2114 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2115 spin_unlock_bh(&bp->phy_lock);
2116 msleep(50);
2117 spin_lock_bh(&bp->phy_lock);
2118
2119 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2120 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2121 }
2122
2123 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2124
2125 /* Normally, the new speed is setup after the link has
2126 * gone down and up again. In some cases, link will not go
2127 * down so we need to set up the new speed here.
2128 */
2129 if (bmsr & BMSR_LSTATUS) {
2130 bp->line_speed = bp->req_line_speed;
2131 bp->duplex = bp->req_duplex;
2132 bnx2_resolve_flow_ctrl(bp);
2133 bnx2_set_mac_link(bp);
2134 }
2135 } else {
2136 bnx2_resolve_flow_ctrl(bp);
2137 bnx2_set_mac_link(bp);
2138 }
2139 return 0;
2140 }
2141
2142 static int
2143 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2144 __releases(&bp->phy_lock)
2145 __acquires(&bp->phy_lock)
2146 {
2147 if (bp->loopback == MAC_LOOPBACK)
2148 return 0;
2149
2150 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2151 return (bnx2_setup_serdes_phy(bp, port));
2152 }
2153 else {
2154 return (bnx2_setup_copper_phy(bp));
2155 }
2156 }
2157
2158 static int
2159 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2160 {
2161 u32 val;
2162
2163 bp->mii_bmcr = MII_BMCR + 0x10;
2164 bp->mii_bmsr = MII_BMSR + 0x10;
2165 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2166 bp->mii_adv = MII_ADVERTISE + 0x10;
2167 bp->mii_lpa = MII_LPA + 0x10;
2168 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2169
2170 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2171 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2172
2173 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2174 if (reset_phy)
2175 bnx2_reset_phy(bp);
2176
2177 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2178
2179 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2180 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2181 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2182 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2183
2184 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2185 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2186 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2187 val |= BCM5708S_UP1_2G5;
2188 else
2189 val &= ~BCM5708S_UP1_2G5;
2190 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2191
2192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2193 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2194 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2195 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2196
2197 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2198
2199 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2200 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2201 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2202
2203 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2204
2205 return 0;
2206 }
2207
2208 static int
2209 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2210 {
2211 u32 val;
2212
2213 if (reset_phy)
2214 bnx2_reset_phy(bp);
2215
2216 bp->mii_up1 = BCM5708S_UP1;
2217
2218 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2219 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2220 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2221
2222 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2223 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2224 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2225
2226 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2227 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2228 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2229
2230 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2231 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2232 val |= BCM5708S_UP1_2G5;
2233 bnx2_write_phy(bp, BCM5708S_UP1, val);
2234 }
2235
2236 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2237 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2238 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2239 /* increase tx signal amplitude */
2240 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2241 BCM5708S_BLK_ADDR_TX_MISC);
2242 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2243 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2244 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2245 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2246 }
2247
2248 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2249 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2250
2251 if (val) {
2252 u32 is_backplane;
2253
2254 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2255 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2256 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2257 BCM5708S_BLK_ADDR_TX_MISC);
2258 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2259 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2260 BCM5708S_BLK_ADDR_DIG);
2261 }
2262 }
2263 return 0;
2264 }
2265
2266 static int
2267 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2268 {
2269 if (reset_phy)
2270 bnx2_reset_phy(bp);
2271
2272 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2273
2274 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2275 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2276
2277 if (bp->dev->mtu > 1500) {
2278 u32 val;
2279
2280 /* Set extended packet length bit */
2281 bnx2_write_phy(bp, 0x18, 0x7);
2282 bnx2_read_phy(bp, 0x18, &val);
2283 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2284
2285 bnx2_write_phy(bp, 0x1c, 0x6c00);
2286 bnx2_read_phy(bp, 0x1c, &val);
2287 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2288 }
2289 else {
2290 u32 val;
2291
2292 bnx2_write_phy(bp, 0x18, 0x7);
2293 bnx2_read_phy(bp, 0x18, &val);
2294 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2295
2296 bnx2_write_phy(bp, 0x1c, 0x6c00);
2297 bnx2_read_phy(bp, 0x1c, &val);
2298 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2299 }
2300
2301 return 0;
2302 }
2303
2304 static int
2305 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2306 {
2307 u32 val;
2308
2309 if (reset_phy)
2310 bnx2_reset_phy(bp);
2311
2312 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2313 bnx2_write_phy(bp, 0x18, 0x0c00);
2314 bnx2_write_phy(bp, 0x17, 0x000a);
2315 bnx2_write_phy(bp, 0x15, 0x310b);
2316 bnx2_write_phy(bp, 0x17, 0x201f);
2317 bnx2_write_phy(bp, 0x15, 0x9506);
2318 bnx2_write_phy(bp, 0x17, 0x401f);
2319 bnx2_write_phy(bp, 0x15, 0x14e2);
2320 bnx2_write_phy(bp, 0x18, 0x0400);
2321 }
2322
2323 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2324 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2325 MII_BNX2_DSP_EXPAND_REG | 0x8);
2326 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2327 val &= ~(1 << 8);
2328 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2329 }
2330
2331 if (bp->dev->mtu > 1500) {
2332 /* Set extended packet length bit */
2333 bnx2_write_phy(bp, 0x18, 0x7);
2334 bnx2_read_phy(bp, 0x18, &val);
2335 bnx2_write_phy(bp, 0x18, val | 0x4000);
2336
2337 bnx2_read_phy(bp, 0x10, &val);
2338 bnx2_write_phy(bp, 0x10, val | 0x1);
2339 }
2340 else {
2341 bnx2_write_phy(bp, 0x18, 0x7);
2342 bnx2_read_phy(bp, 0x18, &val);
2343 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2344
2345 bnx2_read_phy(bp, 0x10, &val);
2346 bnx2_write_phy(bp, 0x10, val & ~0x1);
2347 }
2348
2349 /* ethernet@wirespeed */
2350 bnx2_write_phy(bp, 0x18, 0x7007);
2351 bnx2_read_phy(bp, 0x18, &val);
2352 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2353 return 0;
2354 }
2355
2356
2357 static int
2358 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2359 __releases(&bp->phy_lock)
2360 __acquires(&bp->phy_lock)
2361 {
2362 u32 val;
2363 int rc = 0;
2364
2365 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2366 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2367
2368 bp->mii_bmcr = MII_BMCR;
2369 bp->mii_bmsr = MII_BMSR;
2370 bp->mii_bmsr1 = MII_BMSR;
2371 bp->mii_adv = MII_ADVERTISE;
2372 bp->mii_lpa = MII_LPA;
2373
2374 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2375
2376 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2377 goto setup_phy;
2378
2379 bnx2_read_phy(bp, MII_PHYSID1, &val);
2380 bp->phy_id = val << 16;
2381 bnx2_read_phy(bp, MII_PHYSID2, &val);
2382 bp->phy_id |= val & 0xffff;
2383
2384 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2385 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2386 rc = bnx2_init_5706s_phy(bp, reset_phy);
2387 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2388 rc = bnx2_init_5708s_phy(bp, reset_phy);
2389 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2390 rc = bnx2_init_5709s_phy(bp, reset_phy);
2391 }
2392 else {
2393 rc = bnx2_init_copper_phy(bp, reset_phy);
2394 }
2395
2396 setup_phy:
2397 if (!rc)
2398 rc = bnx2_setup_phy(bp, bp->phy_port);
2399
2400 return rc;
2401 }
2402
2403 static int
2404 bnx2_set_mac_loopback(struct bnx2 *bp)
2405 {
2406 u32 mac_mode;
2407
2408 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2409 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2410 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2411 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2412 bp->link_up = 1;
2413 return 0;
2414 }
2415
2416 static int bnx2_test_link(struct bnx2 *);
2417
2418 static int
2419 bnx2_set_phy_loopback(struct bnx2 *bp)
2420 {
2421 u32 mac_mode;
2422 int rc, i;
2423
2424 spin_lock_bh(&bp->phy_lock);
2425 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2426 BMCR_SPEED1000);
2427 spin_unlock_bh(&bp->phy_lock);
2428 if (rc)
2429 return rc;
2430
2431 for (i = 0; i < 10; i++) {
2432 if (bnx2_test_link(bp) == 0)
2433 break;
2434 msleep(100);
2435 }
2436
2437 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2438 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2439 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2440 BNX2_EMAC_MODE_25G_MODE);
2441
2442 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2443 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2444 bp->link_up = 1;
2445 return 0;
2446 }
2447
2448 static int
2449 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2450 {
2451 int i;
2452 u32 val;
2453
2454 bp->fw_wr_seq++;
2455 msg_data |= bp->fw_wr_seq;
2456
2457 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2458
2459 if (!ack)
2460 return 0;
2461
2462 /* wait for an acknowledgement. */
2463 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2464 msleep(10);
2465
2466 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2467
2468 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2469 break;
2470 }
2471 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2472 return 0;
2473
2474 /* If we timed out, inform the firmware that this is the case. */
2475 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2476 if (!silent)
2477 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2478 "%x\n", msg_data);
2479
2480 msg_data &= ~BNX2_DRV_MSG_CODE;
2481 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2482
2483 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2484
2485 return -EBUSY;
2486 }
2487
2488 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2489 return -EIO;
2490
2491 return 0;
2492 }
2493
2494 static int
2495 bnx2_init_5709_context(struct bnx2 *bp)
2496 {
2497 int i, ret = 0;
2498 u32 val;
2499
2500 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2501 val |= (BCM_PAGE_BITS - 8) << 16;
2502 REG_WR(bp, BNX2_CTX_COMMAND, val);
2503 for (i = 0; i < 10; i++) {
2504 val = REG_RD(bp, BNX2_CTX_COMMAND);
2505 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2506 break;
2507 udelay(2);
2508 }
2509 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2510 return -EBUSY;
2511
2512 for (i = 0; i < bp->ctx_pages; i++) {
2513 int j;
2514
2515 if (bp->ctx_blk[i])
2516 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2517 else
2518 return -ENOMEM;
2519
2520 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2521 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2522 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2523 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2524 (u64) bp->ctx_blk_mapping[i] >> 32);
2525 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2526 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2527 for (j = 0; j < 10; j++) {
2528
2529 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2530 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2531 break;
2532 udelay(5);
2533 }
2534 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2535 ret = -EBUSY;
2536 break;
2537 }
2538 }
2539 return ret;
2540 }
2541
2542 static void
2543 bnx2_init_context(struct bnx2 *bp)
2544 {
2545 u32 vcid;
2546
2547 vcid = 96;
2548 while (vcid) {
2549 u32 vcid_addr, pcid_addr, offset;
2550 int i;
2551
2552 vcid--;
2553
2554 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2555 u32 new_vcid;
2556
2557 vcid_addr = GET_PCID_ADDR(vcid);
2558 if (vcid & 0x8) {
2559 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2560 }
2561 else {
2562 new_vcid = vcid;
2563 }
2564 pcid_addr = GET_PCID_ADDR(new_vcid);
2565 }
2566 else {
2567 vcid_addr = GET_CID_ADDR(vcid);
2568 pcid_addr = vcid_addr;
2569 }
2570
2571 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2572 vcid_addr += (i << PHY_CTX_SHIFT);
2573 pcid_addr += (i << PHY_CTX_SHIFT);
2574
2575 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2576 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2577
2578 /* Zero out the context. */
2579 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2580 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2581 }
2582 }
2583 }
2584
2585 static int
2586 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2587 {
2588 u16 *good_mbuf;
2589 u32 good_mbuf_cnt;
2590 u32 val;
2591
2592 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2593 if (good_mbuf == NULL) {
2594 printk(KERN_ERR PFX "Failed to allocate memory in "
2595 "bnx2_alloc_bad_rbuf\n");
2596 return -ENOMEM;
2597 }
2598
2599 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2600 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2601
2602 good_mbuf_cnt = 0;
2603
2604 /* Allocate a bunch of mbufs and save the good ones in an array. */
2605 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2606 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2607 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2608 BNX2_RBUF_COMMAND_ALLOC_REQ);
2609
2610 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2611
2612 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2613
2614 /* The addresses with Bit 9 set are bad memory blocks. */
2615 if (!(val & (1 << 9))) {
2616 good_mbuf[good_mbuf_cnt] = (u16) val;
2617 good_mbuf_cnt++;
2618 }
2619
2620 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2621 }
2622
2623 /* Free the good ones back to the mbuf pool thus discarding
2624 * all the bad ones. */
2625 while (good_mbuf_cnt) {
2626 good_mbuf_cnt--;
2627
2628 val = good_mbuf[good_mbuf_cnt];
2629 val = (val << 9) | val | 1;
2630
2631 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2632 }
2633 kfree(good_mbuf);
2634 return 0;
2635 }
2636
2637 static void
2638 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2639 {
2640 u32 val;
2641
2642 val = (mac_addr[0] << 8) | mac_addr[1];
2643
2644 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2645
2646 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2647 (mac_addr[4] << 8) | mac_addr[5];
2648
2649 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2650 }
2651
2652 static inline int
2653 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2654 {
2655 dma_addr_t mapping;
2656 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2657 struct rx_bd *rxbd =
2658 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2659 struct page *page = alloc_page(GFP_ATOMIC);
2660
2661 if (!page)
2662 return -ENOMEM;
2663 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2664 PCI_DMA_FROMDEVICE);
2665 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2666 __free_page(page);
2667 return -EIO;
2668 }
2669
2670 rx_pg->page = page;
2671 pci_unmap_addr_set(rx_pg, mapping, mapping);
2672 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2673 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2674 return 0;
2675 }
2676
2677 static void
2678 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2679 {
2680 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2681 struct page *page = rx_pg->page;
2682
2683 if (!page)
2684 return;
2685
2686 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2687 PCI_DMA_FROMDEVICE);
2688
2689 __free_page(page);
2690 rx_pg->page = NULL;
2691 }
2692
2693 static inline int
2694 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2695 {
2696 struct sk_buff *skb;
2697 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2698 dma_addr_t mapping;
2699 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2700 unsigned long align;
2701
2702 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2703 if (skb == NULL) {
2704 return -ENOMEM;
2705 }
2706
2707 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2708 skb_reserve(skb, BNX2_RX_ALIGN - align);
2709
2710 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2711 PCI_DMA_FROMDEVICE);
2712 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2713 dev_kfree_skb(skb);
2714 return -EIO;
2715 }
2716
2717 rx_buf->skb = skb;
2718 pci_unmap_addr_set(rx_buf, mapping, mapping);
2719
2720 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2721 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2722
2723 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2724
2725 return 0;
2726 }
2727
2728 static int
2729 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2730 {
2731 struct status_block *sblk = bnapi->status_blk.msi;
2732 u32 new_link_state, old_link_state;
2733 int is_set = 1;
2734
2735 new_link_state = sblk->status_attn_bits & event;
2736 old_link_state = sblk->status_attn_bits_ack & event;
2737 if (new_link_state != old_link_state) {
2738 if (new_link_state)
2739 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2740 else
2741 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2742 } else
2743 is_set = 0;
2744
2745 return is_set;
2746 }
2747
2748 static void
2749 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2750 {
2751 spin_lock(&bp->phy_lock);
2752
2753 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2754 bnx2_set_link(bp);
2755 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2756 bnx2_set_remote_link(bp);
2757
2758 spin_unlock(&bp->phy_lock);
2759
2760 }
2761
2762 static inline u16
2763 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2764 {
2765 u16 cons;
2766
2767 /* Tell compiler that status block fields can change. */
2768 barrier();
2769 cons = *bnapi->hw_tx_cons_ptr;
2770 barrier();
2771 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2772 cons++;
2773 return cons;
2774 }
2775
2776 static int
2777 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2778 {
2779 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2780 u16 hw_cons, sw_cons, sw_ring_cons;
2781 int tx_pkt = 0, index;
2782 struct netdev_queue *txq;
2783
2784 index = (bnapi - bp->bnx2_napi);
2785 txq = netdev_get_tx_queue(bp->dev, index);
2786
2787 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2788 sw_cons = txr->tx_cons;
2789
2790 while (sw_cons != hw_cons) {
2791 struct sw_tx_bd *tx_buf;
2792 struct sk_buff *skb;
2793 int i, last;
2794
2795 sw_ring_cons = TX_RING_IDX(sw_cons);
2796
2797 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2798 skb = tx_buf->skb;
2799
2800 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2801 prefetch(&skb->end);
2802
2803 /* partial BD completions possible with TSO packets */
2804 if (tx_buf->is_gso) {
2805 u16 last_idx, last_ring_idx;
2806
2807 last_idx = sw_cons + tx_buf->nr_frags + 1;
2808 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2809 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2810 last_idx++;
2811 }
2812 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2813 break;
2814 }
2815 }
2816
2817 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2818
2819 tx_buf->skb = NULL;
2820 last = tx_buf->nr_frags;
2821
2822 for (i = 0; i < last; i++) {
2823 sw_cons = NEXT_TX_BD(sw_cons);
2824 }
2825
2826 sw_cons = NEXT_TX_BD(sw_cons);
2827
2828 dev_kfree_skb(skb);
2829 tx_pkt++;
2830 if (tx_pkt == budget)
2831 break;
2832
2833 if (hw_cons == sw_cons)
2834 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2835 }
2836
2837 txr->hw_tx_cons = hw_cons;
2838 txr->tx_cons = sw_cons;
2839
2840 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2841 * before checking for netif_tx_queue_stopped(). Without the
2842 * memory barrier, there is a small possibility that bnx2_start_xmit()
2843 * will miss it and cause the queue to be stopped forever.
2844 */
2845 smp_mb();
2846
2847 if (unlikely(netif_tx_queue_stopped(txq)) &&
2848 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2849 __netif_tx_lock(txq, smp_processor_id());
2850 if ((netif_tx_queue_stopped(txq)) &&
2851 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2852 netif_tx_wake_queue(txq);
2853 __netif_tx_unlock(txq);
2854 }
2855
2856 return tx_pkt;
2857 }
2858
2859 static void
2860 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2861 struct sk_buff *skb, int count)
2862 {
2863 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2864 struct rx_bd *cons_bd, *prod_bd;
2865 int i;
2866 u16 hw_prod, prod;
2867 u16 cons = rxr->rx_pg_cons;
2868
2869 cons_rx_pg = &rxr->rx_pg_ring[cons];
2870
2871 /* The caller was unable to allocate a new page to replace the
2872 * last one in the frags array, so we need to recycle that page
2873 * and then free the skb.
2874 */
2875 if (skb) {
2876 struct page *page;
2877 struct skb_shared_info *shinfo;
2878
2879 shinfo = skb_shinfo(skb);
2880 shinfo->nr_frags--;
2881 page = shinfo->frags[shinfo->nr_frags].page;
2882 shinfo->frags[shinfo->nr_frags].page = NULL;
2883
2884 cons_rx_pg->page = page;
2885 dev_kfree_skb(skb);
2886 }
2887
2888 hw_prod = rxr->rx_pg_prod;
2889
2890 for (i = 0; i < count; i++) {
2891 prod = RX_PG_RING_IDX(hw_prod);
2892
2893 prod_rx_pg = &rxr->rx_pg_ring[prod];
2894 cons_rx_pg = &rxr->rx_pg_ring[cons];
2895 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2896 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2897
2898 if (prod != cons) {
2899 prod_rx_pg->page = cons_rx_pg->page;
2900 cons_rx_pg->page = NULL;
2901 pci_unmap_addr_set(prod_rx_pg, mapping,
2902 pci_unmap_addr(cons_rx_pg, mapping));
2903
2904 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2905 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2906
2907 }
2908 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2909 hw_prod = NEXT_RX_BD(hw_prod);
2910 }
2911 rxr->rx_pg_prod = hw_prod;
2912 rxr->rx_pg_cons = cons;
2913 }
2914
2915 static inline void
2916 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2917 struct sk_buff *skb, u16 cons, u16 prod)
2918 {
2919 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2920 struct rx_bd *cons_bd, *prod_bd;
2921
2922 cons_rx_buf = &rxr->rx_buf_ring[cons];
2923 prod_rx_buf = &rxr->rx_buf_ring[prod];
2924
2925 pci_dma_sync_single_for_device(bp->pdev,
2926 pci_unmap_addr(cons_rx_buf, mapping),
2927 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2928
2929 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2930
2931 prod_rx_buf->skb = skb;
2932
2933 if (cons == prod)
2934 return;
2935
2936 pci_unmap_addr_set(prod_rx_buf, mapping,
2937 pci_unmap_addr(cons_rx_buf, mapping));
2938
2939 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2940 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2941 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2942 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2943 }
2944
2945 static int
2946 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2947 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2948 u32 ring_idx)
2949 {
2950 int err;
2951 u16 prod = ring_idx & 0xffff;
2952
2953 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2954 if (unlikely(err)) {
2955 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2956 if (hdr_len) {
2957 unsigned int raw_len = len + 4;
2958 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2959
2960 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2961 }
2962 return err;
2963 }
2964
2965 skb_reserve(skb, BNX2_RX_OFFSET);
2966 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2967 PCI_DMA_FROMDEVICE);
2968
2969 if (hdr_len == 0) {
2970 skb_put(skb, len);
2971 return 0;
2972 } else {
2973 unsigned int i, frag_len, frag_size, pages;
2974 struct sw_pg *rx_pg;
2975 u16 pg_cons = rxr->rx_pg_cons;
2976 u16 pg_prod = rxr->rx_pg_prod;
2977
2978 frag_size = len + 4 - hdr_len;
2979 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2980 skb_put(skb, hdr_len);
2981
2982 for (i = 0; i < pages; i++) {
2983 dma_addr_t mapping_old;
2984
2985 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2986 if (unlikely(frag_len <= 4)) {
2987 unsigned int tail = 4 - frag_len;
2988
2989 rxr->rx_pg_cons = pg_cons;
2990 rxr->rx_pg_prod = pg_prod;
2991 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2992 pages - i);
2993 skb->len -= tail;
2994 if (i == 0) {
2995 skb->tail -= tail;
2996 } else {
2997 skb_frag_t *frag =
2998 &skb_shinfo(skb)->frags[i - 1];
2999 frag->size -= tail;
3000 skb->data_len -= tail;
3001 skb->truesize -= tail;
3002 }
3003 return 0;
3004 }
3005 rx_pg = &rxr->rx_pg_ring[pg_cons];
3006
3007 /* Don't unmap yet. If we're unable to allocate a new
3008 * page, we need to recycle the page and the DMA addr.
3009 */
3010 mapping_old = pci_unmap_addr(rx_pg, mapping);
3011 if (i == pages - 1)
3012 frag_len -= 4;
3013
3014 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3015 rx_pg->page = NULL;
3016
3017 err = bnx2_alloc_rx_page(bp, rxr,
3018 RX_PG_RING_IDX(pg_prod));
3019 if (unlikely(err)) {
3020 rxr->rx_pg_cons = pg_cons;
3021 rxr->rx_pg_prod = pg_prod;
3022 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3023 pages - i);
3024 return err;
3025 }
3026
3027 pci_unmap_page(bp->pdev, mapping_old,
3028 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3029
3030 frag_size -= frag_len;
3031 skb->data_len += frag_len;
3032 skb->truesize += frag_len;
3033 skb->len += frag_len;
3034
3035 pg_prod = NEXT_RX_BD(pg_prod);
3036 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3037 }
3038 rxr->rx_pg_prod = pg_prod;
3039 rxr->rx_pg_cons = pg_cons;
3040 }
3041 return 0;
3042 }
3043
3044 static inline u16
3045 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3046 {
3047 u16 cons;
3048
3049 /* Tell compiler that status block fields can change. */
3050 barrier();
3051 cons = *bnapi->hw_rx_cons_ptr;
3052 barrier();
3053 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3054 cons++;
3055 return cons;
3056 }
3057
3058 static int
3059 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3060 {
3061 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3062 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3063 struct l2_fhdr *rx_hdr;
3064 int rx_pkt = 0, pg_ring_used = 0;
3065
3066 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3067 sw_cons = rxr->rx_cons;
3068 sw_prod = rxr->rx_prod;
3069
3070 /* Memory barrier necessary as speculative reads of the rx
3071 * buffer can be ahead of the index in the status block
3072 */
3073 rmb();
3074 while (sw_cons != hw_cons) {
3075 unsigned int len, hdr_len;
3076 u32 status;
3077 struct sw_bd *rx_buf;
3078 struct sk_buff *skb;
3079 dma_addr_t dma_addr;
3080 u16 vtag = 0;
3081 int hw_vlan __maybe_unused = 0;
3082
3083 sw_ring_cons = RX_RING_IDX(sw_cons);
3084 sw_ring_prod = RX_RING_IDX(sw_prod);
3085
3086 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3087 skb = rx_buf->skb;
3088
3089 rx_buf->skb = NULL;
3090
3091 dma_addr = pci_unmap_addr(rx_buf, mapping);
3092
3093 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3094 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3095 PCI_DMA_FROMDEVICE);
3096
3097 rx_hdr = (struct l2_fhdr *) skb->data;
3098 len = rx_hdr->l2_fhdr_pkt_len;
3099 status = rx_hdr->l2_fhdr_status;
3100
3101 hdr_len = 0;
3102 if (status & L2_FHDR_STATUS_SPLIT) {
3103 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3104 pg_ring_used = 1;
3105 } else if (len > bp->rx_jumbo_thresh) {
3106 hdr_len = bp->rx_jumbo_thresh;
3107 pg_ring_used = 1;
3108 }
3109
3110 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3111 L2_FHDR_ERRORS_PHY_DECODE |
3112 L2_FHDR_ERRORS_ALIGNMENT |
3113 L2_FHDR_ERRORS_TOO_SHORT |
3114 L2_FHDR_ERRORS_GIANT_FRAME))) {
3115
3116 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3117 sw_ring_prod);
3118 if (pg_ring_used) {
3119 int pages;
3120
3121 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3122
3123 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3124 }
3125 goto next_rx;
3126 }
3127
3128 len -= 4;
3129
3130 if (len <= bp->rx_copy_thresh) {
3131 struct sk_buff *new_skb;
3132
3133 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3134 if (new_skb == NULL) {
3135 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3136 sw_ring_prod);
3137 goto next_rx;
3138 }
3139
3140 /* aligned copy */
3141 skb_copy_from_linear_data_offset(skb,
3142 BNX2_RX_OFFSET - 6,
3143 new_skb->data, len + 6);
3144 skb_reserve(new_skb, 6);
3145 skb_put(new_skb, len);
3146
3147 bnx2_reuse_rx_skb(bp, rxr, skb,
3148 sw_ring_cons, sw_ring_prod);
3149
3150 skb = new_skb;
3151 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3152 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3153 goto next_rx;
3154
3155 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3156 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3157 vtag = rx_hdr->l2_fhdr_vlan_tag;
3158 #ifdef BCM_VLAN
3159 if (bp->vlgrp)
3160 hw_vlan = 1;
3161 else
3162 #endif
3163 {
3164 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3165 __skb_push(skb, 4);
3166
3167 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3168 ve->h_vlan_proto = htons(ETH_P_8021Q);
3169 ve->h_vlan_TCI = htons(vtag);
3170 len += 4;
3171 }
3172 }
3173
3174 skb->protocol = eth_type_trans(skb, bp->dev);
3175
3176 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3177 (ntohs(skb->protocol) != 0x8100)) {
3178
3179 dev_kfree_skb(skb);
3180 goto next_rx;
3181
3182 }
3183
3184 skb->ip_summed = CHECKSUM_NONE;
3185 if (bp->rx_csum &&
3186 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3187 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3188
3189 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3190 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3191 skb->ip_summed = CHECKSUM_UNNECESSARY;
3192 }
3193
3194 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3195
3196 #ifdef BCM_VLAN
3197 if (hw_vlan)
3198 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3199 else
3200 #endif
3201 netif_receive_skb(skb);
3202
3203 rx_pkt++;
3204
3205 next_rx:
3206 sw_cons = NEXT_RX_BD(sw_cons);
3207 sw_prod = NEXT_RX_BD(sw_prod);
3208
3209 if ((rx_pkt == budget))
3210 break;
3211
3212 /* Refresh hw_cons to see if there is new work */
3213 if (sw_cons == hw_cons) {
3214 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3215 rmb();
3216 }
3217 }
3218 rxr->rx_cons = sw_cons;
3219 rxr->rx_prod = sw_prod;
3220
3221 if (pg_ring_used)
3222 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3223
3224 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3225
3226 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3227
3228 mmiowb();
3229
3230 return rx_pkt;
3231
3232 }
3233
3234 /* MSI ISR - The only difference between this and the INTx ISR
3235 * is that the MSI interrupt is always serviced.
3236 */
3237 static irqreturn_t
3238 bnx2_msi(int irq, void *dev_instance)
3239 {
3240 struct bnx2_napi *bnapi = dev_instance;
3241 struct bnx2 *bp = bnapi->bp;
3242
3243 prefetch(bnapi->status_blk.msi);
3244 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3245 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3246 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3247
3248 /* Return here if interrupt is disabled. */
3249 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3250 return IRQ_HANDLED;
3251
3252 napi_schedule(&bnapi->napi);
3253
3254 return IRQ_HANDLED;
3255 }
3256
3257 static irqreturn_t
3258 bnx2_msi_1shot(int irq, void *dev_instance)
3259 {
3260 struct bnx2_napi *bnapi = dev_instance;
3261 struct bnx2 *bp = bnapi->bp;
3262
3263 prefetch(bnapi->status_blk.msi);
3264
3265 /* Return here if interrupt is disabled. */
3266 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3267 return IRQ_HANDLED;
3268
3269 napi_schedule(&bnapi->napi);
3270
3271 return IRQ_HANDLED;
3272 }
3273
3274 static irqreturn_t
3275 bnx2_interrupt(int irq, void *dev_instance)
3276 {
3277 struct bnx2_napi *bnapi = dev_instance;
3278 struct bnx2 *bp = bnapi->bp;
3279 struct status_block *sblk = bnapi->status_blk.msi;
3280
3281 /* When using INTx, it is possible for the interrupt to arrive
3282 * at the CPU before the status block posted prior to the
3283 * interrupt. Reading a register will flush the status block.
3284 * When using MSI, the MSI message will always complete after
3285 * the status block write.
3286 */
3287 if ((sblk->status_idx == bnapi->last_status_idx) &&
3288 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3289 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3290 return IRQ_NONE;
3291
3292 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3293 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3294 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3295
3296 /* Read back to deassert IRQ immediately to avoid too many
3297 * spurious interrupts.
3298 */
3299 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3300
3301 /* Return here if interrupt is shared and is disabled. */
3302 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3303 return IRQ_HANDLED;
3304
3305 if (napi_schedule_prep(&bnapi->napi)) {
3306 bnapi->last_status_idx = sblk->status_idx;
3307 __napi_schedule(&bnapi->napi);
3308 }
3309
3310 return IRQ_HANDLED;
3311 }
3312
3313 static inline int
3314 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3315 {
3316 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3317 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3318
3319 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3320 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3321 return 1;
3322 return 0;
3323 }
3324
3325 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3326 STATUS_ATTN_BITS_TIMER_ABORT)
3327
3328 static inline int
3329 bnx2_has_work(struct bnx2_napi *bnapi)
3330 {
3331 struct status_block *sblk = bnapi->status_blk.msi;
3332
3333 if (bnx2_has_fast_work(bnapi))
3334 return 1;
3335
3336 #ifdef BCM_CNIC
3337 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3338 return 1;
3339 #endif
3340
3341 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3342 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3343 return 1;
3344
3345 return 0;
3346 }
3347
3348 static void
3349 bnx2_chk_missed_msi(struct bnx2 *bp)
3350 {
3351 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3352 u32 msi_ctrl;
3353
3354 if (bnx2_has_work(bnapi)) {
3355 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3356 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3357 return;
3358
3359 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3360 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3361 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3362 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3363 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3364 }
3365 }
3366
3367 bp->idle_chk_status_idx = bnapi->last_status_idx;
3368 }
3369
3370 #ifdef BCM_CNIC
3371 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3372 {
3373 struct cnic_ops *c_ops;
3374
3375 if (!bnapi->cnic_present)
3376 return;
3377
3378 rcu_read_lock();
3379 c_ops = rcu_dereference(bp->cnic_ops);
3380 if (c_ops)
3381 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3382 bnapi->status_blk.msi);
3383 rcu_read_unlock();
3384 }
3385 #endif
3386
3387 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3388 {
3389 struct status_block *sblk = bnapi->status_blk.msi;
3390 u32 status_attn_bits = sblk->status_attn_bits;
3391 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3392
3393 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3394 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3395
3396 bnx2_phy_int(bp, bnapi);
3397
3398 /* This is needed to take care of transient status
3399 * during link changes.
3400 */
3401 REG_WR(bp, BNX2_HC_COMMAND,
3402 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3403 REG_RD(bp, BNX2_HC_COMMAND);
3404 }
3405 }
3406
3407 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3408 int work_done, int budget)
3409 {
3410 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3411 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3412
3413 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3414 bnx2_tx_int(bp, bnapi, 0);
3415
3416 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3417 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3418
3419 return work_done;
3420 }
3421
3422 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3423 {
3424 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3425 struct bnx2 *bp = bnapi->bp;
3426 int work_done = 0;
3427 struct status_block_msix *sblk = bnapi->status_blk.msix;
3428
3429 while (1) {
3430 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3431 if (unlikely(work_done >= budget))
3432 break;
3433
3434 bnapi->last_status_idx = sblk->status_idx;
3435 /* status idx must be read before checking for more work. */
3436 rmb();
3437 if (likely(!bnx2_has_fast_work(bnapi))) {
3438
3439 napi_complete(napi);
3440 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3441 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3442 bnapi->last_status_idx);
3443 break;
3444 }
3445 }
3446 return work_done;
3447 }
3448
3449 static int bnx2_poll(struct napi_struct *napi, int budget)
3450 {
3451 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3452 struct bnx2 *bp = bnapi->bp;
3453 int work_done = 0;
3454 struct status_block *sblk = bnapi->status_blk.msi;
3455
3456 while (1) {
3457 bnx2_poll_link(bp, bnapi);
3458
3459 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3460
3461 #ifdef BCM_CNIC
3462 bnx2_poll_cnic(bp, bnapi);
3463 #endif
3464
3465 /* bnapi->last_status_idx is used below to tell the hw how
3466 * much work has been processed, so we must read it before
3467 * checking for more work.
3468 */
3469 bnapi->last_status_idx = sblk->status_idx;
3470
3471 if (unlikely(work_done >= budget))
3472 break;
3473
3474 rmb();
3475 if (likely(!bnx2_has_work(bnapi))) {
3476 napi_complete(napi);
3477 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3478 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3479 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3480 bnapi->last_status_idx);
3481 break;
3482 }
3483 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3484 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3485 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3486 bnapi->last_status_idx);
3487
3488 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3489 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3490 bnapi->last_status_idx);
3491 break;
3492 }
3493 }
3494
3495 return work_done;
3496 }
3497
3498 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3499 * from set_multicast.
3500 */
3501 static void
3502 bnx2_set_rx_mode(struct net_device *dev)
3503 {
3504 struct bnx2 *bp = netdev_priv(dev);
3505 u32 rx_mode, sort_mode;
3506 struct netdev_hw_addr *ha;
3507 int i;
3508
3509 if (!netif_running(dev))
3510 return;
3511
3512 spin_lock_bh(&bp->phy_lock);
3513
3514 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3515 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3516 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3517 #ifdef BCM_VLAN
3518 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3519 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3520 #else
3521 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3522 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3523 #endif
3524 if (dev->flags & IFF_PROMISC) {
3525 /* Promiscuous mode. */
3526 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3527 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3528 BNX2_RPM_SORT_USER0_PROM_VLAN;
3529 }
3530 else if (dev->flags & IFF_ALLMULTI) {
3531 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3532 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3533 0xffffffff);
3534 }
3535 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3536 }
3537 else {
3538 /* Accept one or more multicast(s). */
3539 struct dev_mc_list *mclist;
3540 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3541 u32 regidx;
3542 u32 bit;
3543 u32 crc;
3544
3545 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3546
3547 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3548 i++, mclist = mclist->next) {
3549
3550 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3551 bit = crc & 0xff;
3552 regidx = (bit & 0xe0) >> 5;
3553 bit &= 0x1f;
3554 mc_filter[regidx] |= (1 << bit);
3555 }
3556
3557 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3558 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3559 mc_filter[i]);
3560 }
3561
3562 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3563 }
3564
3565 if (dev->uc.count > BNX2_MAX_UNICAST_ADDRESSES) {
3566 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3567 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3568 BNX2_RPM_SORT_USER0_PROM_VLAN;
3569 } else if (!(dev->flags & IFF_PROMISC)) {
3570 /* Add all entries into to the match filter list */
3571 i = 0;
3572 list_for_each_entry(ha, &dev->uc.list, list) {
3573 bnx2_set_mac_addr(bp, ha->addr,
3574 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3575 sort_mode |= (1 <<
3576 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3577 i++;
3578 }
3579
3580 }
3581
3582 if (rx_mode != bp->rx_mode) {
3583 bp->rx_mode = rx_mode;
3584 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3585 }
3586
3587 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3588 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3589 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3590
3591 spin_unlock_bh(&bp->phy_lock);
3592 }
3593
3594 static int __devinit
3595 check_fw_section(const struct firmware *fw,
3596 const struct bnx2_fw_file_section *section,
3597 u32 alignment, bool non_empty)
3598 {
3599 u32 offset = be32_to_cpu(section->offset);
3600 u32 len = be32_to_cpu(section->len);
3601
3602 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3603 return -EINVAL;
3604 if ((non_empty && len == 0) || len > fw->size - offset ||
3605 len & (alignment - 1))
3606 return -EINVAL;
3607 return 0;
3608 }
3609
3610 static int __devinit
3611 check_mips_fw_entry(const struct firmware *fw,
3612 const struct bnx2_mips_fw_file_entry *entry)
3613 {
3614 if (check_fw_section(fw, &entry->text, 4, true) ||
3615 check_fw_section(fw, &entry->data, 4, false) ||
3616 check_fw_section(fw, &entry->rodata, 4, false))
3617 return -EINVAL;
3618 return 0;
3619 }
3620
3621 static int __devinit
3622 bnx2_request_firmware(struct bnx2 *bp)
3623 {
3624 const char *mips_fw_file, *rv2p_fw_file;
3625 const struct bnx2_mips_fw_file *mips_fw;
3626 const struct bnx2_rv2p_fw_file *rv2p_fw;
3627 int rc;
3628
3629 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3630 mips_fw_file = FW_MIPS_FILE_09;
3631 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3632 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3633 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3634 else
3635 rv2p_fw_file = FW_RV2P_FILE_09;
3636 } else {
3637 mips_fw_file = FW_MIPS_FILE_06;
3638 rv2p_fw_file = FW_RV2P_FILE_06;
3639 }
3640
3641 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3642 if (rc) {
3643 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3644 mips_fw_file);
3645 return rc;
3646 }
3647
3648 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3649 if (rc) {
3650 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3651 rv2p_fw_file);
3652 return rc;
3653 }
3654 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3655 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3656 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3657 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3658 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3659 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3660 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3661 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3662 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3663 mips_fw_file);
3664 return -EINVAL;
3665 }
3666 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3667 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3668 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3669 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3670 rv2p_fw_file);
3671 return -EINVAL;
3672 }
3673
3674 return 0;
3675 }
3676
3677 static u32
3678 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3679 {
3680 switch (idx) {
3681 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3682 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3683 rv2p_code |= RV2P_BD_PAGE_SIZE;
3684 break;
3685 }
3686 return rv2p_code;
3687 }
3688
3689 static int
3690 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3691 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3692 {
3693 u32 rv2p_code_len, file_offset;
3694 __be32 *rv2p_code;
3695 int i;
3696 u32 val, cmd, addr;
3697
3698 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3699 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3700
3701 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3702
3703 if (rv2p_proc == RV2P_PROC1) {
3704 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3705 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3706 } else {
3707 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3708 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3709 }
3710
3711 for (i = 0; i < rv2p_code_len; i += 8) {
3712 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3713 rv2p_code++;
3714 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3715 rv2p_code++;
3716
3717 val = (i / 8) | cmd;
3718 REG_WR(bp, addr, val);
3719 }
3720
3721 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3722 for (i = 0; i < 8; i++) {
3723 u32 loc, code;
3724
3725 loc = be32_to_cpu(fw_entry->fixup[i]);
3726 if (loc && ((loc * 4) < rv2p_code_len)) {
3727 code = be32_to_cpu(*(rv2p_code + loc - 1));
3728 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3729 code = be32_to_cpu(*(rv2p_code + loc));
3730 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3731 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3732
3733 val = (loc / 2) | cmd;
3734 REG_WR(bp, addr, val);
3735 }
3736 }
3737
3738 /* Reset the processor, un-stall is done later. */
3739 if (rv2p_proc == RV2P_PROC1) {
3740 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3741 }
3742 else {
3743 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3744 }
3745
3746 return 0;
3747 }
3748
3749 static int
3750 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3751 const struct bnx2_mips_fw_file_entry *fw_entry)
3752 {
3753 u32 addr, len, file_offset;
3754 __be32 *data;
3755 u32 offset;
3756 u32 val;
3757
3758 /* Halt the CPU. */
3759 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3760 val |= cpu_reg->mode_value_halt;
3761 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3762 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3763
3764 /* Load the Text area. */
3765 addr = be32_to_cpu(fw_entry->text.addr);
3766 len = be32_to_cpu(fw_entry->text.len);
3767 file_offset = be32_to_cpu(fw_entry->text.offset);
3768 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3769
3770 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3771 if (len) {
3772 int j;
3773
3774 for (j = 0; j < (len / 4); j++, offset += 4)
3775 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3776 }
3777
3778 /* Load the Data area. */
3779 addr = be32_to_cpu(fw_entry->data.addr);
3780 len = be32_to_cpu(fw_entry->data.len);
3781 file_offset = be32_to_cpu(fw_entry->data.offset);
3782 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3783
3784 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3785 if (len) {
3786 int j;
3787
3788 for (j = 0; j < (len / 4); j++, offset += 4)
3789 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3790 }
3791
3792 /* Load the Read-Only area. */
3793 addr = be32_to_cpu(fw_entry->rodata.addr);
3794 len = be32_to_cpu(fw_entry->rodata.len);
3795 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3796 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3797
3798 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3799 if (len) {
3800 int j;
3801
3802 for (j = 0; j < (len / 4); j++, offset += 4)
3803 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3804 }
3805
3806 /* Clear the pre-fetch instruction. */
3807 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3808
3809 val = be32_to_cpu(fw_entry->start_addr);
3810 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3811
3812 /* Start the CPU. */
3813 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3814 val &= ~cpu_reg->mode_value_halt;
3815 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3816 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3817
3818 return 0;
3819 }
3820
3821 static int
3822 bnx2_init_cpus(struct bnx2 *bp)
3823 {
3824 const struct bnx2_mips_fw_file *mips_fw =
3825 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3826 const struct bnx2_rv2p_fw_file *rv2p_fw =
3827 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3828 int rc;
3829
3830 /* Initialize the RV2P processor. */
3831 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3832 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3833
3834 /* Initialize the RX Processor. */
3835 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3836 if (rc)
3837 goto init_cpu_err;
3838
3839 /* Initialize the TX Processor. */
3840 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3841 if (rc)
3842 goto init_cpu_err;
3843
3844 /* Initialize the TX Patch-up Processor. */
3845 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3846 if (rc)
3847 goto init_cpu_err;
3848
3849 /* Initialize the Completion Processor. */
3850 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3851 if (rc)
3852 goto init_cpu_err;
3853
3854 /* Initialize the Command Processor. */
3855 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3856
3857 init_cpu_err:
3858 return rc;
3859 }
3860
3861 static int
3862 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3863 {
3864 u16 pmcsr;
3865
3866 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3867
3868 switch (state) {
3869 case PCI_D0: {
3870 u32 val;
3871
3872 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3873 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3874 PCI_PM_CTRL_PME_STATUS);
3875
3876 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3877 /* delay required during transition out of D3hot */
3878 msleep(20);
3879
3880 val = REG_RD(bp, BNX2_EMAC_MODE);
3881 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3882 val &= ~BNX2_EMAC_MODE_MPKT;
3883 REG_WR(bp, BNX2_EMAC_MODE, val);
3884
3885 val = REG_RD(bp, BNX2_RPM_CONFIG);
3886 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3887 REG_WR(bp, BNX2_RPM_CONFIG, val);
3888 break;
3889 }
3890 case PCI_D3hot: {
3891 int i;
3892 u32 val, wol_msg;
3893
3894 if (bp->wol) {
3895 u32 advertising;
3896 u8 autoneg;
3897
3898 autoneg = bp->autoneg;
3899 advertising = bp->advertising;
3900
3901 if (bp->phy_port == PORT_TP) {
3902 bp->autoneg = AUTONEG_SPEED;
3903 bp->advertising = ADVERTISED_10baseT_Half |
3904 ADVERTISED_10baseT_Full |
3905 ADVERTISED_100baseT_Half |
3906 ADVERTISED_100baseT_Full |
3907 ADVERTISED_Autoneg;
3908 }
3909
3910 spin_lock_bh(&bp->phy_lock);
3911 bnx2_setup_phy(bp, bp->phy_port);
3912 spin_unlock_bh(&bp->phy_lock);
3913
3914 bp->autoneg = autoneg;
3915 bp->advertising = advertising;
3916
3917 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3918
3919 val = REG_RD(bp, BNX2_EMAC_MODE);
3920
3921 /* Enable port mode. */
3922 val &= ~BNX2_EMAC_MODE_PORT;
3923 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3924 BNX2_EMAC_MODE_ACPI_RCVD |
3925 BNX2_EMAC_MODE_MPKT;
3926 if (bp->phy_port == PORT_TP)
3927 val |= BNX2_EMAC_MODE_PORT_MII;
3928 else {
3929 val |= BNX2_EMAC_MODE_PORT_GMII;
3930 if (bp->line_speed == SPEED_2500)
3931 val |= BNX2_EMAC_MODE_25G_MODE;
3932 }
3933
3934 REG_WR(bp, BNX2_EMAC_MODE, val);
3935
3936 /* receive all multicast */
3937 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3938 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3939 0xffffffff);
3940 }
3941 REG_WR(bp, BNX2_EMAC_RX_MODE,
3942 BNX2_EMAC_RX_MODE_SORT_MODE);
3943
3944 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3945 BNX2_RPM_SORT_USER0_MC_EN;
3946 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3947 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3948 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3949 BNX2_RPM_SORT_USER0_ENA);
3950
3951 /* Need to enable EMAC and RPM for WOL. */
3952 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3953 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3954 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3955 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3956
3957 val = REG_RD(bp, BNX2_RPM_CONFIG);
3958 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3959 REG_WR(bp, BNX2_RPM_CONFIG, val);
3960
3961 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3962 }
3963 else {
3964 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3965 }
3966
3967 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3968 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3969 1, 0);
3970
3971 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3972 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3973 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3974
3975 if (bp->wol)
3976 pmcsr |= 3;
3977 }
3978 else {
3979 pmcsr |= 3;
3980 }
3981 if (bp->wol) {
3982 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3983 }
3984 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3985 pmcsr);
3986
3987 /* No more memory access after this point until
3988 * device is brought back to D0.
3989 */
3990 udelay(50);
3991 break;
3992 }
3993 default:
3994 return -EINVAL;
3995 }
3996 return 0;
3997 }
3998
3999 static int
4000 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4001 {
4002 u32 val;
4003 int j;
4004
4005 /* Request access to the flash interface. */
4006 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4007 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4008 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4009 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4010 break;
4011
4012 udelay(5);
4013 }
4014
4015 if (j >= NVRAM_TIMEOUT_COUNT)
4016 return -EBUSY;
4017
4018 return 0;
4019 }
4020
4021 static int
4022 bnx2_release_nvram_lock(struct bnx2 *bp)
4023 {
4024 int j;
4025 u32 val;
4026
4027 /* Relinquish nvram interface. */
4028 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4029
4030 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4031 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4032 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4033 break;
4034
4035 udelay(5);
4036 }
4037
4038 if (j >= NVRAM_TIMEOUT_COUNT)
4039 return -EBUSY;
4040
4041 return 0;
4042 }
4043
4044
4045 static int
4046 bnx2_enable_nvram_write(struct bnx2 *bp)
4047 {
4048 u32 val;
4049
4050 val = REG_RD(bp, BNX2_MISC_CFG);
4051 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4052
4053 if (bp->flash_info->flags & BNX2_NV_WREN) {
4054 int j;
4055
4056 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4057 REG_WR(bp, BNX2_NVM_COMMAND,
4058 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4059
4060 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4061 udelay(5);
4062
4063 val = REG_RD(bp, BNX2_NVM_COMMAND);
4064 if (val & BNX2_NVM_COMMAND_DONE)
4065 break;
4066 }
4067
4068 if (j >= NVRAM_TIMEOUT_COUNT)
4069 return -EBUSY;
4070 }
4071 return 0;
4072 }
4073
4074 static void
4075 bnx2_disable_nvram_write(struct bnx2 *bp)
4076 {
4077 u32 val;
4078
4079 val = REG_RD(bp, BNX2_MISC_CFG);
4080 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4081 }
4082
4083
4084 static void
4085 bnx2_enable_nvram_access(struct bnx2 *bp)
4086 {
4087 u32 val;
4088
4089 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4090 /* Enable both bits, even on read. */
4091 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4092 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4093 }
4094
4095 static void
4096 bnx2_disable_nvram_access(struct bnx2 *bp)
4097 {
4098 u32 val;
4099
4100 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4101 /* Disable both bits, even after read. */
4102 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4103 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4104 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4105 }
4106
4107 static int
4108 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4109 {
4110 u32 cmd;
4111 int j;
4112
4113 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4114 /* Buffered flash, no erase needed */
4115 return 0;
4116
4117 /* Build an erase command */
4118 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4119 BNX2_NVM_COMMAND_DOIT;
4120
4121 /* Need to clear DONE bit separately. */
4122 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4123
4124 /* Address of the NVRAM to read from. */
4125 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4126
4127 /* Issue an erase command. */
4128 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4129
4130 /* Wait for completion. */
4131 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4132 u32 val;
4133
4134 udelay(5);
4135
4136 val = REG_RD(bp, BNX2_NVM_COMMAND);
4137 if (val & BNX2_NVM_COMMAND_DONE)
4138 break;
4139 }
4140
4141 if (j >= NVRAM_TIMEOUT_COUNT)
4142 return -EBUSY;
4143
4144 return 0;
4145 }
4146
4147 static int
4148 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4149 {
4150 u32 cmd;
4151 int j;
4152
4153 /* Build the command word. */
4154 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4155
4156 /* Calculate an offset of a buffered flash, not needed for 5709. */
4157 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4158 offset = ((offset / bp->flash_info->page_size) <<
4159 bp->flash_info->page_bits) +
4160 (offset % bp->flash_info->page_size);
4161 }
4162
4163 /* Need to clear DONE bit separately. */
4164 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4165
4166 /* Address of the NVRAM to read from. */
4167 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4168
4169 /* Issue a read command. */
4170 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4171
4172 /* Wait for completion. */
4173 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4174 u32 val;
4175
4176 udelay(5);
4177
4178 val = REG_RD(bp, BNX2_NVM_COMMAND);
4179 if (val & BNX2_NVM_COMMAND_DONE) {
4180 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4181 memcpy(ret_val, &v, 4);
4182 break;
4183 }
4184 }
4185 if (j >= NVRAM_TIMEOUT_COUNT)
4186 return -EBUSY;
4187
4188 return 0;
4189 }
4190
4191
4192 static int
4193 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4194 {
4195 u32 cmd;
4196 __be32 val32;
4197 int j;
4198
4199 /* Build the command word. */
4200 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4201
4202 /* Calculate an offset of a buffered flash, not needed for 5709. */
4203 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4204 offset = ((offset / bp->flash_info->page_size) <<
4205 bp->flash_info->page_bits) +
4206 (offset % bp->flash_info->page_size);
4207 }
4208
4209 /* Need to clear DONE bit separately. */
4210 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4211
4212 memcpy(&val32, val, 4);
4213
4214 /* Write the data. */
4215 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4216
4217 /* Address of the NVRAM to write to. */
4218 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4219
4220 /* Issue the write command. */
4221 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4222
4223 /* Wait for completion. */
4224 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4225 udelay(5);
4226
4227 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4228 break;
4229 }
4230 if (j >= NVRAM_TIMEOUT_COUNT)
4231 return -EBUSY;
4232
4233 return 0;
4234 }
4235
4236 static int
4237 bnx2_init_nvram(struct bnx2 *bp)
4238 {
4239 u32 val;
4240 int j, entry_count, rc = 0;
4241 const struct flash_spec *flash;
4242
4243 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4244 bp->flash_info = &flash_5709;
4245 goto get_flash_size;
4246 }
4247
4248 /* Determine the selected interface. */
4249 val = REG_RD(bp, BNX2_NVM_CFG1);
4250
4251 entry_count = ARRAY_SIZE(flash_table);
4252
4253 if (val & 0x40000000) {
4254
4255 /* Flash interface has been reconfigured */
4256 for (j = 0, flash = &flash_table[0]; j < entry_count;
4257 j++, flash++) {
4258 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4259 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4260 bp->flash_info = flash;
4261 break;
4262 }
4263 }
4264 }
4265 else {
4266 u32 mask;
4267 /* Not yet been reconfigured */
4268
4269 if (val & (1 << 23))
4270 mask = FLASH_BACKUP_STRAP_MASK;
4271 else
4272 mask = FLASH_STRAP_MASK;
4273
4274 for (j = 0, flash = &flash_table[0]; j < entry_count;
4275 j++, flash++) {
4276
4277 if ((val & mask) == (flash->strapping & mask)) {
4278 bp->flash_info = flash;
4279
4280 /* Request access to the flash interface. */
4281 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4282 return rc;
4283
4284 /* Enable access to flash interface */
4285 bnx2_enable_nvram_access(bp);
4286
4287 /* Reconfigure the flash interface */
4288 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4289 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4290 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4291 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4292
4293 /* Disable access to flash interface */
4294 bnx2_disable_nvram_access(bp);
4295 bnx2_release_nvram_lock(bp);
4296
4297 break;
4298 }
4299 }
4300 } /* if (val & 0x40000000) */
4301
4302 if (j == entry_count) {
4303 bp->flash_info = NULL;
4304 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4305 return -ENODEV;
4306 }
4307
4308 get_flash_size:
4309 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4310 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4311 if (val)
4312 bp->flash_size = val;
4313 else
4314 bp->flash_size = bp->flash_info->total_size;
4315
4316 return rc;
4317 }
4318
4319 static int
4320 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4321 int buf_size)
4322 {
4323 int rc = 0;
4324 u32 cmd_flags, offset32, len32, extra;
4325
4326 if (buf_size == 0)
4327 return 0;
4328
4329 /* Request access to the flash interface. */
4330 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4331 return rc;
4332
4333 /* Enable access to flash interface */
4334 bnx2_enable_nvram_access(bp);
4335
4336 len32 = buf_size;
4337 offset32 = offset;
4338 extra = 0;
4339
4340 cmd_flags = 0;
4341
4342 if (offset32 & 3) {
4343 u8 buf[4];
4344 u32 pre_len;
4345
4346 offset32 &= ~3;
4347 pre_len = 4 - (offset & 3);
4348
4349 if (pre_len >= len32) {
4350 pre_len = len32;
4351 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4352 BNX2_NVM_COMMAND_LAST;
4353 }
4354 else {
4355 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4356 }
4357
4358 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4359
4360 if (rc)
4361 return rc;
4362
4363 memcpy(ret_buf, buf + (offset & 3), pre_len);
4364
4365 offset32 += 4;
4366 ret_buf += pre_len;
4367 len32 -= pre_len;
4368 }
4369 if (len32 & 3) {
4370 extra = 4 - (len32 & 3);
4371 len32 = (len32 + 4) & ~3;
4372 }
4373
4374 if (len32 == 4) {
4375 u8 buf[4];
4376
4377 if (cmd_flags)
4378 cmd_flags = BNX2_NVM_COMMAND_LAST;
4379 else
4380 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4381 BNX2_NVM_COMMAND_LAST;
4382
4383 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4384
4385 memcpy(ret_buf, buf, 4 - extra);
4386 }
4387 else if (len32 > 0) {
4388 u8 buf[4];
4389
4390 /* Read the first word. */
4391 if (cmd_flags)
4392 cmd_flags = 0;
4393 else
4394 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4395
4396 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4397
4398 /* Advance to the next dword. */
4399 offset32 += 4;
4400 ret_buf += 4;
4401 len32 -= 4;
4402
4403 while (len32 > 4 && rc == 0) {
4404 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4405
4406 /* Advance to the next dword. */
4407 offset32 += 4;
4408 ret_buf += 4;
4409 len32 -= 4;
4410 }
4411
4412 if (rc)
4413 return rc;
4414
4415 cmd_flags = BNX2_NVM_COMMAND_LAST;
4416 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4417
4418 memcpy(ret_buf, buf, 4 - extra);
4419 }
4420
4421 /* Disable access to flash interface */
4422 bnx2_disable_nvram_access(bp);
4423
4424 bnx2_release_nvram_lock(bp);
4425
4426 return rc;
4427 }
4428
4429 static int
4430 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4431 int buf_size)
4432 {
4433 u32 written, offset32, len32;
4434 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4435 int rc = 0;
4436 int align_start, align_end;
4437
4438 buf = data_buf;
4439 offset32 = offset;
4440 len32 = buf_size;
4441 align_start = align_end = 0;
4442
4443 if ((align_start = (offset32 & 3))) {
4444 offset32 &= ~3;
4445 len32 += align_start;
4446 if (len32 < 4)
4447 len32 = 4;
4448 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4449 return rc;
4450 }
4451
4452 if (len32 & 3) {
4453 align_end = 4 - (len32 & 3);
4454 len32 += align_end;
4455 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4456 return rc;
4457 }
4458
4459 if (align_start || align_end) {
4460 align_buf = kmalloc(len32, GFP_KERNEL);
4461 if (align_buf == NULL)
4462 return -ENOMEM;
4463 if (align_start) {
4464 memcpy(align_buf, start, 4);
4465 }
4466 if (align_end) {
4467 memcpy(align_buf + len32 - 4, end, 4);
4468 }
4469 memcpy(align_buf + align_start, data_buf, buf_size);
4470 buf = align_buf;
4471 }
4472
4473 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4474 flash_buffer = kmalloc(264, GFP_KERNEL);
4475 if (flash_buffer == NULL) {
4476 rc = -ENOMEM;
4477 goto nvram_write_end;
4478 }
4479 }
4480
4481 written = 0;
4482 while ((written < len32) && (rc == 0)) {
4483 u32 page_start, page_end, data_start, data_end;
4484 u32 addr, cmd_flags;
4485 int i;
4486
4487 /* Find the page_start addr */
4488 page_start = offset32 + written;
4489 page_start -= (page_start % bp->flash_info->page_size);
4490 /* Find the page_end addr */
4491 page_end = page_start + bp->flash_info->page_size;
4492 /* Find the data_start addr */
4493 data_start = (written == 0) ? offset32 : page_start;
4494 /* Find the data_end addr */
4495 data_end = (page_end > offset32 + len32) ?
4496 (offset32 + len32) : page_end;
4497
4498 /* Request access to the flash interface. */
4499 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4500 goto nvram_write_end;
4501
4502 /* Enable access to flash interface */
4503 bnx2_enable_nvram_access(bp);
4504
4505 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4506 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4507 int j;
4508
4509 /* Read the whole page into the buffer
4510 * (non-buffer flash only) */
4511 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4512 if (j == (bp->flash_info->page_size - 4)) {
4513 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4514 }
4515 rc = bnx2_nvram_read_dword(bp,
4516 page_start + j,
4517 &flash_buffer[j],
4518 cmd_flags);
4519
4520 if (rc)
4521 goto nvram_write_end;
4522
4523 cmd_flags = 0;
4524 }
4525 }
4526
4527 /* Enable writes to flash interface (unlock write-protect) */
4528 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4529 goto nvram_write_end;
4530
4531 /* Loop to write back the buffer data from page_start to
4532 * data_start */
4533 i = 0;
4534 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4535 /* Erase the page */
4536 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4537 goto nvram_write_end;
4538
4539 /* Re-enable the write again for the actual write */
4540 bnx2_enable_nvram_write(bp);
4541
4542 for (addr = page_start; addr < data_start;
4543 addr += 4, i += 4) {
4544
4545 rc = bnx2_nvram_write_dword(bp, addr,
4546 &flash_buffer[i], cmd_flags);
4547
4548 if (rc != 0)
4549 goto nvram_write_end;
4550
4551 cmd_flags = 0;
4552 }
4553 }
4554
4555 /* Loop to write the new data from data_start to data_end */
4556 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4557 if ((addr == page_end - 4) ||
4558 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4559 (addr == data_end - 4))) {
4560
4561 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4562 }
4563 rc = bnx2_nvram_write_dword(bp, addr, buf,
4564 cmd_flags);
4565
4566 if (rc != 0)
4567 goto nvram_write_end;
4568
4569 cmd_flags = 0;
4570 buf += 4;
4571 }
4572
4573 /* Loop to write back the buffer data from data_end
4574 * to page_end */
4575 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4576 for (addr = data_end; addr < page_end;
4577 addr += 4, i += 4) {
4578
4579 if (addr == page_end-4) {
4580 cmd_flags = BNX2_NVM_COMMAND_LAST;
4581 }
4582 rc = bnx2_nvram_write_dword(bp, addr,
4583 &flash_buffer[i], cmd_flags);
4584
4585 if (rc != 0)
4586 goto nvram_write_end;
4587
4588 cmd_flags = 0;
4589 }
4590 }
4591
4592 /* Disable writes to flash interface (lock write-protect) */
4593 bnx2_disable_nvram_write(bp);
4594
4595 /* Disable access to flash interface */
4596 bnx2_disable_nvram_access(bp);
4597 bnx2_release_nvram_lock(bp);
4598
4599 /* Increment written */
4600 written += data_end - data_start;
4601 }
4602
4603 nvram_write_end:
4604 kfree(flash_buffer);
4605 kfree(align_buf);
4606 return rc;
4607 }
4608
4609 static void
4610 bnx2_init_fw_cap(struct bnx2 *bp)
4611 {
4612 u32 val, sig = 0;
4613
4614 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4615 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4616
4617 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4618 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4619
4620 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4621 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4622 return;
4623
4624 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4625 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4626 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4627 }
4628
4629 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4630 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4631 u32 link;
4632
4633 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4634
4635 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4636 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4637 bp->phy_port = PORT_FIBRE;
4638 else
4639 bp->phy_port = PORT_TP;
4640
4641 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4642 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4643 }
4644
4645 if (netif_running(bp->dev) && sig)
4646 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4647 }
4648
4649 static void
4650 bnx2_setup_msix_tbl(struct bnx2 *bp)
4651 {
4652 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4653
4654 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4655 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4656 }
4657
4658 static int
4659 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4660 {
4661 u32 val;
4662 int i, rc = 0;
4663 u8 old_port;
4664
4665 /* Wait for the current PCI transaction to complete before
4666 * issuing a reset. */
4667 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4668 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4669 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4670 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4671 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4672 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4673 udelay(5);
4674
4675 /* Wait for the firmware to tell us it is ok to issue a reset. */
4676 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4677
4678 /* Deposit a driver reset signature so the firmware knows that
4679 * this is a soft reset. */
4680 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4681 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4682
4683 /* Do a dummy read to force the chip to complete all current transaction
4684 * before we issue a reset. */
4685 val = REG_RD(bp, BNX2_MISC_ID);
4686
4687 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4688 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4689 REG_RD(bp, BNX2_MISC_COMMAND);
4690 udelay(5);
4691
4692 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4693 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4694
4695 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4696
4697 } else {
4698 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4699 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4700 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4701
4702 /* Chip reset. */
4703 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4704
4705 /* Reading back any register after chip reset will hang the
4706 * bus on 5706 A0 and A1. The msleep below provides plenty
4707 * of margin for write posting.
4708 */
4709 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4710 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4711 msleep(20);
4712
4713 /* Reset takes approximate 30 usec */
4714 for (i = 0; i < 10; i++) {
4715 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4716 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4717 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4718 break;
4719 udelay(10);
4720 }
4721
4722 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4723 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4724 printk(KERN_ERR PFX "Chip reset did not complete\n");
4725 return -EBUSY;
4726 }
4727 }
4728
4729 /* Make sure byte swapping is properly configured. */
4730 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4731 if (val != 0x01020304) {
4732 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4733 return -ENODEV;
4734 }
4735
4736 /* Wait for the firmware to finish its initialization. */
4737 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4738 if (rc)
4739 return rc;
4740
4741 spin_lock_bh(&bp->phy_lock);
4742 old_port = bp->phy_port;
4743 bnx2_init_fw_cap(bp);
4744 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4745 old_port != bp->phy_port)
4746 bnx2_set_default_remote_link(bp);
4747 spin_unlock_bh(&bp->phy_lock);
4748
4749 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4750 /* Adjust the voltage regular to two steps lower. The default
4751 * of this register is 0x0000000e. */
4752 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4753
4754 /* Remove bad rbuf memory from the free pool. */
4755 rc = bnx2_alloc_bad_rbuf(bp);
4756 }
4757
4758 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4759 bnx2_setup_msix_tbl(bp);
4760 /* Prevent MSIX table reads and write from timing out */
4761 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4762 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4763 }
4764
4765 return rc;
4766 }
4767
4768 static int
4769 bnx2_init_chip(struct bnx2 *bp)
4770 {
4771 u32 val, mtu;
4772 int rc, i;
4773
4774 /* Make sure the interrupt is not active. */
4775 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4776
4777 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4778 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4779 #ifdef __BIG_ENDIAN
4780 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4781 #endif
4782 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4783 DMA_READ_CHANS << 12 |
4784 DMA_WRITE_CHANS << 16;
4785
4786 val |= (0x2 << 20) | (1 << 11);
4787
4788 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4789 val |= (1 << 23);
4790
4791 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4792 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4793 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4794
4795 REG_WR(bp, BNX2_DMA_CONFIG, val);
4796
4797 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4798 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4799 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4800 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4801 }
4802
4803 if (bp->flags & BNX2_FLAG_PCIX) {
4804 u16 val16;
4805
4806 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4807 &val16);
4808 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4809 val16 & ~PCI_X_CMD_ERO);
4810 }
4811
4812 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4813 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4814 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4815 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4816
4817 /* Initialize context mapping and zero out the quick contexts. The
4818 * context block must have already been enabled. */
4819 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4820 rc = bnx2_init_5709_context(bp);
4821 if (rc)
4822 return rc;
4823 } else
4824 bnx2_init_context(bp);
4825
4826 if ((rc = bnx2_init_cpus(bp)) != 0)
4827 return rc;
4828
4829 bnx2_init_nvram(bp);
4830
4831 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4832
4833 val = REG_RD(bp, BNX2_MQ_CONFIG);
4834 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4835 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4836 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4837 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4838 if (CHIP_REV(bp) == CHIP_REV_Ax)
4839 val |= BNX2_MQ_CONFIG_HALT_DIS;
4840 }
4841
4842 REG_WR(bp, BNX2_MQ_CONFIG, val);
4843
4844 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4845 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4846 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4847
4848 val = (BCM_PAGE_BITS - 8) << 24;
4849 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4850
4851 /* Configure page size. */
4852 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4853 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4854 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4855 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4856
4857 val = bp->mac_addr[0] +
4858 (bp->mac_addr[1] << 8) +
4859 (bp->mac_addr[2] << 16) +
4860 bp->mac_addr[3] +
4861 (bp->mac_addr[4] << 8) +
4862 (bp->mac_addr[5] << 16);
4863 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4864
4865 /* Program the MTU. Also include 4 bytes for CRC32. */
4866 mtu = bp->dev->mtu;
4867 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4868 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4869 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4870 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4871
4872 if (mtu < 1500)
4873 mtu = 1500;
4874
4875 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4876 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4877 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4878
4879 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4880 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4881 bp->bnx2_napi[i].last_status_idx = 0;
4882
4883 bp->idle_chk_status_idx = 0xffff;
4884
4885 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4886
4887 /* Set up how to generate a link change interrupt. */
4888 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4889
4890 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4891 (u64) bp->status_blk_mapping & 0xffffffff);
4892 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4893
4894 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4895 (u64) bp->stats_blk_mapping & 0xffffffff);
4896 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4897 (u64) bp->stats_blk_mapping >> 32);
4898
4899 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4900 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4901
4902 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4903 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4904
4905 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4906 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4907
4908 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4909
4910 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4911
4912 REG_WR(bp, BNX2_HC_COM_TICKS,
4913 (bp->com_ticks_int << 16) | bp->com_ticks);
4914
4915 REG_WR(bp, BNX2_HC_CMD_TICKS,
4916 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4917
4918 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4919 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4920 else
4921 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4922 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4923
4924 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4925 val = BNX2_HC_CONFIG_COLLECT_STATS;
4926 else {
4927 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4928 BNX2_HC_CONFIG_COLLECT_STATS;
4929 }
4930
4931 if (bp->irq_nvecs > 1) {
4932 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4933 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4934
4935 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4936 }
4937
4938 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4939 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4940
4941 REG_WR(bp, BNX2_HC_CONFIG, val);
4942
4943 for (i = 1; i < bp->irq_nvecs; i++) {
4944 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4945 BNX2_HC_SB_CONFIG_1;
4946
4947 REG_WR(bp, base,
4948 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4949 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4950 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4951
4952 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4953 (bp->tx_quick_cons_trip_int << 16) |
4954 bp->tx_quick_cons_trip);
4955
4956 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4957 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4958
4959 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4960 (bp->rx_quick_cons_trip_int << 16) |
4961 bp->rx_quick_cons_trip);
4962
4963 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4964 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4965 }
4966
4967 /* Clear internal stats counters. */
4968 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4969
4970 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4971
4972 /* Initialize the receive filter. */
4973 bnx2_set_rx_mode(bp->dev);
4974
4975 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4976 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4977 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4978 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4979 }
4980 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4981 1, 0);
4982
4983 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4984 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4985
4986 udelay(20);
4987
4988 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4989
4990 return rc;
4991 }
4992
4993 static void
4994 bnx2_clear_ring_states(struct bnx2 *bp)
4995 {
4996 struct bnx2_napi *bnapi;
4997 struct bnx2_tx_ring_info *txr;
4998 struct bnx2_rx_ring_info *rxr;
4999 int i;
5000
5001 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5002 bnapi = &bp->bnx2_napi[i];
5003 txr = &bnapi->tx_ring;
5004 rxr = &bnapi->rx_ring;
5005
5006 txr->tx_cons = 0;
5007 txr->hw_tx_cons = 0;
5008 rxr->rx_prod_bseq = 0;
5009 rxr->rx_prod = 0;
5010 rxr->rx_cons = 0;
5011 rxr->rx_pg_prod = 0;
5012 rxr->rx_pg_cons = 0;
5013 }
5014 }
5015
5016 static void
5017 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5018 {
5019 u32 val, offset0, offset1, offset2, offset3;
5020 u32 cid_addr = GET_CID_ADDR(cid);
5021
5022 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5023 offset0 = BNX2_L2CTX_TYPE_XI;
5024 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5025 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5026 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5027 } else {
5028 offset0 = BNX2_L2CTX_TYPE;
5029 offset1 = BNX2_L2CTX_CMD_TYPE;
5030 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5031 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5032 }
5033 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5034 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5035
5036 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5037 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5038
5039 val = (u64) txr->tx_desc_mapping >> 32;
5040 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5041
5042 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5043 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5044 }
5045
5046 static void
5047 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5048 {
5049 struct tx_bd *txbd;
5050 u32 cid = TX_CID;
5051 struct bnx2_napi *bnapi;
5052 struct bnx2_tx_ring_info *txr;
5053
5054 bnapi = &bp->bnx2_napi[ring_num];
5055 txr = &bnapi->tx_ring;
5056
5057 if (ring_num == 0)
5058 cid = TX_CID;
5059 else
5060 cid = TX_TSS_CID + ring_num - 1;
5061
5062 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5063
5064 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5065
5066 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5067 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5068
5069 txr->tx_prod = 0;
5070 txr->tx_prod_bseq = 0;
5071
5072 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5073 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5074
5075 bnx2_init_tx_context(bp, cid, txr);
5076 }
5077
5078 static void
5079 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5080 int num_rings)
5081 {
5082 int i;
5083 struct rx_bd *rxbd;
5084
5085 for (i = 0; i < num_rings; i++) {
5086 int j;
5087
5088 rxbd = &rx_ring[i][0];
5089 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5090 rxbd->rx_bd_len = buf_size;
5091 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5092 }
5093 if (i == (num_rings - 1))
5094 j = 0;
5095 else
5096 j = i + 1;
5097 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5098 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5099 }
5100 }
5101
5102 static void
5103 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5104 {
5105 int i;
5106 u16 prod, ring_prod;
5107 u32 cid, rx_cid_addr, val;
5108 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5109 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5110
5111 if (ring_num == 0)
5112 cid = RX_CID;
5113 else
5114 cid = RX_RSS_CID + ring_num - 1;
5115
5116 rx_cid_addr = GET_CID_ADDR(cid);
5117
5118 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5119 bp->rx_buf_use_size, bp->rx_max_ring);
5120
5121 bnx2_init_rx_context(bp, cid);
5122
5123 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5124 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5125 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5126 }
5127
5128 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5129 if (bp->rx_pg_ring_size) {
5130 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5131 rxr->rx_pg_desc_mapping,
5132 PAGE_SIZE, bp->rx_max_pg_ring);
5133 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5134 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5135 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5136 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5137
5138 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5139 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5140
5141 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5142 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5143
5144 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5145 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5146 }
5147
5148 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5149 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5150
5151 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5152 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5153
5154 ring_prod = prod = rxr->rx_pg_prod;
5155 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5156 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
5157 break;
5158 prod = NEXT_RX_BD(prod);
5159 ring_prod = RX_PG_RING_IDX(prod);
5160 }
5161 rxr->rx_pg_prod = prod;
5162
5163 ring_prod = prod = rxr->rx_prod;
5164 for (i = 0; i < bp->rx_ring_size; i++) {
5165 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
5166 break;
5167 prod = NEXT_RX_BD(prod);
5168 ring_prod = RX_RING_IDX(prod);
5169 }
5170 rxr->rx_prod = prod;
5171
5172 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5173 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5174 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5175
5176 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5177 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5178
5179 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5180 }
5181
5182 static void
5183 bnx2_init_all_rings(struct bnx2 *bp)
5184 {
5185 int i;
5186 u32 val;
5187
5188 bnx2_clear_ring_states(bp);
5189
5190 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5191 for (i = 0; i < bp->num_tx_rings; i++)
5192 bnx2_init_tx_ring(bp, i);
5193
5194 if (bp->num_tx_rings > 1)
5195 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5196 (TX_TSS_CID << 7));
5197
5198 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5199 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5200
5201 for (i = 0; i < bp->num_rx_rings; i++)
5202 bnx2_init_rx_ring(bp, i);
5203
5204 if (bp->num_rx_rings > 1) {
5205 u32 tbl_32;
5206 u8 *tbl = (u8 *) &tbl_32;
5207
5208 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5209 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5210
5211 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5212 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5213 if ((i % 4) == 3)
5214 bnx2_reg_wr_ind(bp,
5215 BNX2_RXP_SCRATCH_RSS_TBL + i,
5216 cpu_to_be32(tbl_32));
5217 }
5218
5219 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5220 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5221
5222 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5223
5224 }
5225 }
5226
5227 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5228 {
5229 u32 max, num_rings = 1;
5230
5231 while (ring_size > MAX_RX_DESC_CNT) {
5232 ring_size -= MAX_RX_DESC_CNT;
5233 num_rings++;
5234 }
5235 /* round to next power of 2 */
5236 max = max_size;
5237 while ((max & num_rings) == 0)
5238 max >>= 1;
5239
5240 if (num_rings != max)
5241 max <<= 1;
5242
5243 return max;
5244 }
5245
5246 static void
5247 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5248 {
5249 u32 rx_size, rx_space, jumbo_size;
5250
5251 /* 8 for CRC and VLAN */
5252 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5253
5254 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5255 sizeof(struct skb_shared_info);
5256
5257 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5258 bp->rx_pg_ring_size = 0;
5259 bp->rx_max_pg_ring = 0;
5260 bp->rx_max_pg_ring_idx = 0;
5261 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5262 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5263
5264 jumbo_size = size * pages;
5265 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5266 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5267
5268 bp->rx_pg_ring_size = jumbo_size;
5269 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5270 MAX_RX_PG_RINGS);
5271 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5272 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5273 bp->rx_copy_thresh = 0;
5274 }
5275
5276 bp->rx_buf_use_size = rx_size;
5277 /* hw alignment */
5278 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5279 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5280 bp->rx_ring_size = size;
5281 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5282 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5283 }
5284
5285 static void
5286 bnx2_free_tx_skbs(struct bnx2 *bp)
5287 {
5288 int i;
5289
5290 for (i = 0; i < bp->num_tx_rings; i++) {
5291 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5292 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5293 int j;
5294
5295 if (txr->tx_buf_ring == NULL)
5296 continue;
5297
5298 for (j = 0; j < TX_DESC_CNT; ) {
5299 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5300 struct sk_buff *skb = tx_buf->skb;
5301
5302 if (skb == NULL) {
5303 j++;
5304 continue;
5305 }
5306
5307 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5308
5309 tx_buf->skb = NULL;
5310
5311 j += skb_shinfo(skb)->nr_frags + 1;
5312 dev_kfree_skb(skb);
5313 }
5314 }
5315 }
5316
5317 static void
5318 bnx2_free_rx_skbs(struct bnx2 *bp)
5319 {
5320 int i;
5321
5322 for (i = 0; i < bp->num_rx_rings; i++) {
5323 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5324 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5325 int j;
5326
5327 if (rxr->rx_buf_ring == NULL)
5328 return;
5329
5330 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5331 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5332 struct sk_buff *skb = rx_buf->skb;
5333
5334 if (skb == NULL)
5335 continue;
5336
5337 pci_unmap_single(bp->pdev,
5338 pci_unmap_addr(rx_buf, mapping),
5339 bp->rx_buf_use_size,
5340 PCI_DMA_FROMDEVICE);
5341
5342 rx_buf->skb = NULL;
5343
5344 dev_kfree_skb(skb);
5345 }
5346 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5347 bnx2_free_rx_page(bp, rxr, j);
5348 }
5349 }
5350
5351 static void
5352 bnx2_free_skbs(struct bnx2 *bp)
5353 {
5354 bnx2_free_tx_skbs(bp);
5355 bnx2_free_rx_skbs(bp);
5356 }
5357
5358 static int
5359 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5360 {
5361 int rc;
5362
5363 rc = bnx2_reset_chip(bp, reset_code);
5364 bnx2_free_skbs(bp);
5365 if (rc)
5366 return rc;
5367
5368 if ((rc = bnx2_init_chip(bp)) != 0)
5369 return rc;
5370
5371 bnx2_init_all_rings(bp);
5372 return 0;
5373 }
5374
5375 static int
5376 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5377 {
5378 int rc;
5379
5380 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5381 return rc;
5382
5383 spin_lock_bh(&bp->phy_lock);
5384 bnx2_init_phy(bp, reset_phy);
5385 bnx2_set_link(bp);
5386 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5387 bnx2_remote_phy_event(bp);
5388 spin_unlock_bh(&bp->phy_lock);
5389 return 0;
5390 }
5391
5392 static int
5393 bnx2_shutdown_chip(struct bnx2 *bp)
5394 {
5395 u32 reset_code;
5396
5397 if (bp->flags & BNX2_FLAG_NO_WOL)
5398 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5399 else if (bp->wol)
5400 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5401 else
5402 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5403
5404 return bnx2_reset_chip(bp, reset_code);
5405 }
5406
5407 static int
5408 bnx2_test_registers(struct bnx2 *bp)
5409 {
5410 int ret;
5411 int i, is_5709;
5412 static const struct {
5413 u16 offset;
5414 u16 flags;
5415 #define BNX2_FL_NOT_5709 1
5416 u32 rw_mask;
5417 u32 ro_mask;
5418 } reg_tbl[] = {
5419 { 0x006c, 0, 0x00000000, 0x0000003f },
5420 { 0x0090, 0, 0xffffffff, 0x00000000 },
5421 { 0x0094, 0, 0x00000000, 0x00000000 },
5422
5423 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5424 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5425 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5426 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5427 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5428 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5429 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5430 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5431 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5432
5433 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5434 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5435 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5436 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5437 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5438 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5439
5440 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5441 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5442 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5443
5444 { 0x1000, 0, 0x00000000, 0x00000001 },
5445 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5446
5447 { 0x1408, 0, 0x01c00800, 0x00000000 },
5448 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5449 { 0x14a8, 0, 0x00000000, 0x000001ff },
5450 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5451 { 0x14b0, 0, 0x00000002, 0x00000001 },
5452 { 0x14b8, 0, 0x00000000, 0x00000000 },
5453 { 0x14c0, 0, 0x00000000, 0x00000009 },
5454 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5455 { 0x14cc, 0, 0x00000000, 0x00000001 },
5456 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5457
5458 { 0x1800, 0, 0x00000000, 0x00000001 },
5459 { 0x1804, 0, 0x00000000, 0x00000003 },
5460
5461 { 0x2800, 0, 0x00000000, 0x00000001 },
5462 { 0x2804, 0, 0x00000000, 0x00003f01 },
5463 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5464 { 0x2810, 0, 0xffff0000, 0x00000000 },
5465 { 0x2814, 0, 0xffff0000, 0x00000000 },
5466 { 0x2818, 0, 0xffff0000, 0x00000000 },
5467 { 0x281c, 0, 0xffff0000, 0x00000000 },
5468 { 0x2834, 0, 0xffffffff, 0x00000000 },
5469 { 0x2840, 0, 0x00000000, 0xffffffff },
5470 { 0x2844, 0, 0x00000000, 0xffffffff },
5471 { 0x2848, 0, 0xffffffff, 0x00000000 },
5472 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5473
5474 { 0x2c00, 0, 0x00000000, 0x00000011 },
5475 { 0x2c04, 0, 0x00000000, 0x00030007 },
5476
5477 { 0x3c00, 0, 0x00000000, 0x00000001 },
5478 { 0x3c04, 0, 0x00000000, 0x00070000 },
5479 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5480 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5481 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5482 { 0x3c14, 0, 0x00000000, 0xffffffff },
5483 { 0x3c18, 0, 0x00000000, 0xffffffff },
5484 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5485 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5486
5487 { 0x5004, 0, 0x00000000, 0x0000007f },
5488 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5489
5490 { 0x5c00, 0, 0x00000000, 0x00000001 },
5491 { 0x5c04, 0, 0x00000000, 0x0003000f },
5492 { 0x5c08, 0, 0x00000003, 0x00000000 },
5493 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5494 { 0x5c10, 0, 0x00000000, 0xffffffff },
5495 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5496 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5497 { 0x5c88, 0, 0x00000000, 0x00077373 },
5498 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5499
5500 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5501 { 0x680c, 0, 0xffffffff, 0x00000000 },
5502 { 0x6810, 0, 0xffffffff, 0x00000000 },
5503 { 0x6814, 0, 0xffffffff, 0x00000000 },
5504 { 0x6818, 0, 0xffffffff, 0x00000000 },
5505 { 0x681c, 0, 0xffffffff, 0x00000000 },
5506 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5507 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5508 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5509 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5510 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5511 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5512 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5513 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5514 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5515 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5516 { 0x684c, 0, 0xffffffff, 0x00000000 },
5517 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5518 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5519 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5520 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5521 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5522 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5523
5524 { 0xffff, 0, 0x00000000, 0x00000000 },
5525 };
5526
5527 ret = 0;
5528 is_5709 = 0;
5529 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5530 is_5709 = 1;
5531
5532 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5533 u32 offset, rw_mask, ro_mask, save_val, val;
5534 u16 flags = reg_tbl[i].flags;
5535
5536 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5537 continue;
5538
5539 offset = (u32) reg_tbl[i].offset;
5540 rw_mask = reg_tbl[i].rw_mask;
5541 ro_mask = reg_tbl[i].ro_mask;
5542
5543 save_val = readl(bp->regview + offset);
5544
5545 writel(0, bp->regview + offset);
5546
5547 val = readl(bp->regview + offset);
5548 if ((val & rw_mask) != 0) {
5549 goto reg_test_err;
5550 }
5551
5552 if ((val & ro_mask) != (save_val & ro_mask)) {
5553 goto reg_test_err;
5554 }
5555
5556 writel(0xffffffff, bp->regview + offset);
5557
5558 val = readl(bp->regview + offset);
5559 if ((val & rw_mask) != rw_mask) {
5560 goto reg_test_err;
5561 }
5562
5563 if ((val & ro_mask) != (save_val & ro_mask)) {
5564 goto reg_test_err;
5565 }
5566
5567 writel(save_val, bp->regview + offset);
5568 continue;
5569
5570 reg_test_err:
5571 writel(save_val, bp->regview + offset);
5572 ret = -ENODEV;
5573 break;
5574 }
5575 return ret;
5576 }
5577
5578 static int
5579 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5580 {
5581 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5582 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5583 int i;
5584
5585 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5586 u32 offset;
5587
5588 for (offset = 0; offset < size; offset += 4) {
5589
5590 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5591
5592 if (bnx2_reg_rd_ind(bp, start + offset) !=
5593 test_pattern[i]) {
5594 return -ENODEV;
5595 }
5596 }
5597 }
5598 return 0;
5599 }
5600
5601 static int
5602 bnx2_test_memory(struct bnx2 *bp)
5603 {
5604 int ret = 0;
5605 int i;
5606 static struct mem_entry {
5607 u32 offset;
5608 u32 len;
5609 } mem_tbl_5706[] = {
5610 { 0x60000, 0x4000 },
5611 { 0xa0000, 0x3000 },
5612 { 0xe0000, 0x4000 },
5613 { 0x120000, 0x4000 },
5614 { 0x1a0000, 0x4000 },
5615 { 0x160000, 0x4000 },
5616 { 0xffffffff, 0 },
5617 },
5618 mem_tbl_5709[] = {
5619 { 0x60000, 0x4000 },
5620 { 0xa0000, 0x3000 },
5621 { 0xe0000, 0x4000 },
5622 { 0x120000, 0x4000 },
5623 { 0x1a0000, 0x4000 },
5624 { 0xffffffff, 0 },
5625 };
5626 struct mem_entry *mem_tbl;
5627
5628 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5629 mem_tbl = mem_tbl_5709;
5630 else
5631 mem_tbl = mem_tbl_5706;
5632
5633 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5634 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5635 mem_tbl[i].len)) != 0) {
5636 return ret;
5637 }
5638 }
5639
5640 return ret;
5641 }
5642
5643 #define BNX2_MAC_LOOPBACK 0
5644 #define BNX2_PHY_LOOPBACK 1
5645
5646 static int
5647 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5648 {
5649 unsigned int pkt_size, num_pkts, i;
5650 struct sk_buff *skb, *rx_skb;
5651 unsigned char *packet;
5652 u16 rx_start_idx, rx_idx;
5653 dma_addr_t map;
5654 struct tx_bd *txbd;
5655 struct sw_bd *rx_buf;
5656 struct l2_fhdr *rx_hdr;
5657 int ret = -ENODEV;
5658 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5659 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5660 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5661
5662 tx_napi = bnapi;
5663
5664 txr = &tx_napi->tx_ring;
5665 rxr = &bnapi->rx_ring;
5666 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5667 bp->loopback = MAC_LOOPBACK;
5668 bnx2_set_mac_loopback(bp);
5669 }
5670 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5671 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5672 return 0;
5673
5674 bp->loopback = PHY_LOOPBACK;
5675 bnx2_set_phy_loopback(bp);
5676 }
5677 else
5678 return -EINVAL;
5679
5680 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5681 skb = netdev_alloc_skb(bp->dev, pkt_size);
5682 if (!skb)
5683 return -ENOMEM;
5684 packet = skb_put(skb, pkt_size);
5685 memcpy(packet, bp->dev->dev_addr, 6);
5686 memset(packet + 6, 0x0, 8);
5687 for (i = 14; i < pkt_size; i++)
5688 packet[i] = (unsigned char) (i & 0xff);
5689
5690 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5691 dev_kfree_skb(skb);
5692 return -EIO;
5693 }
5694 map = skb_shinfo(skb)->dma_head;
5695
5696 REG_WR(bp, BNX2_HC_COMMAND,
5697 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5698
5699 REG_RD(bp, BNX2_HC_COMMAND);
5700
5701 udelay(5);
5702 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5703
5704 num_pkts = 0;
5705
5706 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5707
5708 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5709 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5710 txbd->tx_bd_mss_nbytes = pkt_size;
5711 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5712
5713 num_pkts++;
5714 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5715 txr->tx_prod_bseq += pkt_size;
5716
5717 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5718 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5719
5720 udelay(100);
5721
5722 REG_WR(bp, BNX2_HC_COMMAND,
5723 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5724
5725 REG_RD(bp, BNX2_HC_COMMAND);
5726
5727 udelay(5);
5728
5729 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5730 dev_kfree_skb(skb);
5731
5732 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5733 goto loopback_test_done;
5734
5735 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5736 if (rx_idx != rx_start_idx + num_pkts) {
5737 goto loopback_test_done;
5738 }
5739
5740 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5741 rx_skb = rx_buf->skb;
5742
5743 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5744 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5745
5746 pci_dma_sync_single_for_cpu(bp->pdev,
5747 pci_unmap_addr(rx_buf, mapping),
5748 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5749
5750 if (rx_hdr->l2_fhdr_status &
5751 (L2_FHDR_ERRORS_BAD_CRC |
5752 L2_FHDR_ERRORS_PHY_DECODE |
5753 L2_FHDR_ERRORS_ALIGNMENT |
5754 L2_FHDR_ERRORS_TOO_SHORT |
5755 L2_FHDR_ERRORS_GIANT_FRAME)) {
5756
5757 goto loopback_test_done;
5758 }
5759
5760 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5761 goto loopback_test_done;
5762 }
5763
5764 for (i = 14; i < pkt_size; i++) {
5765 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5766 goto loopback_test_done;
5767 }
5768 }
5769
5770 ret = 0;
5771
5772 loopback_test_done:
5773 bp->loopback = 0;
5774 return ret;
5775 }
5776
5777 #define BNX2_MAC_LOOPBACK_FAILED 1
5778 #define BNX2_PHY_LOOPBACK_FAILED 2
5779 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5780 BNX2_PHY_LOOPBACK_FAILED)
5781
5782 static int
5783 bnx2_test_loopback(struct bnx2 *bp)
5784 {
5785 int rc = 0;
5786
5787 if (!netif_running(bp->dev))
5788 return BNX2_LOOPBACK_FAILED;
5789
5790 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5791 spin_lock_bh(&bp->phy_lock);
5792 bnx2_init_phy(bp, 1);
5793 spin_unlock_bh(&bp->phy_lock);
5794 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5795 rc |= BNX2_MAC_LOOPBACK_FAILED;
5796 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5797 rc |= BNX2_PHY_LOOPBACK_FAILED;
5798 return rc;
5799 }
5800
5801 #define NVRAM_SIZE 0x200
5802 #define CRC32_RESIDUAL 0xdebb20e3
5803
5804 static int
5805 bnx2_test_nvram(struct bnx2 *bp)
5806 {
5807 __be32 buf[NVRAM_SIZE / 4];
5808 u8 *data = (u8 *) buf;
5809 int rc = 0;
5810 u32 magic, csum;
5811
5812 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5813 goto test_nvram_done;
5814
5815 magic = be32_to_cpu(buf[0]);
5816 if (magic != 0x669955aa) {
5817 rc = -ENODEV;
5818 goto test_nvram_done;
5819 }
5820
5821 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5822 goto test_nvram_done;
5823
5824 csum = ether_crc_le(0x100, data);
5825 if (csum != CRC32_RESIDUAL) {
5826 rc = -ENODEV;
5827 goto test_nvram_done;
5828 }
5829
5830 csum = ether_crc_le(0x100, data + 0x100);
5831 if (csum != CRC32_RESIDUAL) {
5832 rc = -ENODEV;
5833 }
5834
5835 test_nvram_done:
5836 return rc;
5837 }
5838
5839 static int
5840 bnx2_test_link(struct bnx2 *bp)
5841 {
5842 u32 bmsr;
5843
5844 if (!netif_running(bp->dev))
5845 return -ENODEV;
5846
5847 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5848 if (bp->link_up)
5849 return 0;
5850 return -ENODEV;
5851 }
5852 spin_lock_bh(&bp->phy_lock);
5853 bnx2_enable_bmsr1(bp);
5854 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5855 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5856 bnx2_disable_bmsr1(bp);
5857 spin_unlock_bh(&bp->phy_lock);
5858
5859 if (bmsr & BMSR_LSTATUS) {
5860 return 0;
5861 }
5862 return -ENODEV;
5863 }
5864
5865 static int
5866 bnx2_test_intr(struct bnx2 *bp)
5867 {
5868 int i;
5869 u16 status_idx;
5870
5871 if (!netif_running(bp->dev))
5872 return -ENODEV;
5873
5874 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5875
5876 /* This register is not touched during run-time. */
5877 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5878 REG_RD(bp, BNX2_HC_COMMAND);
5879
5880 for (i = 0; i < 10; i++) {
5881 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5882 status_idx) {
5883
5884 break;
5885 }
5886
5887 msleep_interruptible(10);
5888 }
5889 if (i < 10)
5890 return 0;
5891
5892 return -ENODEV;
5893 }
5894
5895 /* Determining link for parallel detection. */
5896 static int
5897 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5898 {
5899 u32 mode_ctl, an_dbg, exp;
5900
5901 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5902 return 0;
5903
5904 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5905 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5906
5907 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5908 return 0;
5909
5910 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5911 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5912 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5913
5914 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5915 return 0;
5916
5917 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5918 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5919 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5920
5921 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5922 return 0;
5923
5924 return 1;
5925 }
5926
5927 static void
5928 bnx2_5706_serdes_timer(struct bnx2 *bp)
5929 {
5930 int check_link = 1;
5931
5932 spin_lock(&bp->phy_lock);
5933 if (bp->serdes_an_pending) {
5934 bp->serdes_an_pending--;
5935 check_link = 0;
5936 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5937 u32 bmcr;
5938
5939 bp->current_interval = BNX2_TIMER_INTERVAL;
5940
5941 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5942
5943 if (bmcr & BMCR_ANENABLE) {
5944 if (bnx2_5706_serdes_has_link(bp)) {
5945 bmcr &= ~BMCR_ANENABLE;
5946 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5947 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5948 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5949 }
5950 }
5951 }
5952 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5953 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5954 u32 phy2;
5955
5956 bnx2_write_phy(bp, 0x17, 0x0f01);
5957 bnx2_read_phy(bp, 0x15, &phy2);
5958 if (phy2 & 0x20) {
5959 u32 bmcr;
5960
5961 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5962 bmcr |= BMCR_ANENABLE;
5963 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5964
5965 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5966 }
5967 } else
5968 bp->current_interval = BNX2_TIMER_INTERVAL;
5969
5970 if (check_link) {
5971 u32 val;
5972
5973 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5974 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5975 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5976
5977 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5978 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5979 bnx2_5706s_force_link_dn(bp, 1);
5980 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5981 } else
5982 bnx2_set_link(bp);
5983 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5984 bnx2_set_link(bp);
5985 }
5986 spin_unlock(&bp->phy_lock);
5987 }
5988
5989 static void
5990 bnx2_5708_serdes_timer(struct bnx2 *bp)
5991 {
5992 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5993 return;
5994
5995 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5996 bp->serdes_an_pending = 0;
5997 return;
5998 }
5999
6000 spin_lock(&bp->phy_lock);
6001 if (bp->serdes_an_pending)
6002 bp->serdes_an_pending--;
6003 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6004 u32 bmcr;
6005
6006 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6007 if (bmcr & BMCR_ANENABLE) {
6008 bnx2_enable_forced_2g5(bp);
6009 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6010 } else {
6011 bnx2_disable_forced_2g5(bp);
6012 bp->serdes_an_pending = 2;
6013 bp->current_interval = BNX2_TIMER_INTERVAL;
6014 }
6015
6016 } else
6017 bp->current_interval = BNX2_TIMER_INTERVAL;
6018
6019 spin_unlock(&bp->phy_lock);
6020 }
6021
6022 static void
6023 bnx2_timer(unsigned long data)
6024 {
6025 struct bnx2 *bp = (struct bnx2 *) data;
6026
6027 if (!netif_running(bp->dev))
6028 return;
6029
6030 if (atomic_read(&bp->intr_sem) != 0)
6031 goto bnx2_restart_timer;
6032
6033 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6034 BNX2_FLAG_USING_MSI)
6035 bnx2_chk_missed_msi(bp);
6036
6037 bnx2_send_heart_beat(bp);
6038
6039 bp->stats_blk->stat_FwRxDrop =
6040 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6041
6042 /* workaround occasional corrupted counters */
6043 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6044 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6045 BNX2_HC_COMMAND_STATS_NOW);
6046
6047 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6048 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6049 bnx2_5706_serdes_timer(bp);
6050 else
6051 bnx2_5708_serdes_timer(bp);
6052 }
6053
6054 bnx2_restart_timer:
6055 mod_timer(&bp->timer, jiffies + bp->current_interval);
6056 }
6057
6058 static int
6059 bnx2_request_irq(struct bnx2 *bp)
6060 {
6061 unsigned long flags;
6062 struct bnx2_irq *irq;
6063 int rc = 0, i;
6064
6065 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6066 flags = 0;
6067 else
6068 flags = IRQF_SHARED;
6069
6070 for (i = 0; i < bp->irq_nvecs; i++) {
6071 irq = &bp->irq_tbl[i];
6072 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6073 &bp->bnx2_napi[i]);
6074 if (rc)
6075 break;
6076 irq->requested = 1;
6077 }
6078 return rc;
6079 }
6080
6081 static void
6082 bnx2_free_irq(struct bnx2 *bp)
6083 {
6084 struct bnx2_irq *irq;
6085 int i;
6086
6087 for (i = 0; i < bp->irq_nvecs; i++) {
6088 irq = &bp->irq_tbl[i];
6089 if (irq->requested)
6090 free_irq(irq->vector, &bp->bnx2_napi[i]);
6091 irq->requested = 0;
6092 }
6093 if (bp->flags & BNX2_FLAG_USING_MSI)
6094 pci_disable_msi(bp->pdev);
6095 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6096 pci_disable_msix(bp->pdev);
6097
6098 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6099 }
6100
6101 static void
6102 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6103 {
6104 int i, rc;
6105 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6106 struct net_device *dev = bp->dev;
6107 const int len = sizeof(bp->irq_tbl[0].name);
6108
6109 bnx2_setup_msix_tbl(bp);
6110 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6111 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6112 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6113
6114 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6115 msix_ent[i].entry = i;
6116 msix_ent[i].vector = 0;
6117 }
6118
6119 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6120 if (rc != 0)
6121 return;
6122
6123 bp->irq_nvecs = msix_vecs;
6124 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6125 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6126 bp->irq_tbl[i].vector = msix_ent[i].vector;
6127 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6128 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6129 }
6130 }
6131
6132 static void
6133 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6134 {
6135 int cpus = num_online_cpus();
6136 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6137
6138 bp->irq_tbl[0].handler = bnx2_interrupt;
6139 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6140 bp->irq_nvecs = 1;
6141 bp->irq_tbl[0].vector = bp->pdev->irq;
6142
6143 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
6144 bnx2_enable_msix(bp, msix_vecs);
6145
6146 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6147 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6148 if (pci_enable_msi(bp->pdev) == 0) {
6149 bp->flags |= BNX2_FLAG_USING_MSI;
6150 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6151 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6152 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6153 } else
6154 bp->irq_tbl[0].handler = bnx2_msi;
6155
6156 bp->irq_tbl[0].vector = bp->pdev->irq;
6157 }
6158 }
6159
6160 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6161 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6162
6163 bp->num_rx_rings = bp->irq_nvecs;
6164 }
6165
6166 /* Called with rtnl_lock */
6167 static int
6168 bnx2_open(struct net_device *dev)
6169 {
6170 struct bnx2 *bp = netdev_priv(dev);
6171 int rc;
6172
6173 netif_carrier_off(dev);
6174
6175 bnx2_set_power_state(bp, PCI_D0);
6176 bnx2_disable_int(bp);
6177
6178 bnx2_setup_int_mode(bp, disable_msi);
6179 bnx2_init_napi(bp);
6180 bnx2_napi_enable(bp);
6181 rc = bnx2_alloc_mem(bp);
6182 if (rc)
6183 goto open_err;
6184
6185 rc = bnx2_request_irq(bp);
6186 if (rc)
6187 goto open_err;
6188
6189 rc = bnx2_init_nic(bp, 1);
6190 if (rc)
6191 goto open_err;
6192
6193 mod_timer(&bp->timer, jiffies + bp->current_interval);
6194
6195 atomic_set(&bp->intr_sem, 0);
6196
6197 bnx2_enable_int(bp);
6198
6199 if (bp->flags & BNX2_FLAG_USING_MSI) {
6200 /* Test MSI to make sure it is working
6201 * If MSI test fails, go back to INTx mode
6202 */
6203 if (bnx2_test_intr(bp) != 0) {
6204 printk(KERN_WARNING PFX "%s: No interrupt was generated"
6205 " using MSI, switching to INTx mode. Please"
6206 " report this failure to the PCI maintainer"
6207 " and include system chipset information.\n",
6208 bp->dev->name);
6209
6210 bnx2_disable_int(bp);
6211 bnx2_free_irq(bp);
6212
6213 bnx2_setup_int_mode(bp, 1);
6214
6215 rc = bnx2_init_nic(bp, 0);
6216
6217 if (!rc)
6218 rc = bnx2_request_irq(bp);
6219
6220 if (rc) {
6221 del_timer_sync(&bp->timer);
6222 goto open_err;
6223 }
6224 bnx2_enable_int(bp);
6225 }
6226 }
6227 if (bp->flags & BNX2_FLAG_USING_MSI)
6228 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
6229 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6230 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
6231
6232 netif_tx_start_all_queues(dev);
6233
6234 return 0;
6235
6236 open_err:
6237 bnx2_napi_disable(bp);
6238 bnx2_free_skbs(bp);
6239 bnx2_free_irq(bp);
6240 bnx2_free_mem(bp);
6241 bnx2_del_napi(bp);
6242 return rc;
6243 }
6244
6245 static void
6246 bnx2_reset_task(struct work_struct *work)
6247 {
6248 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6249
6250 if (!netif_running(bp->dev))
6251 return;
6252
6253 bnx2_netif_stop(bp);
6254
6255 bnx2_init_nic(bp, 1);
6256
6257 atomic_set(&bp->intr_sem, 1);
6258 bnx2_netif_start(bp);
6259 }
6260
6261 static void
6262 bnx2_tx_timeout(struct net_device *dev)
6263 {
6264 struct bnx2 *bp = netdev_priv(dev);
6265
6266 /* This allows the netif to be shutdown gracefully before resetting */
6267 schedule_work(&bp->reset_task);
6268 }
6269
6270 #ifdef BCM_VLAN
6271 /* Called with rtnl_lock */
6272 static void
6273 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6274 {
6275 struct bnx2 *bp = netdev_priv(dev);
6276
6277 if (netif_running(dev))
6278 bnx2_netif_stop(bp);
6279
6280 bp->vlgrp = vlgrp;
6281
6282 if (!netif_running(dev))
6283 return;
6284
6285 bnx2_set_rx_mode(dev);
6286 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6287 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6288
6289 bnx2_netif_start(bp);
6290 }
6291 #endif
6292
6293 /* Called with netif_tx_lock.
6294 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6295 * netif_wake_queue().
6296 */
6297 static netdev_tx_t
6298 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6299 {
6300 struct bnx2 *bp = netdev_priv(dev);
6301 dma_addr_t mapping;
6302 struct tx_bd *txbd;
6303 struct sw_tx_bd *tx_buf;
6304 u32 len, vlan_tag_flags, last_frag, mss;
6305 u16 prod, ring_prod;
6306 int i;
6307 struct bnx2_napi *bnapi;
6308 struct bnx2_tx_ring_info *txr;
6309 struct netdev_queue *txq;
6310 struct skb_shared_info *sp;
6311
6312 /* Determine which tx ring we will be placed on */
6313 i = skb_get_queue_mapping(skb);
6314 bnapi = &bp->bnx2_napi[i];
6315 txr = &bnapi->tx_ring;
6316 txq = netdev_get_tx_queue(dev, i);
6317
6318 if (unlikely(bnx2_tx_avail(bp, txr) <
6319 (skb_shinfo(skb)->nr_frags + 1))) {
6320 netif_tx_stop_queue(txq);
6321 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6322 dev->name);
6323
6324 return NETDEV_TX_BUSY;
6325 }
6326 len = skb_headlen(skb);
6327 prod = txr->tx_prod;
6328 ring_prod = TX_RING_IDX(prod);
6329
6330 vlan_tag_flags = 0;
6331 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6332 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6333 }
6334
6335 #ifdef BCM_VLAN
6336 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6337 vlan_tag_flags |=
6338 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6339 }
6340 #endif
6341 if ((mss = skb_shinfo(skb)->gso_size)) {
6342 u32 tcp_opt_len;
6343 struct iphdr *iph;
6344
6345 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6346
6347 tcp_opt_len = tcp_optlen(skb);
6348
6349 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6350 u32 tcp_off = skb_transport_offset(skb) -
6351 sizeof(struct ipv6hdr) - ETH_HLEN;
6352
6353 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6354 TX_BD_FLAGS_SW_FLAGS;
6355 if (likely(tcp_off == 0))
6356 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6357 else {
6358 tcp_off >>= 3;
6359 vlan_tag_flags |= ((tcp_off & 0x3) <<
6360 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6361 ((tcp_off & 0x10) <<
6362 TX_BD_FLAGS_TCP6_OFF4_SHL);
6363 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6364 }
6365 } else {
6366 iph = ip_hdr(skb);
6367 if (tcp_opt_len || (iph->ihl > 5)) {
6368 vlan_tag_flags |= ((iph->ihl - 5) +
6369 (tcp_opt_len >> 2)) << 8;
6370 }
6371 }
6372 } else
6373 mss = 0;
6374
6375 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
6376 dev_kfree_skb(skb);
6377 return NETDEV_TX_OK;
6378 }
6379
6380 sp = skb_shinfo(skb);
6381 mapping = sp->dma_head;
6382
6383 tx_buf = &txr->tx_buf_ring[ring_prod];
6384 tx_buf->skb = skb;
6385
6386 txbd = &txr->tx_desc_ring[ring_prod];
6387
6388 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6389 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6390 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6391 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6392
6393 last_frag = skb_shinfo(skb)->nr_frags;
6394 tx_buf->nr_frags = last_frag;
6395 tx_buf->is_gso = skb_is_gso(skb);
6396
6397 for (i = 0; i < last_frag; i++) {
6398 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6399
6400 prod = NEXT_TX_BD(prod);
6401 ring_prod = TX_RING_IDX(prod);
6402 txbd = &txr->tx_desc_ring[ring_prod];
6403
6404 len = frag->size;
6405 mapping = sp->dma_maps[i];
6406
6407 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6408 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6409 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6410 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6411
6412 }
6413 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6414
6415 prod = NEXT_TX_BD(prod);
6416 txr->tx_prod_bseq += skb->len;
6417
6418 REG_WR16(bp, txr->tx_bidx_addr, prod);
6419 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6420
6421 mmiowb();
6422
6423 txr->tx_prod = prod;
6424
6425 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6426 netif_tx_stop_queue(txq);
6427 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6428 netif_tx_wake_queue(txq);
6429 }
6430
6431 return NETDEV_TX_OK;
6432 }
6433
6434 /* Called with rtnl_lock */
6435 static int
6436 bnx2_close(struct net_device *dev)
6437 {
6438 struct bnx2 *bp = netdev_priv(dev);
6439
6440 cancel_work_sync(&bp->reset_task);
6441
6442 bnx2_disable_int_sync(bp);
6443 bnx2_napi_disable(bp);
6444 del_timer_sync(&bp->timer);
6445 bnx2_shutdown_chip(bp);
6446 bnx2_free_irq(bp);
6447 bnx2_free_skbs(bp);
6448 bnx2_free_mem(bp);
6449 bnx2_del_napi(bp);
6450 bp->link_up = 0;
6451 netif_carrier_off(bp->dev);
6452 bnx2_set_power_state(bp, PCI_D3hot);
6453 return 0;
6454 }
6455
6456 #define GET_NET_STATS64(ctr) \
6457 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6458 (unsigned long) (ctr##_lo)
6459
6460 #define GET_NET_STATS32(ctr) \
6461 (ctr##_lo)
6462
6463 #if (BITS_PER_LONG == 64)
6464 #define GET_NET_STATS GET_NET_STATS64
6465 #else
6466 #define GET_NET_STATS GET_NET_STATS32
6467 #endif
6468
6469 static struct net_device_stats *
6470 bnx2_get_stats(struct net_device *dev)
6471 {
6472 struct bnx2 *bp = netdev_priv(dev);
6473 struct statistics_block *stats_blk = bp->stats_blk;
6474 struct net_device_stats *net_stats = &dev->stats;
6475
6476 if (bp->stats_blk == NULL) {
6477 return net_stats;
6478 }
6479 net_stats->rx_packets =
6480 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6481 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6482 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6483
6484 net_stats->tx_packets =
6485 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6486 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6487 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6488
6489 net_stats->rx_bytes =
6490 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6491
6492 net_stats->tx_bytes =
6493 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6494
6495 net_stats->multicast =
6496 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6497
6498 net_stats->collisions =
6499 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6500
6501 net_stats->rx_length_errors =
6502 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6503 stats_blk->stat_EtherStatsOverrsizePkts);
6504
6505 net_stats->rx_over_errors =
6506 (unsigned long) (stats_blk->stat_IfInFTQDiscards +
6507 stats_blk->stat_IfInMBUFDiscards);
6508
6509 net_stats->rx_frame_errors =
6510 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6511
6512 net_stats->rx_crc_errors =
6513 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6514
6515 net_stats->rx_errors = net_stats->rx_length_errors +
6516 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6517 net_stats->rx_crc_errors;
6518
6519 net_stats->tx_aborted_errors =
6520 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6521 stats_blk->stat_Dot3StatsLateCollisions);
6522
6523 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6524 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6525 net_stats->tx_carrier_errors = 0;
6526 else {
6527 net_stats->tx_carrier_errors =
6528 (unsigned long)
6529 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6530 }
6531
6532 net_stats->tx_errors =
6533 (unsigned long)
6534 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6535 +
6536 net_stats->tx_aborted_errors +
6537 net_stats->tx_carrier_errors;
6538
6539 net_stats->rx_missed_errors =
6540 (unsigned long) (stats_blk->stat_IfInFTQDiscards +
6541 stats_blk->stat_IfInMBUFDiscards + stats_blk->stat_FwRxDrop);
6542
6543 return net_stats;
6544 }
6545
6546 /* All ethtool functions called with rtnl_lock */
6547
6548 static int
6549 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6550 {
6551 struct bnx2 *bp = netdev_priv(dev);
6552 int support_serdes = 0, support_copper = 0;
6553
6554 cmd->supported = SUPPORTED_Autoneg;
6555 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6556 support_serdes = 1;
6557 support_copper = 1;
6558 } else if (bp->phy_port == PORT_FIBRE)
6559 support_serdes = 1;
6560 else
6561 support_copper = 1;
6562
6563 if (support_serdes) {
6564 cmd->supported |= SUPPORTED_1000baseT_Full |
6565 SUPPORTED_FIBRE;
6566 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6567 cmd->supported |= SUPPORTED_2500baseX_Full;
6568
6569 }
6570 if (support_copper) {
6571 cmd->supported |= SUPPORTED_10baseT_Half |
6572 SUPPORTED_10baseT_Full |
6573 SUPPORTED_100baseT_Half |
6574 SUPPORTED_100baseT_Full |
6575 SUPPORTED_1000baseT_Full |
6576 SUPPORTED_TP;
6577
6578 }
6579
6580 spin_lock_bh(&bp->phy_lock);
6581 cmd->port = bp->phy_port;
6582 cmd->advertising = bp->advertising;
6583
6584 if (bp->autoneg & AUTONEG_SPEED) {
6585 cmd->autoneg = AUTONEG_ENABLE;
6586 }
6587 else {
6588 cmd->autoneg = AUTONEG_DISABLE;
6589 }
6590
6591 if (netif_carrier_ok(dev)) {
6592 cmd->speed = bp->line_speed;
6593 cmd->duplex = bp->duplex;
6594 }
6595 else {
6596 cmd->speed = -1;
6597 cmd->duplex = -1;
6598 }
6599 spin_unlock_bh(&bp->phy_lock);
6600
6601 cmd->transceiver = XCVR_INTERNAL;
6602 cmd->phy_address = bp->phy_addr;
6603
6604 return 0;
6605 }
6606
6607 static int
6608 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6609 {
6610 struct bnx2 *bp = netdev_priv(dev);
6611 u8 autoneg = bp->autoneg;
6612 u8 req_duplex = bp->req_duplex;
6613 u16 req_line_speed = bp->req_line_speed;
6614 u32 advertising = bp->advertising;
6615 int err = -EINVAL;
6616
6617 spin_lock_bh(&bp->phy_lock);
6618
6619 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6620 goto err_out_unlock;
6621
6622 if (cmd->port != bp->phy_port &&
6623 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6624 goto err_out_unlock;
6625
6626 /* If device is down, we can store the settings only if the user
6627 * is setting the currently active port.
6628 */
6629 if (!netif_running(dev) && cmd->port != bp->phy_port)
6630 goto err_out_unlock;
6631
6632 if (cmd->autoneg == AUTONEG_ENABLE) {
6633 autoneg |= AUTONEG_SPEED;
6634
6635 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6636
6637 /* allow advertising 1 speed */
6638 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6639 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6640 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6641 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6642
6643 if (cmd->port == PORT_FIBRE)
6644 goto err_out_unlock;
6645
6646 advertising = cmd->advertising;
6647
6648 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6649 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6650 (cmd->port == PORT_TP))
6651 goto err_out_unlock;
6652 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6653 advertising = cmd->advertising;
6654 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6655 goto err_out_unlock;
6656 else {
6657 if (cmd->port == PORT_FIBRE)
6658 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6659 else
6660 advertising = ETHTOOL_ALL_COPPER_SPEED;
6661 }
6662 advertising |= ADVERTISED_Autoneg;
6663 }
6664 else {
6665 if (cmd->port == PORT_FIBRE) {
6666 if ((cmd->speed != SPEED_1000 &&
6667 cmd->speed != SPEED_2500) ||
6668 (cmd->duplex != DUPLEX_FULL))
6669 goto err_out_unlock;
6670
6671 if (cmd->speed == SPEED_2500 &&
6672 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6673 goto err_out_unlock;
6674 }
6675 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6676 goto err_out_unlock;
6677
6678 autoneg &= ~AUTONEG_SPEED;
6679 req_line_speed = cmd->speed;
6680 req_duplex = cmd->duplex;
6681 advertising = 0;
6682 }
6683
6684 bp->autoneg = autoneg;
6685 bp->advertising = advertising;
6686 bp->req_line_speed = req_line_speed;
6687 bp->req_duplex = req_duplex;
6688
6689 err = 0;
6690 /* If device is down, the new settings will be picked up when it is
6691 * brought up.
6692 */
6693 if (netif_running(dev))
6694 err = bnx2_setup_phy(bp, cmd->port);
6695
6696 err_out_unlock:
6697 spin_unlock_bh(&bp->phy_lock);
6698
6699 return err;
6700 }
6701
6702 static void
6703 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6704 {
6705 struct bnx2 *bp = netdev_priv(dev);
6706
6707 strcpy(info->driver, DRV_MODULE_NAME);
6708 strcpy(info->version, DRV_MODULE_VERSION);
6709 strcpy(info->bus_info, pci_name(bp->pdev));
6710 strcpy(info->fw_version, bp->fw_version);
6711 }
6712
6713 #define BNX2_REGDUMP_LEN (32 * 1024)
6714
6715 static int
6716 bnx2_get_regs_len(struct net_device *dev)
6717 {
6718 return BNX2_REGDUMP_LEN;
6719 }
6720
6721 static void
6722 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6723 {
6724 u32 *p = _p, i, offset;
6725 u8 *orig_p = _p;
6726 struct bnx2 *bp = netdev_priv(dev);
6727 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6728 0x0800, 0x0880, 0x0c00, 0x0c10,
6729 0x0c30, 0x0d08, 0x1000, 0x101c,
6730 0x1040, 0x1048, 0x1080, 0x10a4,
6731 0x1400, 0x1490, 0x1498, 0x14f0,
6732 0x1500, 0x155c, 0x1580, 0x15dc,
6733 0x1600, 0x1658, 0x1680, 0x16d8,
6734 0x1800, 0x1820, 0x1840, 0x1854,
6735 0x1880, 0x1894, 0x1900, 0x1984,
6736 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6737 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6738 0x2000, 0x2030, 0x23c0, 0x2400,
6739 0x2800, 0x2820, 0x2830, 0x2850,
6740 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6741 0x3c00, 0x3c94, 0x4000, 0x4010,
6742 0x4080, 0x4090, 0x43c0, 0x4458,
6743 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6744 0x4fc0, 0x5010, 0x53c0, 0x5444,
6745 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6746 0x5fc0, 0x6000, 0x6400, 0x6428,
6747 0x6800, 0x6848, 0x684c, 0x6860,
6748 0x6888, 0x6910, 0x8000 };
6749
6750 regs->version = 0;
6751
6752 memset(p, 0, BNX2_REGDUMP_LEN);
6753
6754 if (!netif_running(bp->dev))
6755 return;
6756
6757 i = 0;
6758 offset = reg_boundaries[0];
6759 p += offset;
6760 while (offset < BNX2_REGDUMP_LEN) {
6761 *p++ = REG_RD(bp, offset);
6762 offset += 4;
6763 if (offset == reg_boundaries[i + 1]) {
6764 offset = reg_boundaries[i + 2];
6765 p = (u32 *) (orig_p + offset);
6766 i += 2;
6767 }
6768 }
6769 }
6770
6771 static void
6772 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6773 {
6774 struct bnx2 *bp = netdev_priv(dev);
6775
6776 if (bp->flags & BNX2_FLAG_NO_WOL) {
6777 wol->supported = 0;
6778 wol->wolopts = 0;
6779 }
6780 else {
6781 wol->supported = WAKE_MAGIC;
6782 if (bp->wol)
6783 wol->wolopts = WAKE_MAGIC;
6784 else
6785 wol->wolopts = 0;
6786 }
6787 memset(&wol->sopass, 0, sizeof(wol->sopass));
6788 }
6789
6790 static int
6791 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6792 {
6793 struct bnx2 *bp = netdev_priv(dev);
6794
6795 if (wol->wolopts & ~WAKE_MAGIC)
6796 return -EINVAL;
6797
6798 if (wol->wolopts & WAKE_MAGIC) {
6799 if (bp->flags & BNX2_FLAG_NO_WOL)
6800 return -EINVAL;
6801
6802 bp->wol = 1;
6803 }
6804 else {
6805 bp->wol = 0;
6806 }
6807 return 0;
6808 }
6809
6810 static int
6811 bnx2_nway_reset(struct net_device *dev)
6812 {
6813 struct bnx2 *bp = netdev_priv(dev);
6814 u32 bmcr;
6815
6816 if (!netif_running(dev))
6817 return -EAGAIN;
6818
6819 if (!(bp->autoneg & AUTONEG_SPEED)) {
6820 return -EINVAL;
6821 }
6822
6823 spin_lock_bh(&bp->phy_lock);
6824
6825 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6826 int rc;
6827
6828 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6829 spin_unlock_bh(&bp->phy_lock);
6830 return rc;
6831 }
6832
6833 /* Force a link down visible on the other side */
6834 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6835 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6836 spin_unlock_bh(&bp->phy_lock);
6837
6838 msleep(20);
6839
6840 spin_lock_bh(&bp->phy_lock);
6841
6842 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6843 bp->serdes_an_pending = 1;
6844 mod_timer(&bp->timer, jiffies + bp->current_interval);
6845 }
6846
6847 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6848 bmcr &= ~BMCR_LOOPBACK;
6849 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6850
6851 spin_unlock_bh(&bp->phy_lock);
6852
6853 return 0;
6854 }
6855
6856 static u32
6857 bnx2_get_link(struct net_device *dev)
6858 {
6859 struct bnx2 *bp = netdev_priv(dev);
6860
6861 return bp->link_up;
6862 }
6863
6864 static int
6865 bnx2_get_eeprom_len(struct net_device *dev)
6866 {
6867 struct bnx2 *bp = netdev_priv(dev);
6868
6869 if (bp->flash_info == NULL)
6870 return 0;
6871
6872 return (int) bp->flash_size;
6873 }
6874
6875 static int
6876 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6877 u8 *eebuf)
6878 {
6879 struct bnx2 *bp = netdev_priv(dev);
6880 int rc;
6881
6882 if (!netif_running(dev))
6883 return -EAGAIN;
6884
6885 /* parameters already validated in ethtool_get_eeprom */
6886
6887 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6888
6889 return rc;
6890 }
6891
6892 static int
6893 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6894 u8 *eebuf)
6895 {
6896 struct bnx2 *bp = netdev_priv(dev);
6897 int rc;
6898
6899 if (!netif_running(dev))
6900 return -EAGAIN;
6901
6902 /* parameters already validated in ethtool_set_eeprom */
6903
6904 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6905
6906 return rc;
6907 }
6908
6909 static int
6910 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6911 {
6912 struct bnx2 *bp = netdev_priv(dev);
6913
6914 memset(coal, 0, sizeof(struct ethtool_coalesce));
6915
6916 coal->rx_coalesce_usecs = bp->rx_ticks;
6917 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6918 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6919 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6920
6921 coal->tx_coalesce_usecs = bp->tx_ticks;
6922 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6923 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6924 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6925
6926 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6927
6928 return 0;
6929 }
6930
6931 static int
6932 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6933 {
6934 struct bnx2 *bp = netdev_priv(dev);
6935
6936 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6937 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6938
6939 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6940 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6941
6942 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6943 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6944
6945 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6946 if (bp->rx_quick_cons_trip_int > 0xff)
6947 bp->rx_quick_cons_trip_int = 0xff;
6948
6949 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6950 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6951
6952 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6953 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6954
6955 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6956 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6957
6958 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6959 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6960 0xff;
6961
6962 bp->stats_ticks = coal->stats_block_coalesce_usecs;
6963 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
6964 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6965 bp->stats_ticks = USEC_PER_SEC;
6966 }
6967 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6968 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6969 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6970
6971 if (netif_running(bp->dev)) {
6972 bnx2_netif_stop(bp);
6973 bnx2_init_nic(bp, 0);
6974 bnx2_netif_start(bp);
6975 }
6976
6977 return 0;
6978 }
6979
6980 static void
6981 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6982 {
6983 struct bnx2 *bp = netdev_priv(dev);
6984
6985 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6986 ering->rx_mini_max_pending = 0;
6987 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6988
6989 ering->rx_pending = bp->rx_ring_size;
6990 ering->rx_mini_pending = 0;
6991 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6992
6993 ering->tx_max_pending = MAX_TX_DESC_CNT;
6994 ering->tx_pending = bp->tx_ring_size;
6995 }
6996
6997 static int
6998 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6999 {
7000 if (netif_running(bp->dev)) {
7001 bnx2_netif_stop(bp);
7002 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7003 bnx2_free_skbs(bp);
7004 bnx2_free_mem(bp);
7005 }
7006
7007 bnx2_set_rx_ring_size(bp, rx);
7008 bp->tx_ring_size = tx;
7009
7010 if (netif_running(bp->dev)) {
7011 int rc;
7012
7013 rc = bnx2_alloc_mem(bp);
7014 if (!rc)
7015 rc = bnx2_init_nic(bp, 0);
7016
7017 if (rc) {
7018 bnx2_napi_enable(bp);
7019 dev_close(bp->dev);
7020 return rc;
7021 }
7022 bnx2_netif_start(bp);
7023 }
7024 return 0;
7025 }
7026
7027 static int
7028 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7029 {
7030 struct bnx2 *bp = netdev_priv(dev);
7031 int rc;
7032
7033 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7034 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7035 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7036
7037 return -EINVAL;
7038 }
7039 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7040 return rc;
7041 }
7042
7043 static void
7044 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7045 {
7046 struct bnx2 *bp = netdev_priv(dev);
7047
7048 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7049 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7050 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7051 }
7052
7053 static int
7054 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7055 {
7056 struct bnx2 *bp = netdev_priv(dev);
7057
7058 bp->req_flow_ctrl = 0;
7059 if (epause->rx_pause)
7060 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7061 if (epause->tx_pause)
7062 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7063
7064 if (epause->autoneg) {
7065 bp->autoneg |= AUTONEG_FLOW_CTRL;
7066 }
7067 else {
7068 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7069 }
7070
7071 if (netif_running(dev)) {
7072 spin_lock_bh(&bp->phy_lock);
7073 bnx2_setup_phy(bp, bp->phy_port);
7074 spin_unlock_bh(&bp->phy_lock);
7075 }
7076
7077 return 0;
7078 }
7079
7080 static u32
7081 bnx2_get_rx_csum(struct net_device *dev)
7082 {
7083 struct bnx2 *bp = netdev_priv(dev);
7084
7085 return bp->rx_csum;
7086 }
7087
7088 static int
7089 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7090 {
7091 struct bnx2 *bp = netdev_priv(dev);
7092
7093 bp->rx_csum = data;
7094 return 0;
7095 }
7096
7097 static int
7098 bnx2_set_tso(struct net_device *dev, u32 data)
7099 {
7100 struct bnx2 *bp = netdev_priv(dev);
7101
7102 if (data) {
7103 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7104 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7105 dev->features |= NETIF_F_TSO6;
7106 } else
7107 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7108 NETIF_F_TSO_ECN);
7109 return 0;
7110 }
7111
7112 static struct {
7113 char string[ETH_GSTRING_LEN];
7114 } bnx2_stats_str_arr[] = {
7115 { "rx_bytes" },
7116 { "rx_error_bytes" },
7117 { "tx_bytes" },
7118 { "tx_error_bytes" },
7119 { "rx_ucast_packets" },
7120 { "rx_mcast_packets" },
7121 { "rx_bcast_packets" },
7122 { "tx_ucast_packets" },
7123 { "tx_mcast_packets" },
7124 { "tx_bcast_packets" },
7125 { "tx_mac_errors" },
7126 { "tx_carrier_errors" },
7127 { "rx_crc_errors" },
7128 { "rx_align_errors" },
7129 { "tx_single_collisions" },
7130 { "tx_multi_collisions" },
7131 { "tx_deferred" },
7132 { "tx_excess_collisions" },
7133 { "tx_late_collisions" },
7134 { "tx_total_collisions" },
7135 { "rx_fragments" },
7136 { "rx_jabbers" },
7137 { "rx_undersize_packets" },
7138 { "rx_oversize_packets" },
7139 { "rx_64_byte_packets" },
7140 { "rx_65_to_127_byte_packets" },
7141 { "rx_128_to_255_byte_packets" },
7142 { "rx_256_to_511_byte_packets" },
7143 { "rx_512_to_1023_byte_packets" },
7144 { "rx_1024_to_1522_byte_packets" },
7145 { "rx_1523_to_9022_byte_packets" },
7146 { "tx_64_byte_packets" },
7147 { "tx_65_to_127_byte_packets" },
7148 { "tx_128_to_255_byte_packets" },
7149 { "tx_256_to_511_byte_packets" },
7150 { "tx_512_to_1023_byte_packets" },
7151 { "tx_1024_to_1522_byte_packets" },
7152 { "tx_1523_to_9022_byte_packets" },
7153 { "rx_xon_frames" },
7154 { "rx_xoff_frames" },
7155 { "tx_xon_frames" },
7156 { "tx_xoff_frames" },
7157 { "rx_mac_ctrl_frames" },
7158 { "rx_filtered_packets" },
7159 { "rx_ftq_discards" },
7160 { "rx_discards" },
7161 { "rx_fw_discards" },
7162 };
7163
7164 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7165 sizeof(bnx2_stats_str_arr[0]))
7166
7167 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7168
7169 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7170 STATS_OFFSET32(stat_IfHCInOctets_hi),
7171 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7172 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7173 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7174 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7175 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7176 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7177 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7178 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7179 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7180 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7181 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7182 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7183 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7184 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7185 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7186 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7187 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7188 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7189 STATS_OFFSET32(stat_EtherStatsCollisions),
7190 STATS_OFFSET32(stat_EtherStatsFragments),
7191 STATS_OFFSET32(stat_EtherStatsJabbers),
7192 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7193 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7194 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7195 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7196 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7197 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7198 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7199 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7200 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7201 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7202 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7203 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7204 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7205 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7206 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7207 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7208 STATS_OFFSET32(stat_XonPauseFramesReceived),
7209 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7210 STATS_OFFSET32(stat_OutXonSent),
7211 STATS_OFFSET32(stat_OutXoffSent),
7212 STATS_OFFSET32(stat_MacControlFramesReceived),
7213 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7214 STATS_OFFSET32(stat_IfInFTQDiscards),
7215 STATS_OFFSET32(stat_IfInMBUFDiscards),
7216 STATS_OFFSET32(stat_FwRxDrop),
7217 };
7218
7219 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7220 * skipped because of errata.
7221 */
7222 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7223 8,0,8,8,8,8,8,8,8,8,
7224 4,0,4,4,4,4,4,4,4,4,
7225 4,4,4,4,4,4,4,4,4,4,
7226 4,4,4,4,4,4,4,4,4,4,
7227 4,4,4,4,4,4,4,
7228 };
7229
7230 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7231 8,0,8,8,8,8,8,8,8,8,
7232 4,4,4,4,4,4,4,4,4,4,
7233 4,4,4,4,4,4,4,4,4,4,
7234 4,4,4,4,4,4,4,4,4,4,
7235 4,4,4,4,4,4,4,
7236 };
7237
7238 #define BNX2_NUM_TESTS 6
7239
7240 static struct {
7241 char string[ETH_GSTRING_LEN];
7242 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7243 { "register_test (offline)" },
7244 { "memory_test (offline)" },
7245 { "loopback_test (offline)" },
7246 { "nvram_test (online)" },
7247 { "interrupt_test (online)" },
7248 { "link_test (online)" },
7249 };
7250
7251 static int
7252 bnx2_get_sset_count(struct net_device *dev, int sset)
7253 {
7254 switch (sset) {
7255 case ETH_SS_TEST:
7256 return BNX2_NUM_TESTS;
7257 case ETH_SS_STATS:
7258 return BNX2_NUM_STATS;
7259 default:
7260 return -EOPNOTSUPP;
7261 }
7262 }
7263
7264 static void
7265 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7266 {
7267 struct bnx2 *bp = netdev_priv(dev);
7268
7269 bnx2_set_power_state(bp, PCI_D0);
7270
7271 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7272 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7273 int i;
7274
7275 bnx2_netif_stop(bp);
7276 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7277 bnx2_free_skbs(bp);
7278
7279 if (bnx2_test_registers(bp) != 0) {
7280 buf[0] = 1;
7281 etest->flags |= ETH_TEST_FL_FAILED;
7282 }
7283 if (bnx2_test_memory(bp) != 0) {
7284 buf[1] = 1;
7285 etest->flags |= ETH_TEST_FL_FAILED;
7286 }
7287 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7288 etest->flags |= ETH_TEST_FL_FAILED;
7289
7290 if (!netif_running(bp->dev))
7291 bnx2_shutdown_chip(bp);
7292 else {
7293 bnx2_init_nic(bp, 1);
7294 bnx2_netif_start(bp);
7295 }
7296
7297 /* wait for link up */
7298 for (i = 0; i < 7; i++) {
7299 if (bp->link_up)
7300 break;
7301 msleep_interruptible(1000);
7302 }
7303 }
7304
7305 if (bnx2_test_nvram(bp) != 0) {
7306 buf[3] = 1;
7307 etest->flags |= ETH_TEST_FL_FAILED;
7308 }
7309 if (bnx2_test_intr(bp) != 0) {
7310 buf[4] = 1;
7311 etest->flags |= ETH_TEST_FL_FAILED;
7312 }
7313
7314 if (bnx2_test_link(bp) != 0) {
7315 buf[5] = 1;
7316 etest->flags |= ETH_TEST_FL_FAILED;
7317
7318 }
7319 if (!netif_running(bp->dev))
7320 bnx2_set_power_state(bp, PCI_D3hot);
7321 }
7322
7323 static void
7324 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7325 {
7326 switch (stringset) {
7327 case ETH_SS_STATS:
7328 memcpy(buf, bnx2_stats_str_arr,
7329 sizeof(bnx2_stats_str_arr));
7330 break;
7331 case ETH_SS_TEST:
7332 memcpy(buf, bnx2_tests_str_arr,
7333 sizeof(bnx2_tests_str_arr));
7334 break;
7335 }
7336 }
7337
7338 static void
7339 bnx2_get_ethtool_stats(struct net_device *dev,
7340 struct ethtool_stats *stats, u64 *buf)
7341 {
7342 struct bnx2 *bp = netdev_priv(dev);
7343 int i;
7344 u32 *hw_stats = (u32 *) bp->stats_blk;
7345 u8 *stats_len_arr = NULL;
7346
7347 if (hw_stats == NULL) {
7348 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7349 return;
7350 }
7351
7352 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7353 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7354 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7355 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7356 stats_len_arr = bnx2_5706_stats_len_arr;
7357 else
7358 stats_len_arr = bnx2_5708_stats_len_arr;
7359
7360 for (i = 0; i < BNX2_NUM_STATS; i++) {
7361 if (stats_len_arr[i] == 0) {
7362 /* skip this counter */
7363 buf[i] = 0;
7364 continue;
7365 }
7366 if (stats_len_arr[i] == 4) {
7367 /* 4-byte counter */
7368 buf[i] = (u64)
7369 *(hw_stats + bnx2_stats_offset_arr[i]);
7370 continue;
7371 }
7372 /* 8-byte counter */
7373 buf[i] = (((u64) *(hw_stats +
7374 bnx2_stats_offset_arr[i])) << 32) +
7375 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7376 }
7377 }
7378
7379 static int
7380 bnx2_phys_id(struct net_device *dev, u32 data)
7381 {
7382 struct bnx2 *bp = netdev_priv(dev);
7383 int i;
7384 u32 save;
7385
7386 bnx2_set_power_state(bp, PCI_D0);
7387
7388 if (data == 0)
7389 data = 2;
7390
7391 save = REG_RD(bp, BNX2_MISC_CFG);
7392 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7393
7394 for (i = 0; i < (data * 2); i++) {
7395 if ((i % 2) == 0) {
7396 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7397 }
7398 else {
7399 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7400 BNX2_EMAC_LED_1000MB_OVERRIDE |
7401 BNX2_EMAC_LED_100MB_OVERRIDE |
7402 BNX2_EMAC_LED_10MB_OVERRIDE |
7403 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7404 BNX2_EMAC_LED_TRAFFIC);
7405 }
7406 msleep_interruptible(500);
7407 if (signal_pending(current))
7408 break;
7409 }
7410 REG_WR(bp, BNX2_EMAC_LED, 0);
7411 REG_WR(bp, BNX2_MISC_CFG, save);
7412
7413 if (!netif_running(dev))
7414 bnx2_set_power_state(bp, PCI_D3hot);
7415
7416 return 0;
7417 }
7418
7419 static int
7420 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7421 {
7422 struct bnx2 *bp = netdev_priv(dev);
7423
7424 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7425 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7426 else
7427 return (ethtool_op_set_tx_csum(dev, data));
7428 }
7429
7430 static const struct ethtool_ops bnx2_ethtool_ops = {
7431 .get_settings = bnx2_get_settings,
7432 .set_settings = bnx2_set_settings,
7433 .get_drvinfo = bnx2_get_drvinfo,
7434 .get_regs_len = bnx2_get_regs_len,
7435 .get_regs = bnx2_get_regs,
7436 .get_wol = bnx2_get_wol,
7437 .set_wol = bnx2_set_wol,
7438 .nway_reset = bnx2_nway_reset,
7439 .get_link = bnx2_get_link,
7440 .get_eeprom_len = bnx2_get_eeprom_len,
7441 .get_eeprom = bnx2_get_eeprom,
7442 .set_eeprom = bnx2_set_eeprom,
7443 .get_coalesce = bnx2_get_coalesce,
7444 .set_coalesce = bnx2_set_coalesce,
7445 .get_ringparam = bnx2_get_ringparam,
7446 .set_ringparam = bnx2_set_ringparam,
7447 .get_pauseparam = bnx2_get_pauseparam,
7448 .set_pauseparam = bnx2_set_pauseparam,
7449 .get_rx_csum = bnx2_get_rx_csum,
7450 .set_rx_csum = bnx2_set_rx_csum,
7451 .set_tx_csum = bnx2_set_tx_csum,
7452 .set_sg = ethtool_op_set_sg,
7453 .set_tso = bnx2_set_tso,
7454 .self_test = bnx2_self_test,
7455 .get_strings = bnx2_get_strings,
7456 .phys_id = bnx2_phys_id,
7457 .get_ethtool_stats = bnx2_get_ethtool_stats,
7458 .get_sset_count = bnx2_get_sset_count,
7459 };
7460
7461 /* Called with rtnl_lock */
7462 static int
7463 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7464 {
7465 struct mii_ioctl_data *data = if_mii(ifr);
7466 struct bnx2 *bp = netdev_priv(dev);
7467 int err;
7468
7469 switch(cmd) {
7470 case SIOCGMIIPHY:
7471 data->phy_id = bp->phy_addr;
7472
7473 /* fallthru */
7474 case SIOCGMIIREG: {
7475 u32 mii_regval;
7476
7477 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7478 return -EOPNOTSUPP;
7479
7480 if (!netif_running(dev))
7481 return -EAGAIN;
7482
7483 spin_lock_bh(&bp->phy_lock);
7484 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7485 spin_unlock_bh(&bp->phy_lock);
7486
7487 data->val_out = mii_regval;
7488
7489 return err;
7490 }
7491
7492 case SIOCSMIIREG:
7493 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7494 return -EOPNOTSUPP;
7495
7496 if (!netif_running(dev))
7497 return -EAGAIN;
7498
7499 spin_lock_bh(&bp->phy_lock);
7500 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7501 spin_unlock_bh(&bp->phy_lock);
7502
7503 return err;
7504
7505 default:
7506 /* do nothing */
7507 break;
7508 }
7509 return -EOPNOTSUPP;
7510 }
7511
7512 /* Called with rtnl_lock */
7513 static int
7514 bnx2_change_mac_addr(struct net_device *dev, void *p)
7515 {
7516 struct sockaddr *addr = p;
7517 struct bnx2 *bp = netdev_priv(dev);
7518
7519 if (!is_valid_ether_addr(addr->sa_data))
7520 return -EINVAL;
7521
7522 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7523 if (netif_running(dev))
7524 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7525
7526 return 0;
7527 }
7528
7529 /* Called with rtnl_lock */
7530 static int
7531 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7532 {
7533 struct bnx2 *bp = netdev_priv(dev);
7534
7535 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7536 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7537 return -EINVAL;
7538
7539 dev->mtu = new_mtu;
7540 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7541 }
7542
7543 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7544 static void
7545 poll_bnx2(struct net_device *dev)
7546 {
7547 struct bnx2 *bp = netdev_priv(dev);
7548 int i;
7549
7550 for (i = 0; i < bp->irq_nvecs; i++) {
7551 disable_irq(bp->irq_tbl[i].vector);
7552 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7553 enable_irq(bp->irq_tbl[i].vector);
7554 }
7555 }
7556 #endif
7557
7558 static void __devinit
7559 bnx2_get_5709_media(struct bnx2 *bp)
7560 {
7561 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7562 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7563 u32 strap;
7564
7565 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7566 return;
7567 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7568 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7569 return;
7570 }
7571
7572 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7573 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7574 else
7575 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7576
7577 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7578 switch (strap) {
7579 case 0x4:
7580 case 0x5:
7581 case 0x6:
7582 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7583 return;
7584 }
7585 } else {
7586 switch (strap) {
7587 case 0x1:
7588 case 0x2:
7589 case 0x4:
7590 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7591 return;
7592 }
7593 }
7594 }
7595
7596 static void __devinit
7597 bnx2_get_pci_speed(struct bnx2 *bp)
7598 {
7599 u32 reg;
7600
7601 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7602 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7603 u32 clkreg;
7604
7605 bp->flags |= BNX2_FLAG_PCIX;
7606
7607 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7608
7609 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7610 switch (clkreg) {
7611 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7612 bp->bus_speed_mhz = 133;
7613 break;
7614
7615 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7616 bp->bus_speed_mhz = 100;
7617 break;
7618
7619 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7620 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7621 bp->bus_speed_mhz = 66;
7622 break;
7623
7624 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7625 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7626 bp->bus_speed_mhz = 50;
7627 break;
7628
7629 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7630 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7631 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7632 bp->bus_speed_mhz = 33;
7633 break;
7634 }
7635 }
7636 else {
7637 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7638 bp->bus_speed_mhz = 66;
7639 else
7640 bp->bus_speed_mhz = 33;
7641 }
7642
7643 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7644 bp->flags |= BNX2_FLAG_PCI_32BIT;
7645
7646 }
7647
7648 static int __devinit
7649 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7650 {
7651 struct bnx2 *bp;
7652 unsigned long mem_len;
7653 int rc, i, j;
7654 u32 reg;
7655 u64 dma_mask, persist_dma_mask;
7656
7657 SET_NETDEV_DEV(dev, &pdev->dev);
7658 bp = netdev_priv(dev);
7659
7660 bp->flags = 0;
7661 bp->phy_flags = 0;
7662
7663 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7664 rc = pci_enable_device(pdev);
7665 if (rc) {
7666 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7667 goto err_out;
7668 }
7669
7670 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7671 dev_err(&pdev->dev,
7672 "Cannot find PCI device base address, aborting.\n");
7673 rc = -ENODEV;
7674 goto err_out_disable;
7675 }
7676
7677 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7678 if (rc) {
7679 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7680 goto err_out_disable;
7681 }
7682
7683 pci_set_master(pdev);
7684 pci_save_state(pdev);
7685
7686 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7687 if (bp->pm_cap == 0) {
7688 dev_err(&pdev->dev,
7689 "Cannot find power management capability, aborting.\n");
7690 rc = -EIO;
7691 goto err_out_release;
7692 }
7693
7694 bp->dev = dev;
7695 bp->pdev = pdev;
7696
7697 spin_lock_init(&bp->phy_lock);
7698 spin_lock_init(&bp->indirect_lock);
7699 #ifdef BCM_CNIC
7700 mutex_init(&bp->cnic_lock);
7701 #endif
7702 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7703
7704 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7705 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7706 dev->mem_end = dev->mem_start + mem_len;
7707 dev->irq = pdev->irq;
7708
7709 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7710
7711 if (!bp->regview) {
7712 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7713 rc = -ENOMEM;
7714 goto err_out_release;
7715 }
7716
7717 /* Configure byte swap and enable write to the reg_window registers.
7718 * Rely on CPU to do target byte swapping on big endian systems
7719 * The chip's target access swapping will not swap all accesses
7720 */
7721 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7722 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7723 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7724
7725 bnx2_set_power_state(bp, PCI_D0);
7726
7727 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7728
7729 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7730 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7731 dev_err(&pdev->dev,
7732 "Cannot find PCIE capability, aborting.\n");
7733 rc = -EIO;
7734 goto err_out_unmap;
7735 }
7736 bp->flags |= BNX2_FLAG_PCIE;
7737 if (CHIP_REV(bp) == CHIP_REV_Ax)
7738 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7739 } else {
7740 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7741 if (bp->pcix_cap == 0) {
7742 dev_err(&pdev->dev,
7743 "Cannot find PCIX capability, aborting.\n");
7744 rc = -EIO;
7745 goto err_out_unmap;
7746 }
7747 bp->flags |= BNX2_FLAG_BROKEN_STATS;
7748 }
7749
7750 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7751 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7752 bp->flags |= BNX2_FLAG_MSIX_CAP;
7753 }
7754
7755 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7756 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7757 bp->flags |= BNX2_FLAG_MSI_CAP;
7758 }
7759
7760 /* 5708 cannot support DMA addresses > 40-bit. */
7761 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7762 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7763 else
7764 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7765
7766 /* Configure DMA attributes. */
7767 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7768 dev->features |= NETIF_F_HIGHDMA;
7769 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7770 if (rc) {
7771 dev_err(&pdev->dev,
7772 "pci_set_consistent_dma_mask failed, aborting.\n");
7773 goto err_out_unmap;
7774 }
7775 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7776 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7777 goto err_out_unmap;
7778 }
7779
7780 if (!(bp->flags & BNX2_FLAG_PCIE))
7781 bnx2_get_pci_speed(bp);
7782
7783 /* 5706A0 may falsely detect SERR and PERR. */
7784 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7785 reg = REG_RD(bp, PCI_COMMAND);
7786 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7787 REG_WR(bp, PCI_COMMAND, reg);
7788 }
7789 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7790 !(bp->flags & BNX2_FLAG_PCIX)) {
7791
7792 dev_err(&pdev->dev,
7793 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7794 goto err_out_unmap;
7795 }
7796
7797 bnx2_init_nvram(bp);
7798
7799 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7800
7801 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7802 BNX2_SHM_HDR_SIGNATURE_SIG) {
7803 u32 off = PCI_FUNC(pdev->devfn) << 2;
7804
7805 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7806 } else
7807 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7808
7809 /* Get the permanent MAC address. First we need to make sure the
7810 * firmware is actually running.
7811 */
7812 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7813
7814 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7815 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7816 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7817 rc = -ENODEV;
7818 goto err_out_unmap;
7819 }
7820
7821 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7822 for (i = 0, j = 0; i < 3; i++) {
7823 u8 num, k, skip0;
7824
7825 num = (u8) (reg >> (24 - (i * 8)));
7826 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7827 if (num >= k || !skip0 || k == 1) {
7828 bp->fw_version[j++] = (num / k) + '0';
7829 skip0 = 0;
7830 }
7831 }
7832 if (i != 2)
7833 bp->fw_version[j++] = '.';
7834 }
7835 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7836 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7837 bp->wol = 1;
7838
7839 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7840 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7841
7842 for (i = 0; i < 30; i++) {
7843 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7844 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7845 break;
7846 msleep(10);
7847 }
7848 }
7849 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7850 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7851 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7852 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7853 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7854
7855 bp->fw_version[j++] = ' ';
7856 for (i = 0; i < 3; i++) {
7857 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7858 reg = swab32(reg);
7859 memcpy(&bp->fw_version[j], &reg, 4);
7860 j += 4;
7861 }
7862 }
7863
7864 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7865 bp->mac_addr[0] = (u8) (reg >> 8);
7866 bp->mac_addr[1] = (u8) reg;
7867
7868 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7869 bp->mac_addr[2] = (u8) (reg >> 24);
7870 bp->mac_addr[3] = (u8) (reg >> 16);
7871 bp->mac_addr[4] = (u8) (reg >> 8);
7872 bp->mac_addr[5] = (u8) reg;
7873
7874 bp->tx_ring_size = MAX_TX_DESC_CNT;
7875 bnx2_set_rx_ring_size(bp, 255);
7876
7877 bp->rx_csum = 1;
7878
7879 bp->tx_quick_cons_trip_int = 2;
7880 bp->tx_quick_cons_trip = 20;
7881 bp->tx_ticks_int = 18;
7882 bp->tx_ticks = 80;
7883
7884 bp->rx_quick_cons_trip_int = 2;
7885 bp->rx_quick_cons_trip = 12;
7886 bp->rx_ticks_int = 18;
7887 bp->rx_ticks = 18;
7888
7889 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7890
7891 bp->current_interval = BNX2_TIMER_INTERVAL;
7892
7893 bp->phy_addr = 1;
7894
7895 /* Disable WOL support if we are running on a SERDES chip. */
7896 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7897 bnx2_get_5709_media(bp);
7898 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7899 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7900
7901 bp->phy_port = PORT_TP;
7902 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7903 bp->phy_port = PORT_FIBRE;
7904 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7905 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7906 bp->flags |= BNX2_FLAG_NO_WOL;
7907 bp->wol = 0;
7908 }
7909 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7910 /* Don't do parallel detect on this board because of
7911 * some board problems. The link will not go down
7912 * if we do parallel detect.
7913 */
7914 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7915 pdev->subsystem_device == 0x310c)
7916 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7917 } else {
7918 bp->phy_addr = 2;
7919 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7920 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7921 }
7922 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7923 CHIP_NUM(bp) == CHIP_NUM_5708)
7924 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7925 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7926 (CHIP_REV(bp) == CHIP_REV_Ax ||
7927 CHIP_REV(bp) == CHIP_REV_Bx))
7928 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7929
7930 bnx2_init_fw_cap(bp);
7931
7932 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7933 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7934 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
7935 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7936 bp->flags |= BNX2_FLAG_NO_WOL;
7937 bp->wol = 0;
7938 }
7939
7940 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7941 bp->tx_quick_cons_trip_int =
7942 bp->tx_quick_cons_trip;
7943 bp->tx_ticks_int = bp->tx_ticks;
7944 bp->rx_quick_cons_trip_int =
7945 bp->rx_quick_cons_trip;
7946 bp->rx_ticks_int = bp->rx_ticks;
7947 bp->comp_prod_trip_int = bp->comp_prod_trip;
7948 bp->com_ticks_int = bp->com_ticks;
7949 bp->cmd_ticks_int = bp->cmd_ticks;
7950 }
7951
7952 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7953 *
7954 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7955 * with byte enables disabled on the unused 32-bit word. This is legal
7956 * but causes problems on the AMD 8132 which will eventually stop
7957 * responding after a while.
7958 *
7959 * AMD believes this incompatibility is unique to the 5706, and
7960 * prefers to locally disable MSI rather than globally disabling it.
7961 */
7962 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7963 struct pci_dev *amd_8132 = NULL;
7964
7965 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7966 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7967 amd_8132))) {
7968
7969 if (amd_8132->revision >= 0x10 &&
7970 amd_8132->revision <= 0x13) {
7971 disable_msi = 1;
7972 pci_dev_put(amd_8132);
7973 break;
7974 }
7975 }
7976 }
7977
7978 bnx2_set_default_link(bp);
7979 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7980
7981 init_timer(&bp->timer);
7982 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7983 bp->timer.data = (unsigned long) bp;
7984 bp->timer.function = bnx2_timer;
7985
7986 return 0;
7987
7988 err_out_unmap:
7989 if (bp->regview) {
7990 iounmap(bp->regview);
7991 bp->regview = NULL;
7992 }
7993
7994 err_out_release:
7995 pci_release_regions(pdev);
7996
7997 err_out_disable:
7998 pci_disable_device(pdev);
7999 pci_set_drvdata(pdev, NULL);
8000
8001 err_out:
8002 return rc;
8003 }
8004
8005 static char * __devinit
8006 bnx2_bus_string(struct bnx2 *bp, char *str)
8007 {
8008 char *s = str;
8009
8010 if (bp->flags & BNX2_FLAG_PCIE) {
8011 s += sprintf(s, "PCI Express");
8012 } else {
8013 s += sprintf(s, "PCI");
8014 if (bp->flags & BNX2_FLAG_PCIX)
8015 s += sprintf(s, "-X");
8016 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8017 s += sprintf(s, " 32-bit");
8018 else
8019 s += sprintf(s, " 64-bit");
8020 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8021 }
8022 return str;
8023 }
8024
8025 static void
8026 bnx2_del_napi(struct bnx2 *bp)
8027 {
8028 int i;
8029
8030 for (i = 0; i < bp->irq_nvecs; i++)
8031 netif_napi_del(&bp->bnx2_napi[i].napi);
8032 }
8033
8034 static void
8035 bnx2_init_napi(struct bnx2 *bp)
8036 {
8037 int i;
8038
8039 for (i = 0; i < bp->irq_nvecs; i++) {
8040 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8041 int (*poll)(struct napi_struct *, int);
8042
8043 if (i == 0)
8044 poll = bnx2_poll;
8045 else
8046 poll = bnx2_poll_msix;
8047
8048 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8049 bnapi->bp = bp;
8050 }
8051 }
8052
8053 static const struct net_device_ops bnx2_netdev_ops = {
8054 .ndo_open = bnx2_open,
8055 .ndo_start_xmit = bnx2_start_xmit,
8056 .ndo_stop = bnx2_close,
8057 .ndo_get_stats = bnx2_get_stats,
8058 .ndo_set_rx_mode = bnx2_set_rx_mode,
8059 .ndo_do_ioctl = bnx2_ioctl,
8060 .ndo_validate_addr = eth_validate_addr,
8061 .ndo_set_mac_address = bnx2_change_mac_addr,
8062 .ndo_change_mtu = bnx2_change_mtu,
8063 .ndo_tx_timeout = bnx2_tx_timeout,
8064 #ifdef BCM_VLAN
8065 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8066 #endif
8067 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
8068 .ndo_poll_controller = poll_bnx2,
8069 #endif
8070 };
8071
8072 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8073 {
8074 #ifdef BCM_VLAN
8075 dev->vlan_features |= flags;
8076 #endif
8077 }
8078
8079 static int __devinit
8080 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8081 {
8082 static int version_printed = 0;
8083 struct net_device *dev = NULL;
8084 struct bnx2 *bp;
8085 int rc;
8086 char str[40];
8087
8088 if (version_printed++ == 0)
8089 printk(KERN_INFO "%s", version);
8090
8091 /* dev zeroed in init_etherdev */
8092 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8093
8094 if (!dev)
8095 return -ENOMEM;
8096
8097 rc = bnx2_init_board(pdev, dev);
8098 if (rc < 0) {
8099 free_netdev(dev);
8100 return rc;
8101 }
8102
8103 dev->netdev_ops = &bnx2_netdev_ops;
8104 dev->watchdog_timeo = TX_TIMEOUT;
8105 dev->ethtool_ops = &bnx2_ethtool_ops;
8106
8107 bp = netdev_priv(dev);
8108
8109 pci_set_drvdata(pdev, dev);
8110
8111 rc = bnx2_request_firmware(bp);
8112 if (rc)
8113 goto error;
8114
8115 memcpy(dev->dev_addr, bp->mac_addr, 6);
8116 memcpy(dev->perm_addr, bp->mac_addr, 6);
8117
8118 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
8119 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8120 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8121 dev->features |= NETIF_F_IPV6_CSUM;
8122 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8123 }
8124 #ifdef BCM_VLAN
8125 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8126 #endif
8127 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8128 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8129 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8130 dev->features |= NETIF_F_TSO6;
8131 vlan_features_add(dev, NETIF_F_TSO6);
8132 }
8133 if ((rc = register_netdev(dev))) {
8134 dev_err(&pdev->dev, "Cannot register net device\n");
8135 goto error;
8136 }
8137
8138 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
8139 "IRQ %d, node addr %pM\n",
8140 dev->name,
8141 board_info[ent->driver_data].name,
8142 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8143 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8144 bnx2_bus_string(bp, str),
8145 dev->base_addr,
8146 bp->pdev->irq, dev->dev_addr);
8147
8148 return 0;
8149
8150 error:
8151 if (bp->mips_firmware)
8152 release_firmware(bp->mips_firmware);
8153 if (bp->rv2p_firmware)
8154 release_firmware(bp->rv2p_firmware);
8155
8156 if (bp->regview)
8157 iounmap(bp->regview);
8158 pci_release_regions(pdev);
8159 pci_disable_device(pdev);
8160 pci_set_drvdata(pdev, NULL);
8161 free_netdev(dev);
8162 return rc;
8163 }
8164
8165 static void __devexit
8166 bnx2_remove_one(struct pci_dev *pdev)
8167 {
8168 struct net_device *dev = pci_get_drvdata(pdev);
8169 struct bnx2 *bp = netdev_priv(dev);
8170
8171 flush_scheduled_work();
8172
8173 unregister_netdev(dev);
8174
8175 if (bp->mips_firmware)
8176 release_firmware(bp->mips_firmware);
8177 if (bp->rv2p_firmware)
8178 release_firmware(bp->rv2p_firmware);
8179
8180 if (bp->regview)
8181 iounmap(bp->regview);
8182
8183 free_netdev(dev);
8184 pci_release_regions(pdev);
8185 pci_disable_device(pdev);
8186 pci_set_drvdata(pdev, NULL);
8187 }
8188
8189 static int
8190 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8191 {
8192 struct net_device *dev = pci_get_drvdata(pdev);
8193 struct bnx2 *bp = netdev_priv(dev);
8194
8195 /* PCI register 4 needs to be saved whether netif_running() or not.
8196 * MSI address and data need to be saved if using MSI and
8197 * netif_running().
8198 */
8199 pci_save_state(pdev);
8200 if (!netif_running(dev))
8201 return 0;
8202
8203 flush_scheduled_work();
8204 bnx2_netif_stop(bp);
8205 netif_device_detach(dev);
8206 del_timer_sync(&bp->timer);
8207 bnx2_shutdown_chip(bp);
8208 bnx2_free_skbs(bp);
8209 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8210 return 0;
8211 }
8212
8213 static int
8214 bnx2_resume(struct pci_dev *pdev)
8215 {
8216 struct net_device *dev = pci_get_drvdata(pdev);
8217 struct bnx2 *bp = netdev_priv(dev);
8218
8219 pci_restore_state(pdev);
8220 if (!netif_running(dev))
8221 return 0;
8222
8223 bnx2_set_power_state(bp, PCI_D0);
8224 netif_device_attach(dev);
8225 bnx2_init_nic(bp, 1);
8226 bnx2_netif_start(bp);
8227 return 0;
8228 }
8229
8230 /**
8231 * bnx2_io_error_detected - called when PCI error is detected
8232 * @pdev: Pointer to PCI device
8233 * @state: The current pci connection state
8234 *
8235 * This function is called after a PCI bus error affecting
8236 * this device has been detected.
8237 */
8238 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8239 pci_channel_state_t state)
8240 {
8241 struct net_device *dev = pci_get_drvdata(pdev);
8242 struct bnx2 *bp = netdev_priv(dev);
8243
8244 rtnl_lock();
8245 netif_device_detach(dev);
8246
8247 if (state == pci_channel_io_perm_failure) {
8248 rtnl_unlock();
8249 return PCI_ERS_RESULT_DISCONNECT;
8250 }
8251
8252 if (netif_running(dev)) {
8253 bnx2_netif_stop(bp);
8254 del_timer_sync(&bp->timer);
8255 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8256 }
8257
8258 pci_disable_device(pdev);
8259 rtnl_unlock();
8260
8261 /* Request a slot slot reset. */
8262 return PCI_ERS_RESULT_NEED_RESET;
8263 }
8264
8265 /**
8266 * bnx2_io_slot_reset - called after the pci bus has been reset.
8267 * @pdev: Pointer to PCI device
8268 *
8269 * Restart the card from scratch, as if from a cold-boot.
8270 */
8271 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8272 {
8273 struct net_device *dev = pci_get_drvdata(pdev);
8274 struct bnx2 *bp = netdev_priv(dev);
8275
8276 rtnl_lock();
8277 if (pci_enable_device(pdev)) {
8278 dev_err(&pdev->dev,
8279 "Cannot re-enable PCI device after reset.\n");
8280 rtnl_unlock();
8281 return PCI_ERS_RESULT_DISCONNECT;
8282 }
8283 pci_set_master(pdev);
8284 pci_restore_state(pdev);
8285
8286 if (netif_running(dev)) {
8287 bnx2_set_power_state(bp, PCI_D0);
8288 bnx2_init_nic(bp, 1);
8289 }
8290
8291 rtnl_unlock();
8292 return PCI_ERS_RESULT_RECOVERED;
8293 }
8294
8295 /**
8296 * bnx2_io_resume - called when traffic can start flowing again.
8297 * @pdev: Pointer to PCI device
8298 *
8299 * This callback is called when the error recovery driver tells us that
8300 * its OK to resume normal operation.
8301 */
8302 static void bnx2_io_resume(struct pci_dev *pdev)
8303 {
8304 struct net_device *dev = pci_get_drvdata(pdev);
8305 struct bnx2 *bp = netdev_priv(dev);
8306
8307 rtnl_lock();
8308 if (netif_running(dev))
8309 bnx2_netif_start(bp);
8310
8311 netif_device_attach(dev);
8312 rtnl_unlock();
8313 }
8314
8315 static struct pci_error_handlers bnx2_err_handler = {
8316 .error_detected = bnx2_io_error_detected,
8317 .slot_reset = bnx2_io_slot_reset,
8318 .resume = bnx2_io_resume,
8319 };
8320
8321 static struct pci_driver bnx2_pci_driver = {
8322 .name = DRV_MODULE_NAME,
8323 .id_table = bnx2_pci_tbl,
8324 .probe = bnx2_init_one,
8325 .remove = __devexit_p(bnx2_remove_one),
8326 .suspend = bnx2_suspend,
8327 .resume = bnx2_resume,
8328 .err_handler = &bnx2_err_handler,
8329 };
8330
8331 static int __init bnx2_init(void)
8332 {
8333 return pci_register_driver(&bnx2_pci_driver);
8334 }
8335
8336 static void __exit bnx2_cleanup(void)
8337 {
8338 pci_unregister_driver(&bnx2_pci_driver);
8339 }
8340
8341 module_init(bnx2_init);
8342 module_exit(bnx2_cleanup);
8343
8344
8345
Linux MOXA ART SoC ARM port