drivers/net/igb/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_HW_H_
  29 #define _E1000_HW_H_
  30
  31 #include <linux/types.h>
  32 #include <linux/delay.h>
  33 #include <linux/io.h>
  34
  35 #include "e1000_regs.h"
  36 #include "e1000_defines.h"
  37
  38 struct e1000_hw;
  39
  40 #define E1000_DEV_ID_82576                    0x10C9
  41 #define E1000_DEV_ID_82576_FIBER              0x10E6
  42 #define E1000_DEV_ID_82576_SERDES             0x10E7
  43 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
  44 #define E1000_DEV_ID_82576_NS                 0x150A
  45 #define E1000_DEV_ID_82576_NS_SERDES          0x1518
  46 #define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
  47 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
  48 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
  49 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
  50
  51 #define E1000_REVISION_2 2
  52 #define E1000_REVISION_4 4
  53
  54 #define E1000_FUNC_1     1
  55
  56 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
  57
  58 enum e1000_mac_type {
  59         e1000_undefined = 0,
  60         e1000_82575,
  61         e1000_82576,
  62         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  63 };
  64
  65 enum e1000_media_type {
  66         e1000_media_type_unknown = 0,
  67         e1000_media_type_copper = 1,
  68         e1000_media_type_internal_serdes = 2,
  69         e1000_num_media_types
  70 };
  71
  72 enum e1000_nvm_type {
  73         e1000_nvm_unknown = 0,
  74         e1000_nvm_none,
  75         e1000_nvm_eeprom_spi,
  76         e1000_nvm_eeprom_microwire,
  77         e1000_nvm_flash_hw,
  78         e1000_nvm_flash_sw
  79 };
  80
  81 enum e1000_nvm_override {
  82         e1000_nvm_override_none = 0,
  83         e1000_nvm_override_spi_small,
  84         e1000_nvm_override_spi_large,
  85         e1000_nvm_override_microwire_small,
  86         e1000_nvm_override_microwire_large
  87 };
  88
  89 enum e1000_phy_type {
  90         e1000_phy_unknown = 0,
  91         e1000_phy_none,
  92         e1000_phy_m88,
  93         e1000_phy_igp,
  94         e1000_phy_igp_2,
  95         e1000_phy_gg82563,
  96         e1000_phy_igp_3,
  97         e1000_phy_ife,
  98 };
  99
 100 enum e1000_bus_type {
 101         e1000_bus_type_unknown = 0,
 102         e1000_bus_type_pci,
 103         e1000_bus_type_pcix,
 104         e1000_bus_type_pci_express,
 105         e1000_bus_type_reserved
 106 };
 107
 108 enum e1000_bus_speed {
 109         e1000_bus_speed_unknown = 0,
 110         e1000_bus_speed_33,
 111         e1000_bus_speed_66,
 112         e1000_bus_speed_100,
 113         e1000_bus_speed_120,
 114         e1000_bus_speed_133,
 115         e1000_bus_speed_2500,
 116         e1000_bus_speed_5000,
 117         e1000_bus_speed_reserved
 118 };
 119
 120 enum e1000_bus_width {
 121         e1000_bus_width_unknown = 0,
 122         e1000_bus_width_pcie_x1,
 123         e1000_bus_width_pcie_x2,
 124         e1000_bus_width_pcie_x4 = 4,
 125         e1000_bus_width_pcie_x8 = 8,
 126         e1000_bus_width_32,
 127         e1000_bus_width_64,
 128         e1000_bus_width_reserved
 129 };
 130
 131 enum e1000_1000t_rx_status {
 132         e1000_1000t_rx_status_not_ok = 0,
 133         e1000_1000t_rx_status_ok,
 134         e1000_1000t_rx_status_undefined = 0xFF
 135 };
 136
 137 enum e1000_rev_polarity {
 138         e1000_rev_polarity_normal = 0,
 139         e1000_rev_polarity_reversed,
 140         e1000_rev_polarity_undefined = 0xFF
 141 };
 142
 143 enum e1000_fc_mode {
 144         e1000_fc_none = 0,
 145         e1000_fc_rx_pause,
 146         e1000_fc_tx_pause,
 147         e1000_fc_full,
 148         e1000_fc_default = 0xFF
 149 };
 150
 151 /* Statistics counters collected by the MAC */
 152 struct e1000_hw_stats {
 153         u64 crcerrs;
 154         u64 algnerrc;
 155         u64 symerrs;
 156         u64 rxerrc;
 157         u64 mpc;
 158         u64 scc;
 159         u64 ecol;
 160         u64 mcc;
 161         u64 latecol;
 162         u64 colc;
 163         u64 dc;
 164         u64 tncrs;
 165         u64 sec;
 166         u64 cexterr;
 167         u64 rlec;
 168         u64 xonrxc;
 169         u64 xontxc;
 170         u64 xoffrxc;
 171         u64 xofftxc;
 172         u64 fcruc;
 173         u64 prc64;
 174         u64 prc127;
 175         u64 prc255;
 176         u64 prc511;
 177         u64 prc1023;
 178         u64 prc1522;
 179         u64 gprc;
 180         u64 bprc;
 181         u64 mprc;
 182         u64 gptc;
 183         u64 gorc;
 184         u64 gotc;
 185         u64 rnbc;
 186         u64 ruc;
 187         u64 rfc;
 188         u64 roc;
 189         u64 rjc;
 190         u64 mgprc;
 191         u64 mgpdc;
 192         u64 mgptc;
 193         u64 tor;
 194         u64 tot;
 195         u64 tpr;
 196         u64 tpt;
 197         u64 ptc64;
 198         u64 ptc127;
 199         u64 ptc255;
 200         u64 ptc511;
 201         u64 ptc1023;
 202         u64 ptc1522;
 203         u64 mptc;
 204         u64 bptc;
 205         u64 tsctc;
 206         u64 tsctfc;
 207         u64 iac;
 208         u64 icrxptc;
 209         u64 icrxatc;
 210         u64 ictxptc;
 211         u64 ictxatc;
 212         u64 ictxqec;
 213         u64 ictxqmtc;
 214         u64 icrxdmtc;
 215         u64 icrxoc;
 216         u64 cbtmpc;
 217         u64 htdpmc;
 218         u64 cbrdpc;
 219         u64 cbrmpc;
 220         u64 rpthc;
 221         u64 hgptc;
 222         u64 htcbdpc;
 223         u64 hgorc;
 224         u64 hgotc;
 225         u64 lenerrs;
 226         u64 scvpc;
 227         u64 hrmpc;
 228         u64 doosync;
 229 };
 230
 231 struct e1000_phy_stats {
 232         u32 idle_errors;
 233         u32 receive_errors;
 234 };
 235
 236 struct e1000_host_mng_dhcp_cookie {
 237         u32 signature;
 238         u8  status;
 239         u8  reserved0;
 240         u16 vlan_id;
 241         u32 reserved1;
 242         u16 reserved2;
 243         u8  reserved3;
 244         u8  checksum;
 245 };
 246
 247 /* Host Interface "Rev 1" */
 248 struct e1000_host_command_header {
 249         u8 command_id;
 250         u8 command_length;
 251         u8 command_options;
 252         u8 checksum;
 253 };
 254
 255 #define E1000_HI_MAX_DATA_LENGTH     252
 256 struct e1000_host_command_info {
 257         struct e1000_host_command_header command_header;
 258         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 259 };
 260
 261 /* Host Interface "Rev 2" */
 262 struct e1000_host_mng_command_header {
 263         u8  command_id;
 264         u8  checksum;
 265         u16 reserved1;
 266         u16 reserved2;
 267         u16 command_length;
 268 };
 269
 270 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 271 struct e1000_host_mng_command_info {
 272         struct e1000_host_mng_command_header command_header;
 273         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 274 };
 275
 276 #include "e1000_mac.h"
 277 #include "e1000_phy.h"
 278 #include "e1000_nvm.h"
 279 #include "e1000_mbx.h"
 280
 281 struct e1000_mac_operations {
 282         s32  (*check_for_link)(struct e1000_hw *);
 283         s32  (*reset_hw)(struct e1000_hw *);
 284         s32  (*init_hw)(struct e1000_hw *);
 285         bool (*check_mng_mode)(struct e1000_hw *);
 286         s32  (*setup_physical_interface)(struct e1000_hw *);
 287         void (*rar_set)(struct e1000_hw *, u8 *, u32);
 288         s32  (*read_mac_addr)(struct e1000_hw *);
 289         s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
 290 };
 291
 292 struct e1000_phy_operations {
 293         s32  (*acquire)(struct e1000_hw *);
 294         s32  (*check_reset_block)(struct e1000_hw *);
 295         s32  (*force_speed_duplex)(struct e1000_hw *);
 296         s32  (*get_cfg_done)(struct e1000_hw *hw);
 297         s32  (*get_cable_length)(struct e1000_hw *);
 298         s32  (*get_phy_info)(struct e1000_hw *);
 299         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 300         void (*release)(struct e1000_hw *);
 301         s32  (*reset)(struct e1000_hw *);
 302         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 303         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 304         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 305 };
 306
 307 struct e1000_nvm_operations {
 308         s32  (*acquire)(struct e1000_hw *);
 309         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 310         void (*release)(struct e1000_hw *);
 311         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 312 };
 313
 314 struct e1000_info {
 315         s32 (*get_invariants)(struct e1000_hw *);
 316         struct e1000_mac_operations *mac_ops;
 317         struct e1000_phy_operations *phy_ops;
 318         struct e1000_nvm_operations *nvm_ops;
 319 };
 320
 321 extern const struct e1000_info e1000_82575_info;
 322
 323 struct e1000_mac_info {
 324         struct e1000_mac_operations ops;
 325
 326         u8 addr[6];
 327         u8 perm_addr[6];
 328
 329         enum e1000_mac_type type;
 330
 331         u32 collision_delta;
 332         u32 ledctl_default;
 333         u32 ledctl_mode1;
 334         u32 ledctl_mode2;
 335         u32 mc_filter_type;
 336         u32 tx_packet_delta;
 337         u32 txcw;
 338
 339         u16 current_ifs_val;
 340         u16 ifs_max_val;
 341         u16 ifs_min_val;
 342         u16 ifs_ratio;
 343         u16 ifs_step_size;
 344         u16 mta_reg_count;
 345
 346         /* Maximum size of the MTA register table in all supported adapters */
 347         #define MAX_MTA_REG 128
 348         u32 mta_shadow[MAX_MTA_REG];
 349         u16 rar_entry_count;
 350
 351         u8  forced_speed_duplex;
 352
 353         bool adaptive_ifs;
 354         bool arc_subsystem_valid;
 355         bool asf_firmware_present;
 356         bool autoneg;
 357         bool autoneg_failed;
 358         bool disable_hw_init_bits;
 359         bool get_link_status;
 360         bool ifs_params_forced;
 361         bool in_ifs_mode;
 362         bool report_tx_early;
 363         bool serdes_has_link;
 364         bool tx_pkt_filtering;
 365 };
 366
 367 struct e1000_phy_info {
 368         struct e1000_phy_operations ops;
 369
 370         enum e1000_phy_type type;
 371
 372         enum e1000_1000t_rx_status local_rx;
 373         enum e1000_1000t_rx_status remote_rx;
 374         enum e1000_ms_type ms_type;
 375         enum e1000_ms_type original_ms_type;
 376         enum e1000_rev_polarity cable_polarity;
 377         enum e1000_smart_speed smart_speed;
 378
 379         u32 addr;
 380         u32 id;
 381         u32 reset_delay_us; /* in usec */
 382         u32 revision;
 383
 384         enum e1000_media_type media_type;
 385
 386         u16 autoneg_advertised;
 387         u16 autoneg_mask;
 388         u16 cable_length;
 389         u16 max_cable_length;
 390         u16 min_cable_length;
 391
 392         u8 mdix;
 393
 394         bool disable_polarity_correction;
 395         bool is_mdix;
 396         bool polarity_correction;
 397         bool reset_disable;
 398         bool speed_downgraded;
 399         bool autoneg_wait_to_complete;
 400 };
 401
 402 struct e1000_nvm_info {
 403         struct e1000_nvm_operations ops;
 404
 405         enum e1000_nvm_type type;
 406         enum e1000_nvm_override override;
 407
 408         u32 flash_bank_size;
 409         u32 flash_base_addr;
 410
 411         u16 word_size;
 412         u16 delay_usec;
 413         u16 address_bits;
 414         u16 opcode_bits;
 415         u16 page_size;
 416 };
 417
 418 struct e1000_bus_info {
 419         enum e1000_bus_type type;
 420         enum e1000_bus_speed speed;
 421         enum e1000_bus_width width;
 422
 423         u32 snoop;
 424
 425         u16 func;
 426         u16 pci_cmd_word;
 427 };
 428
 429 struct e1000_fc_info {
 430         u32 high_water;     /* Flow control high-water mark */
 431         u32 low_water;      /* Flow control low-water mark */
 432         u16 pause_time;     /* Flow control pause timer */
 433         bool send_xon;      /* Flow control send XON */
 434         bool strict_ieee;   /* Strict IEEE mode */
 435         enum e1000_fc_mode current_mode; /* Type of flow control */
 436         enum e1000_fc_mode requested_mode;
 437 };
 438
 439 struct e1000_mbx_operations {
 440         s32 (*init_params)(struct e1000_hw *hw);
 441         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 442         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 443         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 444         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 445         s32 (*check_for_msg)(struct e1000_hw *, u16);
 446         s32 (*check_for_ack)(struct e1000_hw *, u16);
 447         s32 (*check_for_rst)(struct e1000_hw *, u16);
 448 };
 449
 450 struct e1000_mbx_stats {
 451         u32 msgs_tx;
 452         u32 msgs_rx;
 453
 454         u32 acks;
 455         u32 reqs;
 456         u32 rsts;
 457 };
 458
 459 struct e1000_mbx_info {
 460         struct e1000_mbx_operations ops;
 461         struct e1000_mbx_stats stats;
 462         u32 timeout;
 463         u32 usec_delay;
 464         u16 size;
 465 };
 466
 467 struct e1000_dev_spec_82575 {
 468         bool sgmii_active;
 469 };
 470
 471 struct e1000_hw {
 472         void *back;
 473
 474         u8 __iomem *hw_addr;
 475         u8 __iomem *flash_address;
 476         unsigned long io_base;
 477
 478         struct e1000_mac_info  mac;
 479         struct e1000_fc_info   fc;
 480         struct e1000_phy_info  phy;
 481         struct e1000_nvm_info  nvm;
 482         struct e1000_bus_info  bus;
 483         struct e1000_mbx_info mbx;
 484         struct e1000_host_mng_dhcp_cookie mng_cookie;
 485
 486         union {
 487                 struct e1000_dev_spec_82575     _82575;
 488         } dev_spec;
 489
 490         u16 device_id;
 491         u16 subsystem_vendor_id;
 492         u16 subsystem_device_id;
 493         u16 vendor_id;
 494
 495         u8  revision_id;
 496 };
 497
 498 #ifdef DEBUG
 499 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 500 #define hw_dbg(format, arg...) \
 501         printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
 502 #else
 503 #define hw_dbg(format, arg...)
 504 #endif
 505 #endif
 506 /* These functions must be implemented by drivers */
 507 s32  igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 508 s32  igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);