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init from v2.6.32.60
[mach-moxart.git] / drivers / net / igb / igb_main.c
blob40dc84c8025999c6673cd273d113086461aef910
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
47 #ifdef CONFIG_IGB_DCA
48 #include <linux/dca.h>
49 #endif
50 #include "igb.h"
51
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name[] = "igb";
54 char igb_driver_version[] = DRV_VERSION;
55 static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
58
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61 };
62
63 static struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
74 /* required last entry */
75 {0, }
76 };
77
78 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
79
80 void igb_reset(struct igb_adapter *);
81 static int igb_setup_all_tx_resources(struct igb_adapter *);
82 static int igb_setup_all_rx_resources(struct igb_adapter *);
83 static void igb_free_all_tx_resources(struct igb_adapter *);
84 static void igb_free_all_rx_resources(struct igb_adapter *);
85 void igb_update_stats(struct igb_adapter *);
86 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
87 static void __devexit igb_remove(struct pci_dev *pdev);
88 static int igb_sw_init(struct igb_adapter *);
89 static int igb_open(struct net_device *);
90 static int igb_close(struct net_device *);
91 static void igb_configure_tx(struct igb_adapter *);
92 static void igb_configure_rx(struct igb_adapter *);
93 static void igb_setup_rctl(struct igb_adapter *);
94 static void igb_clean_all_tx_rings(struct igb_adapter *);
95 static void igb_clean_all_rx_rings(struct igb_adapter *);
96 static void igb_clean_tx_ring(struct igb_ring *);
97 static void igb_clean_rx_ring(struct igb_ring *);
98 static void igb_set_rx_mode(struct net_device *);
99 static void igb_update_phy_info(unsigned long);
100 static void igb_watchdog(unsigned long);
101 static void igb_watchdog_task(struct work_struct *);
102 static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
103 struct net_device *,
104 struct igb_ring *);
105 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
106 struct net_device *);
107 static struct net_device_stats *igb_get_stats(struct net_device *);
108 static int igb_change_mtu(struct net_device *, int);
109 static int igb_set_mac(struct net_device *, void *);
110 static irqreturn_t igb_intr(int irq, void *);
111 static irqreturn_t igb_intr_msi(int irq, void *);
112 static irqreturn_t igb_msix_other(int irq, void *);
113 static irqreturn_t igb_msix_rx(int irq, void *);
114 static irqreturn_t igb_msix_tx(int irq, void *);
115 #ifdef CONFIG_IGB_DCA
116 static void igb_update_rx_dca(struct igb_ring *);
117 static void igb_update_tx_dca(struct igb_ring *);
118 static void igb_setup_dca(struct igb_adapter *);
119 #endif /* CONFIG_IGB_DCA */
120 static bool igb_clean_tx_irq(struct igb_ring *);
121 static int igb_poll(struct napi_struct *, int);
122 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
123 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
124 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
125 static void igb_tx_timeout(struct net_device *);
126 static void igb_reset_task(struct work_struct *);
127 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
128 static void igb_vlan_rx_add_vid(struct net_device *, u16);
129 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
130 static void igb_restore_vlan(struct igb_adapter *);
131 static void igb_ping_all_vfs(struct igb_adapter *);
132 static void igb_msg_task(struct igb_adapter *);
133 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
134 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
135 static void igb_vmm_control(struct igb_adapter *);
136 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
137 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
138
139 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
140 {
141 u32 reg_data;
142
143 reg_data = rd32(E1000_VMOLR(vfn));
144 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
145 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
146 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
147 E1000_VMOLR_AUPE | /* Accept untagged packets */
148 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
149 wr32(E1000_VMOLR(vfn), reg_data);
150 }
151
152 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
153 int vfn)
154 {
155 struct e1000_hw *hw = &adapter->hw;
156 u32 vmolr;
157
158 /* if it isn't the PF check to see if VFs are enabled and
159 * increase the size to support vlan tags */
160 if (vfn < adapter->vfs_allocated_count &&
161 adapter->vf_data[vfn].vlans_enabled)
162 size += VLAN_TAG_SIZE;
163
164 vmolr = rd32(E1000_VMOLR(vfn));
165 vmolr &= ~E1000_VMOLR_RLPML_MASK;
166 vmolr |= size | E1000_VMOLR_LPE;
167 wr32(E1000_VMOLR(vfn), vmolr);
168
169 return 0;
170 }
171
172 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
173 {
174 u32 reg_data;
175
176 reg_data = rd32(E1000_RAH(entry));
177 reg_data &= ~E1000_RAH_POOL_MASK;
178 reg_data |= E1000_RAH_POOL_1 << pool;;
179 wr32(E1000_RAH(entry), reg_data);
180 }
181
182 #ifdef CONFIG_PM
183 static int igb_suspend(struct pci_dev *, pm_message_t);
184 static int igb_resume(struct pci_dev *);
185 #endif
186 static void igb_shutdown(struct pci_dev *);
187 #ifdef CONFIG_IGB_DCA
188 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
189 static struct notifier_block dca_notifier = {
190 .notifier_call = igb_notify_dca,
191 .next = NULL,
192 .priority = 0
193 };
194 #endif
195 #ifdef CONFIG_NET_POLL_CONTROLLER
196 /* for netdump / net console */
197 static void igb_netpoll(struct net_device *);
198 #endif
199 #ifdef CONFIG_PCI_IOV
200 static unsigned int max_vfs = 0;
201 module_param(max_vfs, uint, 0);
202 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
203 "per physical function");
204 #endif /* CONFIG_PCI_IOV */
205
206 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
207 pci_channel_state_t);
208 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
209 static void igb_io_resume(struct pci_dev *);
210
211 static struct pci_error_handlers igb_err_handler = {
212 .error_detected = igb_io_error_detected,
213 .slot_reset = igb_io_slot_reset,
214 .resume = igb_io_resume,
215 };
216
217
218 static struct pci_driver igb_driver = {
219 .name = igb_driver_name,
220 .id_table = igb_pci_tbl,
221 .probe = igb_probe,
222 .remove = __devexit_p(igb_remove),
223 #ifdef CONFIG_PM
224 /* Power Managment Hooks */
225 .suspend = igb_suspend,
226 .resume = igb_resume,
227 #endif
228 .shutdown = igb_shutdown,
229 .err_handler = &igb_err_handler
230 };
231
232 static int global_quad_port_a; /* global quad port a indication */
233
234 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
235 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
236 MODULE_LICENSE("GPL");
237 MODULE_VERSION(DRV_VERSION);
238
239 /**
240 * Scale the NIC clock cycle by a large factor so that
241 * relatively small clock corrections can be added or
242 * substracted at each clock tick. The drawbacks of a
243 * large factor are a) that the clock register overflows
244 * more quickly (not such a big deal) and b) that the
245 * increment per tick has to fit into 24 bits.
246 *
247 * Note that
248 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
249 * IGB_TSYNC_SCALE
250 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
251 *
252 * The base scale factor is intentionally a power of two
253 * so that the division in %struct timecounter can be done with
254 * a shift.
255 */
256 #define IGB_TSYNC_SHIFT (19)
257 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
258
259 /**
260 * The duration of one clock cycle of the NIC.
261 *
262 * @todo This hard-coded value is part of the specification and might change
263 * in future hardware revisions. Add revision check.
264 */
265 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
266
267 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
268 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
269 #endif
270
271 /**
272 * igb_read_clock - read raw cycle counter (to be used by time counter)
273 */
274 static cycle_t igb_read_clock(const struct cyclecounter *tc)
275 {
276 struct igb_adapter *adapter =
277 container_of(tc, struct igb_adapter, cycles);
278 struct e1000_hw *hw = &adapter->hw;
279 u64 stamp;
280
281 stamp = rd32(E1000_SYSTIML);
282 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
283
284 return stamp;
285 }
286
287 #ifdef DEBUG
288 /**
289 * igb_get_hw_dev_name - return device name string
290 * used by hardware layer to print debugging information
291 **/
292 char *igb_get_hw_dev_name(struct e1000_hw *hw)
293 {
294 struct igb_adapter *adapter = hw->back;
295 return adapter->netdev->name;
296 }
297
298 /**
299 * igb_get_time_str - format current NIC and system time as string
300 */
301 static char *igb_get_time_str(struct igb_adapter *adapter,
302 char buffer[160])
303 {
304 cycle_t hw = adapter->cycles.read(&adapter->cycles);
305 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
306 struct timespec sys;
307 struct timespec delta;
308 getnstimeofday(&sys);
309
310 delta = timespec_sub(nic, sys);
311
312 sprintf(buffer,
313 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
314 hw,
315 (long)nic.tv_sec, nic.tv_nsec,
316 (long)sys.tv_sec, sys.tv_nsec,
317 (long)delta.tv_sec, delta.tv_nsec);
318
319 return buffer;
320 }
321 #endif
322
323 /**
324 * igb_desc_unused - calculate if we have unused descriptors
325 **/
326 static int igb_desc_unused(struct igb_ring *ring)
327 {
328 if (ring->next_to_clean > ring->next_to_use)
329 return ring->next_to_clean - ring->next_to_use - 1;
330
331 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
332 }
333
334 /**
335 * igb_init_module - Driver Registration Routine
336 *
337 * igb_init_module is the first routine called when the driver is
338 * loaded. All it does is register with the PCI subsystem.
339 **/
340 static int __init igb_init_module(void)
341 {
342 int ret;
343 printk(KERN_INFO "%s - version %s\n",
344 igb_driver_string, igb_driver_version);
345
346 printk(KERN_INFO "%s\n", igb_copyright);
347
348 global_quad_port_a = 0;
349
350 #ifdef CONFIG_IGB_DCA
351 dca_register_notify(&dca_notifier);
352 #endif
353
354 ret = pci_register_driver(&igb_driver);
355 return ret;
356 }
357
358 module_init(igb_init_module);
359
360 /**
361 * igb_exit_module - Driver Exit Cleanup Routine
362 *
363 * igb_exit_module is called just before the driver is removed
364 * from memory.
365 **/
366 static void __exit igb_exit_module(void)
367 {
368 #ifdef CONFIG_IGB_DCA
369 dca_unregister_notify(&dca_notifier);
370 #endif
371 pci_unregister_driver(&igb_driver);
372 }
373
374 module_exit(igb_exit_module);
375
376 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
377 /**
378 * igb_cache_ring_register - Descriptor ring to register mapping
379 * @adapter: board private structure to initialize
380 *
381 * Once we know the feature-set enabled for the device, we'll cache
382 * the register offset the descriptor ring is assigned to.
383 **/
384 static void igb_cache_ring_register(struct igb_adapter *adapter)
385 {
386 int i;
387 unsigned int rbase_offset = adapter->vfs_allocated_count;
388
389 switch (adapter->hw.mac.type) {
390 case e1000_82576:
391 /* The queues are allocated for virtualization such that VF 0
392 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
393 * In order to avoid collision we start at the first free queue
394 * and continue consuming queues in the same sequence
395 */
396 for (i = 0; i < adapter->num_rx_queues; i++)
397 adapter->rx_ring[i].reg_idx = rbase_offset +
398 Q_IDX_82576(i);
399 for (i = 0; i < adapter->num_tx_queues; i++)
400 adapter->tx_ring[i].reg_idx = rbase_offset +
401 Q_IDX_82576(i);
402 break;
403 case e1000_82575:
404 default:
405 for (i = 0; i < adapter->num_rx_queues; i++)
406 adapter->rx_ring[i].reg_idx = i;
407 for (i = 0; i < adapter->num_tx_queues; i++)
408 adapter->tx_ring[i].reg_idx = i;
409 break;
410 }
411 }
412
413 /**
414 * igb_alloc_queues - Allocate memory for all rings
415 * @adapter: board private structure to initialize
416 *
417 * We allocate one ring per queue at run-time since we don't know the
418 * number of queues at compile-time.
419 **/
420 static int igb_alloc_queues(struct igb_adapter *adapter)
421 {
422 int i;
423
424 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
425 sizeof(struct igb_ring), GFP_KERNEL);
426 if (!adapter->tx_ring)
427 return -ENOMEM;
428
429 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
430 sizeof(struct igb_ring), GFP_KERNEL);
431 if (!adapter->rx_ring) {
432 kfree(adapter->tx_ring);
433 return -ENOMEM;
434 }
435
436 adapter->rx_ring->buddy = adapter->tx_ring;
437
438 for (i = 0; i < adapter->num_tx_queues; i++) {
439 struct igb_ring *ring = &(adapter->tx_ring[i]);
440 ring->count = adapter->tx_ring_count;
441 ring->adapter = adapter;
442 ring->queue_index = i;
443 }
444 for (i = 0; i < adapter->num_rx_queues; i++) {
445 struct igb_ring *ring = &(adapter->rx_ring[i]);
446 ring->count = adapter->rx_ring_count;
447 ring->adapter = adapter;
448 ring->queue_index = i;
449 ring->itr_register = E1000_ITR;
450
451 /* set a default napi handler for each rx_ring */
452 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
453 }
454
455 igb_cache_ring_register(adapter);
456 return 0;
457 }
458
459 static void igb_free_queues(struct igb_adapter *adapter)
460 {
461 int i;
462
463 for (i = 0; i < adapter->num_rx_queues; i++)
464 netif_napi_del(&adapter->rx_ring[i].napi);
465
466 adapter->num_rx_queues = 0;
467 adapter->num_tx_queues = 0;
468
469 kfree(adapter->tx_ring);
470 kfree(adapter->rx_ring);
471 }
472
473 #define IGB_N0_QUEUE -1
474 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
475 int tx_queue, int msix_vector)
476 {
477 u32 msixbm = 0;
478 struct e1000_hw *hw = &adapter->hw;
479 u32 ivar, index;
480
481 switch (hw->mac.type) {
482 case e1000_82575:
483 /* The 82575 assigns vectors using a bitmask, which matches the
484 bitmask for the EICR/EIMS/EIMC registers. To assign one
485 or more queues to a vector, we write the appropriate bits
486 into the MSIXBM register for that vector. */
487 if (rx_queue > IGB_N0_QUEUE) {
488 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
489 adapter->rx_ring[rx_queue].eims_value = msixbm;
490 }
491 if (tx_queue > IGB_N0_QUEUE) {
492 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
493 adapter->tx_ring[tx_queue].eims_value =
494 E1000_EICR_TX_QUEUE0 << tx_queue;
495 }
496 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
497 break;
498 case e1000_82576:
499 /* 82576 uses a table-based method for assigning vectors.
500 Each queue has a single entry in the table to which we write
501 a vector number along with a "valid" bit. Sadly, the layout
502 of the table is somewhat counterintuitive. */
503 if (rx_queue > IGB_N0_QUEUE) {
504 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
505 ivar = array_rd32(E1000_IVAR0, index);
506 if (rx_queue & 0x1) {
507 /* vector goes into third byte of register */
508 ivar = ivar & 0xFF00FFFF;
509 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
510 } else {
511 /* vector goes into low byte of register */
512 ivar = ivar & 0xFFFFFF00;
513 ivar |= msix_vector | E1000_IVAR_VALID;
514 }
515 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
516 array_wr32(E1000_IVAR0, index, ivar);
517 }
518 if (tx_queue > IGB_N0_QUEUE) {
519 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
520 ivar = array_rd32(E1000_IVAR0, index);
521 if (tx_queue & 0x1) {
522 /* vector goes into high byte of register */
523 ivar = ivar & 0x00FFFFFF;
524 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
525 } else {
526 /* vector goes into second byte of register */
527 ivar = ivar & 0xFFFF00FF;
528 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
529 }
530 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
531 array_wr32(E1000_IVAR0, index, ivar);
532 }
533 break;
534 default:
535 BUG();
536 break;
537 }
538 }
539
540 /**
541 * igb_configure_msix - Configure MSI-X hardware
542 *
543 * igb_configure_msix sets up the hardware to properly
544 * generate MSI-X interrupts.
545 **/
546 static void igb_configure_msix(struct igb_adapter *adapter)
547 {
548 u32 tmp;
549 int i, vector = 0;
550 struct e1000_hw *hw = &adapter->hw;
551
552 adapter->eims_enable_mask = 0;
553 if (hw->mac.type == e1000_82576)
554 /* Turn on MSI-X capability first, or our settings
555 * won't stick. And it will take days to debug. */
556 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
557 E1000_GPIE_PBA | E1000_GPIE_EIAME |
558 E1000_GPIE_NSICR);
559
560 for (i = 0; i < adapter->num_tx_queues; i++) {
561 struct igb_ring *tx_ring = &adapter->tx_ring[i];
562 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
563 adapter->eims_enable_mask |= tx_ring->eims_value;
564 if (tx_ring->itr_val)
565 writel(tx_ring->itr_val,
566 hw->hw_addr + tx_ring->itr_register);
567 else
568 writel(1, hw->hw_addr + tx_ring->itr_register);
569 }
570
571 for (i = 0; i < adapter->num_rx_queues; i++) {
572 struct igb_ring *rx_ring = &adapter->rx_ring[i];
573 rx_ring->buddy = NULL;
574 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
575 adapter->eims_enable_mask |= rx_ring->eims_value;
576 if (rx_ring->itr_val)
577 writel(rx_ring->itr_val,
578 hw->hw_addr + rx_ring->itr_register);
579 else
580 writel(1, hw->hw_addr + rx_ring->itr_register);
581 }
582
583
584 /* set vector for other causes, i.e. link changes */
585 switch (hw->mac.type) {
586 case e1000_82575:
587 array_wr32(E1000_MSIXBM(0), vector++,
588 E1000_EIMS_OTHER);
589
590 tmp = rd32(E1000_CTRL_EXT);
591 /* enable MSI-X PBA support*/
592 tmp |= E1000_CTRL_EXT_PBA_CLR;
593
594 /* Auto-Mask interrupts upon ICR read. */
595 tmp |= E1000_CTRL_EXT_EIAME;
596 tmp |= E1000_CTRL_EXT_IRCA;
597
598 wr32(E1000_CTRL_EXT, tmp);
599 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
600 adapter->eims_other = E1000_EIMS_OTHER;
601
602 break;
603
604 case e1000_82576:
605 tmp = (vector++ | E1000_IVAR_VALID) << 8;
606 wr32(E1000_IVAR_MISC, tmp);
607
608 adapter->eims_enable_mask = (1 << (vector)) - 1;
609 adapter->eims_other = 1 << (vector - 1);
610 break;
611 default:
612 /* do nothing, since nothing else supports MSI-X */
613 break;
614 } /* switch (hw->mac.type) */
615 wrfl();
616 }
617
618 /**
619 * igb_request_msix - Initialize MSI-X interrupts
620 *
621 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
622 * kernel.
623 **/
624 static int igb_request_msix(struct igb_adapter *adapter)
625 {
626 struct net_device *netdev = adapter->netdev;
627 int i, err = 0, vector = 0;
628
629 vector = 0;
630
631 for (i = 0; i < adapter->num_tx_queues; i++) {
632 struct igb_ring *ring = &(adapter->tx_ring[i]);
633 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
634 err = request_irq(adapter->msix_entries[vector].vector,
635 &igb_msix_tx, 0, ring->name,
636 &(adapter->tx_ring[i]));
637 if (err)
638 goto out;
639 ring->itr_register = E1000_EITR(0) + (vector << 2);
640 ring->itr_val = 976; /* ~4000 ints/sec */
641 vector++;
642 }
643 for (i = 0; i < adapter->num_rx_queues; i++) {
644 struct igb_ring *ring = &(adapter->rx_ring[i]);
645 if (strlen(netdev->name) < (IFNAMSIZ - 5))
646 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
647 else
648 memcpy(ring->name, netdev->name, IFNAMSIZ);
649 err = request_irq(adapter->msix_entries[vector].vector,
650 &igb_msix_rx, 0, ring->name,
651 &(adapter->rx_ring[i]));
652 if (err)
653 goto out;
654 ring->itr_register = E1000_EITR(0) + (vector << 2);
655 ring->itr_val = adapter->itr;
656 vector++;
657 }
658
659 err = request_irq(adapter->msix_entries[vector].vector,
660 &igb_msix_other, 0, netdev->name, netdev);
661 if (err)
662 goto out;
663
664 igb_configure_msix(adapter);
665 return 0;
666 out:
667 return err;
668 }
669
670 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
671 {
672 if (adapter->msix_entries) {
673 pci_disable_msix(adapter->pdev);
674 kfree(adapter->msix_entries);
675 adapter->msix_entries = NULL;
676 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
677 pci_disable_msi(adapter->pdev);
678 return;
679 }
680
681
682 /**
683 * igb_set_interrupt_capability - set MSI or MSI-X if supported
684 *
685 * Attempt to configure interrupts using the best available
686 * capabilities of the hardware and kernel.
687 **/
688 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
689 {
690 int err;
691 int numvecs, i;
692
693 /* Number of supported queues. */
694 /* Having more queues than CPUs doesn't make sense. */
695 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
696 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
697
698 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
699 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
700 GFP_KERNEL);
701 if (!adapter->msix_entries)
702 goto msi_only;
703
704 for (i = 0; i < numvecs; i++)
705 adapter->msix_entries[i].entry = i;
706
707 err = pci_enable_msix(adapter->pdev,
708 adapter->msix_entries,
709 numvecs);
710 if (err == 0)
711 goto out;
712
713 igb_reset_interrupt_capability(adapter);
714
715 /* If we can't do MSI-X, try MSI */
716 msi_only:
717 #ifdef CONFIG_PCI_IOV
718 /* disable SR-IOV for non MSI-X configurations */
719 if (adapter->vf_data) {
720 struct e1000_hw *hw = &adapter->hw;
721 /* disable iov and allow time for transactions to clear */
722 pci_disable_sriov(adapter->pdev);
723 msleep(500);
724
725 kfree(adapter->vf_data);
726 adapter->vf_data = NULL;
727 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
728 msleep(100);
729 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
730 }
731 #endif
732 adapter->num_rx_queues = 1;
733 adapter->num_tx_queues = 1;
734 if (!pci_enable_msi(adapter->pdev))
735 adapter->flags |= IGB_FLAG_HAS_MSI;
736 out:
737 /* Notify the stack of the (possibly) reduced Tx Queue count. */
738 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
739 return;
740 }
741
742 /**
743 * igb_request_irq - initialize interrupts
744 *
745 * Attempts to configure interrupts using the best available
746 * capabilities of the hardware and kernel.
747 **/
748 static int igb_request_irq(struct igb_adapter *adapter)
749 {
750 struct net_device *netdev = adapter->netdev;
751 struct e1000_hw *hw = &adapter->hw;
752 int err = 0;
753
754 if (adapter->msix_entries) {
755 err = igb_request_msix(adapter);
756 if (!err)
757 goto request_done;
758 /* fall back to MSI */
759 igb_reset_interrupt_capability(adapter);
760 if (!pci_enable_msi(adapter->pdev))
761 adapter->flags |= IGB_FLAG_HAS_MSI;
762 igb_free_all_tx_resources(adapter);
763 igb_free_all_rx_resources(adapter);
764 adapter->num_rx_queues = 1;
765 igb_alloc_queues(adapter);
766 } else {
767 switch (hw->mac.type) {
768 case e1000_82575:
769 wr32(E1000_MSIXBM(0),
770 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
771 break;
772 case e1000_82576:
773 wr32(E1000_IVAR0, E1000_IVAR_VALID);
774 break;
775 default:
776 break;
777 }
778 }
779
780 if (adapter->flags & IGB_FLAG_HAS_MSI) {
781 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
782 netdev->name, netdev);
783 if (!err)
784 goto request_done;
785 /* fall back to legacy interrupts */
786 igb_reset_interrupt_capability(adapter);
787 adapter->flags &= ~IGB_FLAG_HAS_MSI;
788 }
789
790 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
791 netdev->name, netdev);
792
793 if (err)
794 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
795 err);
796
797 request_done:
798 return err;
799 }
800
801 static void igb_free_irq(struct igb_adapter *adapter)
802 {
803 struct net_device *netdev = adapter->netdev;
804
805 if (adapter->msix_entries) {
806 int vector = 0, i;
807
808 for (i = 0; i < adapter->num_tx_queues; i++)
809 free_irq(adapter->msix_entries[vector++].vector,
810 &(adapter->tx_ring[i]));
811 for (i = 0; i < adapter->num_rx_queues; i++)
812 free_irq(adapter->msix_entries[vector++].vector,
813 &(adapter->rx_ring[i]));
814
815 free_irq(adapter->msix_entries[vector++].vector, netdev);
816 return;
817 }
818
819 free_irq(adapter->pdev->irq, netdev);
820 }
821
822 /**
823 * igb_irq_disable - Mask off interrupt generation on the NIC
824 * @adapter: board private structure
825 **/
826 static void igb_irq_disable(struct igb_adapter *adapter)
827 {
828 struct e1000_hw *hw = &adapter->hw;
829
830 if (adapter->msix_entries) {
831 u32 regval = rd32(E1000_EIAM);
832 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
833 wr32(E1000_EIMC, adapter->eims_enable_mask);
834 regval = rd32(E1000_EIAC);
835 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
836 }
837
838 wr32(E1000_IAM, 0);
839 wr32(E1000_IMC, ~0);
840 wrfl();
841 synchronize_irq(adapter->pdev->irq);
842 }
843
844 /**
845 * igb_irq_enable - Enable default interrupt generation settings
846 * @adapter: board private structure
847 **/
848 static void igb_irq_enable(struct igb_adapter *adapter)
849 {
850 struct e1000_hw *hw = &adapter->hw;
851
852 if (adapter->msix_entries) {
853 u32 regval = rd32(E1000_EIAC);
854 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
855 regval = rd32(E1000_EIAM);
856 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
857 wr32(E1000_EIMS, adapter->eims_enable_mask);
858 if (adapter->vfs_allocated_count)
859 wr32(E1000_MBVFIMR, 0xFF);
860 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
861 E1000_IMS_DOUTSYNC));
862 } else {
863 wr32(E1000_IMS, IMS_ENABLE_MASK);
864 wr32(E1000_IAM, IMS_ENABLE_MASK);
865 }
866 }
867
868 static void igb_update_mng_vlan(struct igb_adapter *adapter)
869 {
870 struct net_device *netdev = adapter->netdev;
871 u16 vid = adapter->hw.mng_cookie.vlan_id;
872 u16 old_vid = adapter->mng_vlan_id;
873 if (adapter->vlgrp) {
874 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
875 if (adapter->hw.mng_cookie.status &
876 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
877 igb_vlan_rx_add_vid(netdev, vid);
878 adapter->mng_vlan_id = vid;
879 } else
880 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
881
882 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
883 (vid != old_vid) &&
884 !vlan_group_get_device(adapter->vlgrp, old_vid))
885 igb_vlan_rx_kill_vid(netdev, old_vid);
886 } else
887 adapter->mng_vlan_id = vid;
888 }
889 }
890
891 /**
892 * igb_release_hw_control - release control of the h/w to f/w
893 * @adapter: address of board private structure
894 *
895 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
896 * For ASF and Pass Through versions of f/w this means that the
897 * driver is no longer loaded.
898 *
899 **/
900 static void igb_release_hw_control(struct igb_adapter *adapter)
901 {
902 struct e1000_hw *hw = &adapter->hw;
903 u32 ctrl_ext;
904
905 /* Let firmware take over control of h/w */
906 ctrl_ext = rd32(E1000_CTRL_EXT);
907 wr32(E1000_CTRL_EXT,
908 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
909 }
910
911
912 /**
913 * igb_get_hw_control - get control of the h/w from f/w
914 * @adapter: address of board private structure
915 *
916 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
917 * For ASF and Pass Through versions of f/w this means that
918 * the driver is loaded.
919 *
920 **/
921 static void igb_get_hw_control(struct igb_adapter *adapter)
922 {
923 struct e1000_hw *hw = &adapter->hw;
924 u32 ctrl_ext;
925
926 /* Let firmware know the driver has taken over */
927 ctrl_ext = rd32(E1000_CTRL_EXT);
928 wr32(E1000_CTRL_EXT,
929 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
930 }
931
932 /**
933 * igb_configure - configure the hardware for RX and TX
934 * @adapter: private board structure
935 **/
936 static void igb_configure(struct igb_adapter *adapter)
937 {
938 struct net_device *netdev = adapter->netdev;
939 int i;
940
941 igb_get_hw_control(adapter);
942 igb_set_rx_mode(netdev);
943
944 igb_restore_vlan(adapter);
945
946 igb_configure_tx(adapter);
947 igb_setup_rctl(adapter);
948 igb_configure_rx(adapter);
949
950 igb_rx_fifo_flush_82575(&adapter->hw);
951
952 /* call igb_desc_unused which always leaves
953 * at least 1 descriptor unused to make sure
954 * next_to_use != next_to_clean */
955 for (i = 0; i < adapter->num_rx_queues; i++) {
956 struct igb_ring *ring = &adapter->rx_ring[i];
957 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
958 }
959
960
961 adapter->tx_queue_len = netdev->tx_queue_len;
962 }
963
964
965 /**
966 * igb_up - Open the interface and prepare it to handle traffic
967 * @adapter: board private structure
968 **/
969
970 int igb_up(struct igb_adapter *adapter)
971 {
972 struct e1000_hw *hw = &adapter->hw;
973 int i;
974
975 /* hardware has been reset, we need to reload some things */
976 igb_configure(adapter);
977
978 clear_bit(__IGB_DOWN, &adapter->state);
979
980 for (i = 0; i < adapter->num_rx_queues; i++)
981 napi_enable(&adapter->rx_ring[i].napi);
982 if (adapter->msix_entries)
983 igb_configure_msix(adapter);
984
985 igb_vmm_control(adapter);
986 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
987 igb_set_vmolr(hw, adapter->vfs_allocated_count);
988
989 /* Clear any pending interrupts. */
990 rd32(E1000_ICR);
991 igb_irq_enable(adapter);
992
993 netif_tx_start_all_queues(adapter->netdev);
994
995 /* Fire a link change interrupt to start the watchdog. */
996 wr32(E1000_ICS, E1000_ICS_LSC);
997 return 0;
998 }
999
1000 void igb_down(struct igb_adapter *adapter)
1001 {
1002 struct e1000_hw *hw = &adapter->hw;
1003 struct net_device *netdev = adapter->netdev;
1004 u32 tctl, rctl;
1005 int i;
1006
1007 /* signal that we're down so the interrupt handler does not
1008 * reschedule our watchdog timer */
1009 set_bit(__IGB_DOWN, &adapter->state);
1010
1011 /* disable receives in the hardware */
1012 rctl = rd32(E1000_RCTL);
1013 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1014 /* flush and sleep below */
1015
1016 netif_tx_stop_all_queues(netdev);
1017
1018 /* disable transmits in the hardware */
1019 tctl = rd32(E1000_TCTL);
1020 tctl &= ~E1000_TCTL_EN;
1021 wr32(E1000_TCTL, tctl);
1022 /* flush both disables and wait for them to finish */
1023 wrfl();
1024 msleep(10);
1025
1026 for (i = 0; i < adapter->num_rx_queues; i++)
1027 napi_disable(&adapter->rx_ring[i].napi);
1028
1029 igb_irq_disable(adapter);
1030
1031 del_timer_sync(&adapter->watchdog_timer);
1032 del_timer_sync(&adapter->phy_info_timer);
1033
1034 netdev->tx_queue_len = adapter->tx_queue_len;
1035 netif_carrier_off(netdev);
1036
1037 /* record the stats before reset*/
1038 igb_update_stats(adapter);
1039
1040 adapter->link_speed = 0;
1041 adapter->link_duplex = 0;
1042
1043 if (!pci_channel_offline(adapter->pdev))
1044 igb_reset(adapter);
1045 igb_clean_all_tx_rings(adapter);
1046 igb_clean_all_rx_rings(adapter);
1047 #ifdef CONFIG_IGB_DCA
1048
1049 /* since we reset the hardware DCA settings were cleared */
1050 igb_setup_dca(adapter);
1051 #endif
1052 }
1053
1054 void igb_reinit_locked(struct igb_adapter *adapter)
1055 {
1056 WARN_ON(in_interrupt());
1057 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1058 msleep(1);
1059 igb_down(adapter);
1060 igb_up(adapter);
1061 clear_bit(__IGB_RESETTING, &adapter->state);
1062 }
1063
1064 void igb_reset(struct igb_adapter *adapter)
1065 {
1066 struct e1000_hw *hw = &adapter->hw;
1067 struct e1000_mac_info *mac = &hw->mac;
1068 struct e1000_fc_info *fc = &hw->fc;
1069 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1070 u16 hwm;
1071
1072 /* Repartition Pba for greater than 9k mtu
1073 * To take effect CTRL.RST is required.
1074 */
1075 switch (mac->type) {
1076 case e1000_82576:
1077 pba = E1000_PBA_64K;
1078 break;
1079 case e1000_82575:
1080 default:
1081 pba = E1000_PBA_34K;
1082 break;
1083 }
1084
1085 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1086 (mac->type < e1000_82576)) {
1087 /* adjust PBA for jumbo frames */
1088 wr32(E1000_PBA, pba);
1089
1090 /* To maintain wire speed transmits, the Tx FIFO should be
1091 * large enough to accommodate two full transmit packets,
1092 * rounded up to the next 1KB and expressed in KB. Likewise,
1093 * the Rx FIFO should be large enough to accommodate at least
1094 * one full receive packet and is similarly rounded up and
1095 * expressed in KB. */
1096 pba = rd32(E1000_PBA);
1097 /* upper 16 bits has Tx packet buffer allocation size in KB */
1098 tx_space = pba >> 16;
1099 /* lower 16 bits has Rx packet buffer allocation size in KB */
1100 pba &= 0xffff;
1101 /* the tx fifo also stores 16 bytes of information about the tx
1102 * but don't include ethernet FCS because hardware appends it */
1103 min_tx_space = (adapter->max_frame_size +
1104 sizeof(union e1000_adv_tx_desc) -
1105 ETH_FCS_LEN) * 2;
1106 min_tx_space = ALIGN(min_tx_space, 1024);
1107 min_tx_space >>= 10;
1108 /* software strips receive CRC, so leave room for it */
1109 min_rx_space = adapter->max_frame_size;
1110 min_rx_space = ALIGN(min_rx_space, 1024);
1111 min_rx_space >>= 10;
1112
1113 /* If current Tx allocation is less than the min Tx FIFO size,
1114 * and the min Tx FIFO size is less than the current Rx FIFO
1115 * allocation, take space away from current Rx allocation */
1116 if (tx_space < min_tx_space &&
1117 ((min_tx_space - tx_space) < pba)) {
1118 pba = pba - (min_tx_space - tx_space);
1119
1120 /* if short on rx space, rx wins and must trump tx
1121 * adjustment */
1122 if (pba < min_rx_space)
1123 pba = min_rx_space;
1124 }
1125 wr32(E1000_PBA, pba);
1126 }
1127
1128 /* flow control settings */
1129 /* The high water mark must be low enough to fit one full frame
1130 * (or the size used for early receive) above it in the Rx FIFO.
1131 * Set it to the lower of:
1132 * - 90% of the Rx FIFO size, or
1133 * - the full Rx FIFO size minus one full frame */
1134 hwm = min(((pba << 10) * 9 / 10),
1135 ((pba << 10) - 2 * adapter->max_frame_size));
1136
1137 if (mac->type < e1000_82576) {
1138 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1139 fc->low_water = fc->high_water - 8;
1140 } else {
1141 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1142 fc->low_water = fc->high_water - 16;
1143 }
1144 fc->pause_time = 0xFFFF;
1145 fc->send_xon = 1;
1146 fc->current_mode = fc->requested_mode;
1147
1148 /* disable receive for all VFs and wait one second */
1149 if (adapter->vfs_allocated_count) {
1150 int i;
1151 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1152 adapter->vf_data[i].clear_to_send = false;
1153
1154 /* ping all the active vfs to let them know we are going down */
1155 igb_ping_all_vfs(adapter);
1156
1157 /* disable transmits and receives */
1158 wr32(E1000_VFRE, 0);
1159 wr32(E1000_VFTE, 0);
1160 }
1161
1162 /* Allow time for pending master requests to run */
1163 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1164 wr32(E1000_WUC, 0);
1165
1166 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1167 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1168
1169 igb_update_mng_vlan(adapter);
1170
1171 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1172 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1173
1174 igb_reset_adaptive(&adapter->hw);
1175 igb_get_phy_info(&adapter->hw);
1176 }
1177
1178 static const struct net_device_ops igb_netdev_ops = {
1179 .ndo_open = igb_open,
1180 .ndo_stop = igb_close,
1181 .ndo_start_xmit = igb_xmit_frame_adv,
1182 .ndo_get_stats = igb_get_stats,
1183 .ndo_set_rx_mode = igb_set_rx_mode,
1184 .ndo_set_multicast_list = igb_set_rx_mode,
1185 .ndo_set_mac_address = igb_set_mac,
1186 .ndo_change_mtu = igb_change_mtu,
1187 .ndo_do_ioctl = igb_ioctl,
1188 .ndo_tx_timeout = igb_tx_timeout,
1189 .ndo_validate_addr = eth_validate_addr,
1190 .ndo_vlan_rx_register = igb_vlan_rx_register,
1191 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1192 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1193 #ifdef CONFIG_NET_POLL_CONTROLLER
1194 .ndo_poll_controller = igb_netpoll,
1195 #endif
1196 };
1197
1198 /**
1199 * igb_probe - Device Initialization Routine
1200 * @pdev: PCI device information struct
1201 * @ent: entry in igb_pci_tbl
1202 *
1203 * Returns 0 on success, negative on failure
1204 *
1205 * igb_probe initializes an adapter identified by a pci_dev structure.
1206 * The OS initialization, configuring of the adapter private structure,
1207 * and a hardware reset occur.
1208 **/
1209 static int __devinit igb_probe(struct pci_dev *pdev,
1210 const struct pci_device_id *ent)
1211 {
1212 struct net_device *netdev;
1213 struct igb_adapter *adapter;
1214 struct e1000_hw *hw;
1215 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1216 unsigned long mmio_start, mmio_len;
1217 int err, pci_using_dac;
1218 u16 eeprom_data = 0;
1219 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1220 u32 part_num;
1221
1222 err = pci_enable_device_mem(pdev);
1223 if (err)
1224 return err;
1225
1226 pci_using_dac = 0;
1227 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1228 if (!err) {
1229 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1230 if (!err)
1231 pci_using_dac = 1;
1232 } else {
1233 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1234 if (err) {
1235 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1236 if (err) {
1237 dev_err(&pdev->dev, "No usable DMA "
1238 "configuration, aborting\n");
1239 goto err_dma;
1240 }
1241 }
1242 }
1243
1244 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1245 IORESOURCE_MEM),
1246 igb_driver_name);
1247 if (err)
1248 goto err_pci_reg;
1249
1250 pci_enable_pcie_error_reporting(pdev);
1251
1252 pci_set_master(pdev);
1253 pci_save_state(pdev);
1254
1255 err = -ENOMEM;
1256 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1257 IGB_ABS_MAX_TX_QUEUES);
1258 if (!netdev)
1259 goto err_alloc_etherdev;
1260
1261 SET_NETDEV_DEV(netdev, &pdev->dev);
1262
1263 pci_set_drvdata(pdev, netdev);
1264 adapter = netdev_priv(netdev);
1265 adapter->netdev = netdev;
1266 adapter->pdev = pdev;
1267 hw = &adapter->hw;
1268 hw->back = adapter;
1269 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1270
1271 mmio_start = pci_resource_start(pdev, 0);
1272 mmio_len = pci_resource_len(pdev, 0);
1273
1274 err = -EIO;
1275 hw->hw_addr = ioremap(mmio_start, mmio_len);
1276 if (!hw->hw_addr)
1277 goto err_ioremap;
1278
1279 netdev->netdev_ops = &igb_netdev_ops;
1280 igb_set_ethtool_ops(netdev);
1281 netdev->watchdog_timeo = 5 * HZ;
1282
1283 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1284
1285 netdev->mem_start = mmio_start;
1286 netdev->mem_end = mmio_start + mmio_len;
1287
1288 /* PCI config space info */
1289 hw->vendor_id = pdev->vendor;
1290 hw->device_id = pdev->device;
1291 hw->revision_id = pdev->revision;
1292 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1293 hw->subsystem_device_id = pdev->subsystem_device;
1294
1295 /* setup the private structure */
1296 hw->back = adapter;
1297 /* Copy the default MAC, PHY and NVM function pointers */
1298 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1299 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1300 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1301 /* Initialize skew-specific constants */
1302 err = ei->get_invariants(hw);
1303 if (err)
1304 goto err_sw_init;
1305
1306 #ifdef CONFIG_PCI_IOV
1307 /* since iov functionality isn't critical to base device function we
1308 * can accept failure. If it fails we don't allow iov to be enabled */
1309 if (hw->mac.type == e1000_82576) {
1310 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1311 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1312 int i;
1313 unsigned char mac_addr[ETH_ALEN];
1314
1315 if (num_vfs) {
1316 adapter->vf_data = kcalloc(num_vfs,
1317 sizeof(struct vf_data_storage),
1318 GFP_KERNEL);
1319 if (!adapter->vf_data) {
1320 dev_err(&pdev->dev,
1321 "Could not allocate VF private data - "
1322 "IOV enable failed\n");
1323 } else {
1324 err = pci_enable_sriov(pdev, num_vfs);
1325 if (!err) {
1326 adapter->vfs_allocated_count = num_vfs;
1327 dev_info(&pdev->dev,
1328 "%d vfs allocated\n",
1329 num_vfs);
1330 for (i = 0;
1331 i < adapter->vfs_allocated_count;
1332 i++) {
1333 random_ether_addr(mac_addr);
1334 igb_set_vf_mac(adapter, i,
1335 mac_addr);
1336 }
1337 } else {
1338 kfree(adapter->vf_data);
1339 adapter->vf_data = NULL;
1340 }
1341 }
1342 }
1343 }
1344
1345 #endif
1346 /* setup the private structure */
1347 err = igb_sw_init(adapter);
1348 if (err)
1349 goto err_sw_init;
1350
1351 igb_get_bus_info_pcie(hw);
1352
1353 /* set flags */
1354 switch (hw->mac.type) {
1355 case e1000_82575:
1356 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1357 break;
1358 case e1000_82576:
1359 default:
1360 break;
1361 }
1362
1363 hw->phy.autoneg_wait_to_complete = false;
1364 hw->mac.adaptive_ifs = true;
1365
1366 /* Copper options */
1367 if (hw->phy.media_type == e1000_media_type_copper) {
1368 hw->phy.mdix = AUTO_ALL_MODES;
1369 hw->phy.disable_polarity_correction = false;
1370 hw->phy.ms_type = e1000_ms_hw_default;
1371 }
1372
1373 if (igb_check_reset_block(hw))
1374 dev_info(&pdev->dev,
1375 "PHY reset is blocked due to SOL/IDER session.\n");
1376
1377 netdev->features = NETIF_F_SG |
1378 NETIF_F_IP_CSUM |
1379 NETIF_F_HW_VLAN_TX |
1380 NETIF_F_HW_VLAN_RX |
1381 NETIF_F_HW_VLAN_FILTER;
1382
1383 netdev->features |= NETIF_F_IPV6_CSUM;
1384 netdev->features |= NETIF_F_TSO;
1385 netdev->features |= NETIF_F_TSO6;
1386
1387 netdev->features |= NETIF_F_GRO;
1388
1389 netdev->vlan_features |= NETIF_F_TSO;
1390 netdev->vlan_features |= NETIF_F_TSO6;
1391 netdev->vlan_features |= NETIF_F_IP_CSUM;
1392 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1393 netdev->vlan_features |= NETIF_F_SG;
1394
1395 if (pci_using_dac)
1396 netdev->features |= NETIF_F_HIGHDMA;
1397
1398 if (adapter->hw.mac.type == e1000_82576)
1399 netdev->features |= NETIF_F_SCTP_CSUM;
1400
1401 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1402
1403 /* before reading the NVM, reset the controller to put the device in a
1404 * known good starting state */
1405 hw->mac.ops.reset_hw(hw);
1406
1407 /* make sure the NVM is good */
1408 if (igb_validate_nvm_checksum(hw) < 0) {
1409 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1410 err = -EIO;
1411 goto err_eeprom;
1412 }
1413
1414 /* copy the MAC address out of the NVM */
1415 if (hw->mac.ops.read_mac_addr(hw))
1416 dev_err(&pdev->dev, "NVM Read Error\n");
1417
1418 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1419 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1420
1421 if (!is_valid_ether_addr(netdev->perm_addr)) {
1422 dev_err(&pdev->dev, "Invalid MAC Address\n");
1423 err = -EIO;
1424 goto err_eeprom;
1425 }
1426
1427 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1428 (unsigned long) adapter);
1429 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1430 (unsigned long) adapter);
1431
1432 INIT_WORK(&adapter->reset_task, igb_reset_task);
1433 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1434
1435 /* Initialize link properties that are user-changeable */
1436 adapter->fc_autoneg = true;
1437 hw->mac.autoneg = true;
1438 hw->phy.autoneg_advertised = 0x2f;
1439
1440 hw->fc.requested_mode = e1000_fc_default;
1441 hw->fc.current_mode = e1000_fc_default;
1442
1443 adapter->itr_setting = IGB_DEFAULT_ITR;
1444 adapter->itr = IGB_START_ITR;
1445
1446 igb_validate_mdi_setting(hw);
1447
1448 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1449 * enable the ACPI Magic Packet filter
1450 */
1451
1452 if (hw->bus.func == 0)
1453 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1454 else if (hw->bus.func == 1)
1455 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1456
1457 if (eeprom_data & eeprom_apme_mask)
1458 adapter->eeprom_wol |= E1000_WUFC_MAG;
1459
1460 /* now that we have the eeprom settings, apply the special cases where
1461 * the eeprom may be wrong or the board simply won't support wake on
1462 * lan on a particular port */
1463 switch (pdev->device) {
1464 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1465 adapter->eeprom_wol = 0;
1466 break;
1467 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1468 case E1000_DEV_ID_82576_FIBER:
1469 case E1000_DEV_ID_82576_SERDES:
1470 /* Wake events only supported on port A for dual fiber
1471 * regardless of eeprom setting */
1472 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1473 adapter->eeprom_wol = 0;
1474 break;
1475 case E1000_DEV_ID_82576_QUAD_COPPER:
1476 /* if quad port adapter, disable WoL on all but port A */
1477 if (global_quad_port_a != 0)
1478 adapter->eeprom_wol = 0;
1479 else
1480 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1481 /* Reset for multiple quad port adapters */
1482 if (++global_quad_port_a == 4)
1483 global_quad_port_a = 0;
1484 break;
1485 }
1486
1487 /* initialize the wol settings based on the eeprom settings */
1488 adapter->wol = adapter->eeprom_wol;
1489 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1490
1491 /* reset the hardware with the new settings */
1492 igb_reset(adapter);
1493
1494 /* let the f/w know that the h/w is now under the control of the
1495 * driver. */
1496 igb_get_hw_control(adapter);
1497
1498 strcpy(netdev->name, "eth%d");
1499 err = register_netdev(netdev);
1500 if (err)
1501 goto err_register;
1502
1503 /* carrier off reporting is important to ethtool even BEFORE open */
1504 netif_carrier_off(netdev);
1505
1506 #ifdef CONFIG_IGB_DCA
1507 if (dca_add_requester(&pdev->dev) == 0) {
1508 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1509 dev_info(&pdev->dev, "DCA enabled\n");
1510 igb_setup_dca(adapter);
1511 }
1512 #endif
1513
1514 /*
1515 * Initialize hardware timer: we keep it running just in case
1516 * that some program needs it later on.
1517 */
1518 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1519 adapter->cycles.read = igb_read_clock;
1520 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1521 adapter->cycles.mult = 1;
1522 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1523 wr32(E1000_TIMINCA,
1524 (1<<24) |
1525 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1526 #if 0
1527 /*
1528 * Avoid rollover while we initialize by resetting the time counter.
1529 */
1530 wr32(E1000_SYSTIML, 0x00000000);
1531 wr32(E1000_SYSTIMH, 0x00000000);
1532 #else
1533 /*
1534 * Set registers so that rollover occurs soon to test this.
1535 */
1536 wr32(E1000_SYSTIML, 0x00000000);
1537 wr32(E1000_SYSTIMH, 0xFF800000);
1538 #endif
1539 wrfl();
1540 timecounter_init(&adapter->clock,
1541 &adapter->cycles,
1542 ktime_to_ns(ktime_get_real()));
1543
1544 /*
1545 * Synchronize our NIC clock against system wall clock. NIC
1546 * time stamp reading requires ~3us per sample, each sample
1547 * was pretty stable even under load => only require 10
1548 * samples for each offset comparison.
1549 */
1550 memset(&adapter->compare, 0, sizeof(adapter->compare));
1551 adapter->compare.source = &adapter->clock;
1552 adapter->compare.target = ktime_get_real;
1553 adapter->compare.num_samples = 10;
1554 timecompare_update(&adapter->compare, 0);
1555
1556 #ifdef DEBUG
1557 {
1558 char buffer[160];
1559 printk(KERN_DEBUG
1560 "igb: %s: hw %p initialized timer\n",
1561 igb_get_time_str(adapter, buffer),
1562 &adapter->hw);
1563 }
1564 #endif
1565
1566 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1567 /* print bus type/speed/width info */
1568 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1569 netdev->name,
1570 ((hw->bus.speed == e1000_bus_speed_2500)
1571 ? "2.5Gb/s" : "unknown"),
1572 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1573 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1574 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1575 "unknown"),
1576 netdev->dev_addr);
1577
1578 igb_read_part_num(hw, &part_num);
1579 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1580 (part_num >> 8), (part_num & 0xff));
1581
1582 dev_info(&pdev->dev,
1583 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1584 adapter->msix_entries ? "MSI-X" :
1585 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1586 adapter->num_rx_queues, adapter->num_tx_queues);
1587
1588 return 0;
1589
1590 err_register:
1591 igb_release_hw_control(adapter);
1592 err_eeprom:
1593 if (!igb_check_reset_block(hw))
1594 igb_reset_phy(hw);
1595
1596 if (hw->flash_address)
1597 iounmap(hw->flash_address);
1598
1599 igb_free_queues(adapter);
1600 err_sw_init:
1601 iounmap(hw->hw_addr);
1602 err_ioremap:
1603 free_netdev(netdev);
1604 err_alloc_etherdev:
1605 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1606 IORESOURCE_MEM));
1607 err_pci_reg:
1608 err_dma:
1609 pci_disable_device(pdev);
1610 return err;
1611 }
1612
1613 /**
1614 * igb_remove - Device Removal Routine
1615 * @pdev: PCI device information struct
1616 *
1617 * igb_remove is called by the PCI subsystem to alert the driver
1618 * that it should release a PCI device. The could be caused by a
1619 * Hot-Plug event, or because the driver is going to be removed from
1620 * memory.
1621 **/
1622 static void __devexit igb_remove(struct pci_dev *pdev)
1623 {
1624 struct net_device *netdev = pci_get_drvdata(pdev);
1625 struct igb_adapter *adapter = netdev_priv(netdev);
1626 struct e1000_hw *hw = &adapter->hw;
1627
1628 /* flush_scheduled work may reschedule our watchdog task, so
1629 * explicitly disable watchdog tasks from being rescheduled */
1630 set_bit(__IGB_DOWN, &adapter->state);
1631 del_timer_sync(&adapter->watchdog_timer);
1632 del_timer_sync(&adapter->phy_info_timer);
1633
1634 flush_scheduled_work();
1635
1636 #ifdef CONFIG_IGB_DCA
1637 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1638 dev_info(&pdev->dev, "DCA disabled\n");
1639 dca_remove_requester(&pdev->dev);
1640 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1641 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1642 }
1643 #endif
1644
1645 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1646 * would have already happened in close and is redundant. */
1647 igb_release_hw_control(adapter);
1648
1649 unregister_netdev(netdev);
1650
1651 if (!igb_check_reset_block(&adapter->hw))
1652 igb_reset_phy(&adapter->hw);
1653
1654 igb_reset_interrupt_capability(adapter);
1655
1656 igb_free_queues(adapter);
1657
1658 #ifdef CONFIG_PCI_IOV
1659 /* reclaim resources allocated to VFs */
1660 if (adapter->vf_data) {
1661 /* disable iov and allow time for transactions to clear */
1662 pci_disable_sriov(pdev);
1663 msleep(500);
1664
1665 kfree(adapter->vf_data);
1666 adapter->vf_data = NULL;
1667 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1668 msleep(100);
1669 dev_info(&pdev->dev, "IOV Disabled\n");
1670 }
1671 #endif
1672 iounmap(hw->hw_addr);
1673 if (hw->flash_address)
1674 iounmap(hw->flash_address);
1675 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1676 IORESOURCE_MEM));
1677
1678 free_netdev(netdev);
1679
1680 pci_disable_pcie_error_reporting(pdev);
1681
1682 pci_disable_device(pdev);
1683 }
1684
1685 /**
1686 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1687 * @adapter: board private structure to initialize
1688 *
1689 * igb_sw_init initializes the Adapter private data structure.
1690 * Fields are initialized based on PCI device information and
1691 * OS network device settings (MTU size).
1692 **/
1693 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1694 {
1695 struct e1000_hw *hw = &adapter->hw;
1696 struct net_device *netdev = adapter->netdev;
1697 struct pci_dev *pdev = adapter->pdev;
1698
1699 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1700
1701 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1702 adapter->rx_ring_count = IGB_DEFAULT_RXD;
1703 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1704 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1705 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1706 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1707
1708 /* This call may decrease the number of queues depending on
1709 * interrupt mode. */
1710 igb_set_interrupt_capability(adapter);
1711
1712 if (igb_alloc_queues(adapter)) {
1713 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1714 return -ENOMEM;
1715 }
1716
1717 /* Explicitly disable IRQ since the NIC can be in any state. */
1718 igb_irq_disable(adapter);
1719
1720 set_bit(__IGB_DOWN, &adapter->state);
1721 return 0;
1722 }
1723
1724 /**
1725 * igb_open - Called when a network interface is made active
1726 * @netdev: network interface device structure
1727 *
1728 * Returns 0 on success, negative value on failure
1729 *
1730 * The open entry point is called when a network interface is made
1731 * active by the system (IFF_UP). At this point all resources needed
1732 * for transmit and receive operations are allocated, the interrupt
1733 * handler is registered with the OS, the watchdog timer is started,
1734 * and the stack is notified that the interface is ready.
1735 **/
1736 static int igb_open(struct net_device *netdev)
1737 {
1738 struct igb_adapter *adapter = netdev_priv(netdev);
1739 struct e1000_hw *hw = &adapter->hw;
1740 int err;
1741 int i;
1742
1743 /* disallow open during test */
1744 if (test_bit(__IGB_TESTING, &adapter->state))
1745 return -EBUSY;
1746
1747 netif_carrier_off(netdev);
1748
1749 /* allocate transmit descriptors */
1750 err = igb_setup_all_tx_resources(adapter);
1751 if (err)
1752 goto err_setup_tx;
1753
1754 /* allocate receive descriptors */
1755 err = igb_setup_all_rx_resources(adapter);
1756 if (err)
1757 goto err_setup_rx;
1758
1759 /* e1000_power_up_phy(adapter); */
1760
1761 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1762 if ((adapter->hw.mng_cookie.status &
1763 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1764 igb_update_mng_vlan(adapter);
1765
1766 /* before we allocate an interrupt, we must be ready to handle it.
1767 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1768 * as soon as we call pci_request_irq, so we have to setup our
1769 * clean_rx handler before we do so. */
1770 igb_configure(adapter);
1771
1772 igb_vmm_control(adapter);
1773 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1774 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1775
1776 err = igb_request_irq(adapter);
1777 if (err)
1778 goto err_req_irq;
1779
1780 /* From here on the code is the same as igb_up() */
1781 clear_bit(__IGB_DOWN, &adapter->state);
1782
1783 for (i = 0; i < adapter->num_rx_queues; i++)
1784 napi_enable(&adapter->rx_ring[i].napi);
1785
1786 /* Clear any pending interrupts. */
1787 rd32(E1000_ICR);
1788
1789 igb_irq_enable(adapter);
1790
1791 netif_tx_start_all_queues(netdev);
1792
1793 /* Fire a link status change interrupt to start the watchdog. */
1794 wr32(E1000_ICS, E1000_ICS_LSC);
1795
1796 return 0;
1797
1798 err_req_irq:
1799 igb_release_hw_control(adapter);
1800 /* e1000_power_down_phy(adapter); */
1801 igb_free_all_rx_resources(adapter);
1802 err_setup_rx:
1803 igb_free_all_tx_resources(adapter);
1804 err_setup_tx:
1805 igb_reset(adapter);
1806
1807 return err;
1808 }
1809
1810 /**
1811 * igb_close - Disables a network interface
1812 * @netdev: network interface device structure
1813 *
1814 * Returns 0, this is not allowed to fail
1815 *
1816 * The close entry point is called when an interface is de-activated
1817 * by the OS. The hardware is still under the driver's control, but
1818 * needs to be disabled. A global MAC reset is issued to stop the
1819 * hardware, and all transmit and receive resources are freed.
1820 **/
1821 static int igb_close(struct net_device *netdev)
1822 {
1823 struct igb_adapter *adapter = netdev_priv(netdev);
1824
1825 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1826 igb_down(adapter);
1827
1828 igb_free_irq(adapter);
1829
1830 igb_free_all_tx_resources(adapter);
1831 igb_free_all_rx_resources(adapter);
1832
1833 /* kill manageability vlan ID if supported, but not if a vlan with
1834 * the same ID is registered on the host OS (let 8021q kill it) */
1835 if ((adapter->hw.mng_cookie.status &
1836 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1837 !(adapter->vlgrp &&
1838 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1839 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1840
1841 return 0;
1842 }
1843
1844 /**
1845 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1846 * @adapter: board private structure
1847 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1848 *
1849 * Return 0 on success, negative on failure
1850 **/
1851 int igb_setup_tx_resources(struct igb_adapter *adapter,
1852 struct igb_ring *tx_ring)
1853 {
1854 struct pci_dev *pdev = adapter->pdev;
1855 int size;
1856
1857 size = sizeof(struct igb_buffer) * tx_ring->count;
1858 tx_ring->buffer_info = vmalloc(size);
1859 if (!tx_ring->buffer_info)
1860 goto err;
1861 memset(tx_ring->buffer_info, 0, size);
1862
1863 /* round up to nearest 4K */
1864 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1865 tx_ring->size = ALIGN(tx_ring->size, 4096);
1866
1867 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1868 &tx_ring->dma);
1869
1870 if (!tx_ring->desc)
1871 goto err;
1872
1873 tx_ring->adapter = adapter;
1874 tx_ring->next_to_use = 0;
1875 tx_ring->next_to_clean = 0;
1876 return 0;
1877
1878 err:
1879 vfree(tx_ring->buffer_info);
1880 dev_err(&adapter->pdev->dev,
1881 "Unable to allocate memory for the transmit descriptor ring\n");
1882 return -ENOMEM;
1883 }
1884
1885 /**
1886 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1887 * (Descriptors) for all queues
1888 * @adapter: board private structure
1889 *
1890 * Return 0 on success, negative on failure
1891 **/
1892 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1893 {
1894 int i, err = 0;
1895 int r_idx;
1896
1897 for (i = 0; i < adapter->num_tx_queues; i++) {
1898 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1899 if (err) {
1900 dev_err(&adapter->pdev->dev,
1901 "Allocation for Tx Queue %u failed\n", i);
1902 for (i--; i >= 0; i--)
1903 igb_free_tx_resources(&adapter->tx_ring[i]);
1904 break;
1905 }
1906 }
1907
1908 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1909 r_idx = i % adapter->num_tx_queues;
1910 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1911 }
1912 return err;
1913 }
1914
1915 /**
1916 * igb_configure_tx - Configure transmit Unit after Reset
1917 * @adapter: board private structure
1918 *
1919 * Configure the Tx unit of the MAC after a reset.
1920 **/
1921 static void igb_configure_tx(struct igb_adapter *adapter)
1922 {
1923 u64 tdba;
1924 struct e1000_hw *hw = &adapter->hw;
1925 u32 tctl;
1926 u32 txdctl, txctrl;
1927 int i, j;
1928
1929 for (i = 0; i < adapter->num_tx_queues; i++) {
1930 struct igb_ring *ring = &adapter->tx_ring[i];
1931 j = ring->reg_idx;
1932 wr32(E1000_TDLEN(j),
1933 ring->count * sizeof(union e1000_adv_tx_desc));
1934 tdba = ring->dma;
1935 wr32(E1000_TDBAL(j),
1936 tdba & 0x00000000ffffffffULL);
1937 wr32(E1000_TDBAH(j), tdba >> 32);
1938
1939 ring->head = E1000_TDH(j);
1940 ring->tail = E1000_TDT(j);
1941 writel(0, hw->hw_addr + ring->tail);
1942 writel(0, hw->hw_addr + ring->head);
1943 txdctl = rd32(E1000_TXDCTL(j));
1944 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1945 wr32(E1000_TXDCTL(j), txdctl);
1946
1947 /* Turn off Relaxed Ordering on head write-backs. The
1948 * writebacks MUST be delivered in order or it will
1949 * completely screw up our bookeeping.
1950 */
1951 txctrl = rd32(E1000_DCA_TXCTRL(j));
1952 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1953 wr32(E1000_DCA_TXCTRL(j), txctrl);
1954 }
1955
1956 /* disable queue 0 to prevent tail bump w/o re-configuration */
1957 if (adapter->vfs_allocated_count)
1958 wr32(E1000_TXDCTL(0), 0);
1959
1960 /* Program the Transmit Control Register */
1961 tctl = rd32(E1000_TCTL);
1962 tctl &= ~E1000_TCTL_CT;
1963 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1964 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1965
1966 igb_config_collision_dist(hw);
1967
1968 /* Setup Transmit Descriptor Settings for eop descriptor */
1969 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1970
1971 /* Enable transmits */
1972 tctl |= E1000_TCTL_EN;
1973
1974 wr32(E1000_TCTL, tctl);
1975 }
1976
1977 /**
1978 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1979 * @adapter: board private structure
1980 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1981 *
1982 * Returns 0 on success, negative on failure
1983 **/
1984 int igb_setup_rx_resources(struct igb_adapter *adapter,
1985 struct igb_ring *rx_ring)
1986 {
1987 struct pci_dev *pdev = adapter->pdev;
1988 int size, desc_len;
1989
1990 size = sizeof(struct igb_buffer) * rx_ring->count;
1991 rx_ring->buffer_info = vmalloc(size);
1992 if (!rx_ring->buffer_info)
1993 goto err;
1994 memset(rx_ring->buffer_info, 0, size);
1995
1996 desc_len = sizeof(union e1000_adv_rx_desc);
1997
1998 /* Round up to nearest 4K */
1999 rx_ring->size = rx_ring->count * desc_len;
2000 rx_ring->size = ALIGN(rx_ring->size, 4096);
2001
2002 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2003 &rx_ring->dma);
2004
2005 if (!rx_ring->desc)
2006 goto err;
2007
2008 rx_ring->next_to_clean = 0;
2009 rx_ring->next_to_use = 0;
2010
2011 rx_ring->adapter = adapter;
2012
2013 return 0;
2014
2015 err:
2016 vfree(rx_ring->buffer_info);
2017 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2018 "the receive descriptor ring\n");
2019 return -ENOMEM;
2020 }
2021
2022 /**
2023 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2024 * (Descriptors) for all queues
2025 * @adapter: board private structure
2026 *
2027 * Return 0 on success, negative on failure
2028 **/
2029 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2030 {
2031 int i, err = 0;
2032
2033 for (i = 0; i < adapter->num_rx_queues; i++) {
2034 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2035 if (err) {
2036 dev_err(&adapter->pdev->dev,
2037 "Allocation for Rx Queue %u failed\n", i);
2038 for (i--; i >= 0; i--)
2039 igb_free_rx_resources(&adapter->rx_ring[i]);
2040 break;
2041 }
2042 }
2043
2044 return err;
2045 }
2046
2047 /**
2048 * igb_setup_rctl - configure the receive control registers
2049 * @adapter: Board private structure
2050 **/
2051 static void igb_setup_rctl(struct igb_adapter *adapter)
2052 {
2053 struct e1000_hw *hw = &adapter->hw;
2054 u32 rctl;
2055 u32 srrctl = 0;
2056 int i;
2057
2058 rctl = rd32(E1000_RCTL);
2059
2060 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2061 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2062
2063 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2064 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2065
2066 /*
2067 * enable stripping of CRC. It's unlikely this will break BMC
2068 * redirection as it did with e1000. Newer features require
2069 * that the HW strips the CRC.
2070 */
2071 rctl |= E1000_RCTL_SECRC;
2072
2073 /*
2074 * disable store bad packets and clear size bits.
2075 */
2076 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2077
2078 /* enable LPE when to prevent packets larger than max_frame_size */
2079 rctl |= E1000_RCTL_LPE;
2080
2081 /* Setup buffer sizes */
2082 switch (adapter->rx_buffer_len) {
2083 case IGB_RXBUFFER_256:
2084 rctl |= E1000_RCTL_SZ_256;
2085 break;
2086 case IGB_RXBUFFER_512:
2087 rctl |= E1000_RCTL_SZ_512;
2088 break;
2089 default:
2090 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2091 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2092 break;
2093 }
2094
2095 /* 82575 and greater support packet-split where the protocol
2096 * header is placed in skb->data and the packet data is
2097 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2098 * In the case of a non-split, skb->data is linearly filled,
2099 * followed by the page buffers. Therefore, skb->data is
2100 * sized to hold the largest protocol header.
2101 */
2102 /* allocations using alloc_page take too long for regular MTU
2103 * so only enable packet split for jumbo frames */
2104 if (adapter->netdev->mtu > ETH_DATA_LEN) {
2105 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2106 srrctl |= adapter->rx_ps_hdr_size <<
2107 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2108 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2109 } else {
2110 adapter->rx_ps_hdr_size = 0;
2111 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2112 }
2113
2114 /* Attention!!! For SR-IOV PF driver operations you must enable
2115 * queue drop for all VF and PF queues to prevent head of line blocking
2116 * if an un-trusted VF does not provide descriptors to hardware.
2117 */
2118 if (adapter->vfs_allocated_count) {
2119 u32 vmolr;
2120
2121 /* set all queue drop enable bits */
2122 wr32(E1000_QDE, ALL_QUEUES);
2123 srrctl |= E1000_SRRCTL_DROP_EN;
2124
2125 /* disable queue 0 to prevent tail write w/o re-config */
2126 wr32(E1000_RXDCTL(0), 0);
2127
2128 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2129 if (rctl & E1000_RCTL_LPE)
2130 vmolr |= E1000_VMOLR_LPE;
2131 if (adapter->num_rx_queues > 1)
2132 vmolr |= E1000_VMOLR_RSSE;
2133 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2134 }
2135
2136 for (i = 0; i < adapter->num_rx_queues; i++) {
2137 int j = adapter->rx_ring[i].reg_idx;
2138 wr32(E1000_SRRCTL(j), srrctl);
2139 }
2140
2141 wr32(E1000_RCTL, rctl);
2142 }
2143
2144 /**
2145 * igb_rlpml_set - set maximum receive packet size
2146 * @adapter: board private structure
2147 *
2148 * Configure maximum receivable packet size.
2149 **/
2150 static void igb_rlpml_set(struct igb_adapter *adapter)
2151 {
2152 u32 max_frame_size = adapter->max_frame_size;
2153 struct e1000_hw *hw = &adapter->hw;
2154 u16 pf_id = adapter->vfs_allocated_count;
2155
2156 if (adapter->vlgrp)
2157 max_frame_size += VLAN_TAG_SIZE;
2158
2159 /* if vfs are enabled we set RLPML to the largest possible request
2160 * size and set the VMOLR RLPML to the size we need */
2161 if (pf_id) {
2162 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2163 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2164 }
2165
2166 wr32(E1000_RLPML, max_frame_size);
2167 }
2168
2169 /**
2170 * igb_configure_vt_default_pool - Configure VT default pool
2171 * @adapter: board private structure
2172 *
2173 * Configure the default pool
2174 **/
2175 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2176 {
2177 struct e1000_hw *hw = &adapter->hw;
2178 u16 pf_id = adapter->vfs_allocated_count;
2179 u32 vtctl;
2180
2181 /* not in sr-iov mode - do nothing */
2182 if (!pf_id)
2183 return;
2184
2185 vtctl = rd32(E1000_VT_CTL);
2186 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2187 E1000_VT_CTL_DISABLE_DEF_POOL);
2188 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2189 wr32(E1000_VT_CTL, vtctl);
2190 }
2191
2192 /**
2193 * igb_configure_rx - Configure receive Unit after Reset
2194 * @adapter: board private structure
2195 *
2196 * Configure the Rx unit of the MAC after a reset.
2197 **/
2198 static void igb_configure_rx(struct igb_adapter *adapter)
2199 {
2200 u64 rdba;
2201 struct e1000_hw *hw = &adapter->hw;
2202 u32 rctl, rxcsum;
2203 u32 rxdctl;
2204 int i;
2205
2206 /* disable receives while setting up the descriptors */
2207 rctl = rd32(E1000_RCTL);
2208 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2209 wrfl();
2210 mdelay(10);
2211
2212 if (adapter->itr_setting > 3)
2213 wr32(E1000_ITR, adapter->itr);
2214
2215 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2216 * the Base and Length of the Rx Descriptor Ring */
2217 for (i = 0; i < adapter->num_rx_queues; i++) {
2218 struct igb_ring *ring = &adapter->rx_ring[i];
2219 int j = ring->reg_idx;
2220 rdba = ring->dma;
2221 wr32(E1000_RDBAL(j),
2222 rdba & 0x00000000ffffffffULL);
2223 wr32(E1000_RDBAH(j), rdba >> 32);
2224 wr32(E1000_RDLEN(j),
2225 ring->count * sizeof(union e1000_adv_rx_desc));
2226
2227 ring->head = E1000_RDH(j);
2228 ring->tail = E1000_RDT(j);
2229 writel(0, hw->hw_addr + ring->tail);
2230 writel(0, hw->hw_addr + ring->head);
2231
2232 rxdctl = rd32(E1000_RXDCTL(j));
2233 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2234 rxdctl &= 0xFFF00000;
2235 rxdctl |= IGB_RX_PTHRESH;
2236 rxdctl |= IGB_RX_HTHRESH << 8;
2237 rxdctl |= IGB_RX_WTHRESH << 16;
2238 wr32(E1000_RXDCTL(j), rxdctl);
2239 }
2240
2241 if (adapter->num_rx_queues > 1) {
2242 u32 random[10];
2243 u32 mrqc;
2244 u32 j, shift;
2245 union e1000_reta {
2246 u32 dword;
2247 u8 bytes[4];
2248 } reta;
2249
2250 get_random_bytes(&random[0], 40);
2251
2252 if (hw->mac.type >= e1000_82576)
2253 shift = 0;
2254 else
2255 shift = 6;
2256 for (j = 0; j < (32 * 4); j++) {
2257 reta.bytes[j & 3] =
2258 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2259 if ((j & 3) == 3)
2260 writel(reta.dword,
2261 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2262 }
2263 if (adapter->vfs_allocated_count)
2264 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2265 else
2266 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2267
2268 /* Fill out hash function seeds */
2269 for (j = 0; j < 10; j++)
2270 array_wr32(E1000_RSSRK(0), j, random[j]);
2271
2272 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2273 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2274 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2275 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2276 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2277 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2278 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2279 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2280
2281 wr32(E1000_MRQC, mrqc);
2282 } else if (adapter->vfs_allocated_count) {
2283 /* Enable multi-queue for sr-iov */
2284 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2285 }
2286
2287 /* Enable Receive Checksum Offload for TCP and UDP */
2288 rxcsum = rd32(E1000_RXCSUM);
2289 /* Disable raw packet checksumming */
2290 rxcsum |= E1000_RXCSUM_PCSD;
2291
2292 if (adapter->hw.mac.type == e1000_82576)
2293 /* Enable Receive Checksum Offload for SCTP */
2294 rxcsum |= E1000_RXCSUM_CRCOFL;
2295
2296 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2297 wr32(E1000_RXCSUM, rxcsum);
2298
2299 /* Set the default pool for the PF's first queue */
2300 igb_configure_vt_default_pool(adapter);
2301
2302 igb_rlpml_set(adapter);
2303
2304 /* Enable Receives */
2305 wr32(E1000_RCTL, rctl);
2306 }
2307
2308 /**
2309 * igb_free_tx_resources - Free Tx Resources per Queue
2310 * @tx_ring: Tx descriptor ring for a specific queue
2311 *
2312 * Free all transmit software resources
2313 **/
2314 void igb_free_tx_resources(struct igb_ring *tx_ring)
2315 {
2316 struct pci_dev *pdev = tx_ring->adapter->pdev;
2317
2318 igb_clean_tx_ring(tx_ring);
2319
2320 vfree(tx_ring->buffer_info);
2321 tx_ring->buffer_info = NULL;
2322
2323 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2324
2325 tx_ring->desc = NULL;
2326 }
2327
2328 /**
2329 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2330 * @adapter: board private structure
2331 *
2332 * Free all transmit software resources
2333 **/
2334 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2335 {
2336 int i;
2337
2338 for (i = 0; i < adapter->num_tx_queues; i++)
2339 igb_free_tx_resources(&adapter->tx_ring[i]);
2340 }
2341
2342 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2343 struct igb_buffer *buffer_info)
2344 {
2345 buffer_info->dma = 0;
2346 if (buffer_info->skb) {
2347 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2348 DMA_TO_DEVICE);
2349 dev_kfree_skb_any(buffer_info->skb);
2350 buffer_info->skb = NULL;
2351 }
2352 buffer_info->time_stamp = 0;
2353 /* buffer_info must be completely set up in the transmit path */
2354 }
2355
2356 /**
2357 * igb_clean_tx_ring - Free Tx Buffers
2358 * @tx_ring: ring to be cleaned
2359 **/
2360 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2361 {
2362 struct igb_adapter *adapter = tx_ring->adapter;
2363 struct igb_buffer *buffer_info;
2364 unsigned long size;
2365 unsigned int i;
2366
2367 if (!tx_ring->buffer_info)
2368 return;
2369 /* Free all the Tx ring sk_buffs */
2370
2371 for (i = 0; i < tx_ring->count; i++) {
2372 buffer_info = &tx_ring->buffer_info[i];
2373 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2374 }
2375
2376 size = sizeof(struct igb_buffer) * tx_ring->count;
2377 memset(tx_ring->buffer_info, 0, size);
2378
2379 /* Zero out the descriptor ring */
2380
2381 memset(tx_ring->desc, 0, tx_ring->size);
2382
2383 tx_ring->next_to_use = 0;
2384 tx_ring->next_to_clean = 0;
2385
2386 writel(0, adapter->hw.hw_addr + tx_ring->head);
2387 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2388 }
2389
2390 /**
2391 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2392 * @adapter: board private structure
2393 **/
2394 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2395 {
2396 int i;
2397
2398 for (i = 0; i < adapter->num_tx_queues; i++)
2399 igb_clean_tx_ring(&adapter->tx_ring[i]);
2400 }
2401
2402 /**
2403 * igb_free_rx_resources - Free Rx Resources
2404 * @rx_ring: ring to clean the resources from
2405 *
2406 * Free all receive software resources
2407 **/
2408 void igb_free_rx_resources(struct igb_ring *rx_ring)
2409 {
2410 struct pci_dev *pdev = rx_ring->adapter->pdev;
2411
2412 igb_clean_rx_ring(rx_ring);
2413
2414 vfree(rx_ring->buffer_info);
2415 rx_ring->buffer_info = NULL;
2416
2417 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2418
2419 rx_ring->desc = NULL;
2420 }
2421
2422 /**
2423 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2424 * @adapter: board private structure
2425 *
2426 * Free all receive software resources
2427 **/
2428 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2429 {
2430 int i;
2431
2432 for (i = 0; i < adapter->num_rx_queues; i++)
2433 igb_free_rx_resources(&adapter->rx_ring[i]);
2434 }
2435
2436 /**
2437 * igb_clean_rx_ring - Free Rx Buffers per Queue
2438 * @rx_ring: ring to free buffers from
2439 **/
2440 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2441 {
2442 struct igb_adapter *adapter = rx_ring->adapter;
2443 struct igb_buffer *buffer_info;
2444 struct pci_dev *pdev = adapter->pdev;
2445 unsigned long size;
2446 unsigned int i;
2447
2448 if (!rx_ring->buffer_info)
2449 return;
2450 /* Free all the Rx ring sk_buffs */
2451 for (i = 0; i < rx_ring->count; i++) {
2452 buffer_info = &rx_ring->buffer_info[i];
2453 if (buffer_info->dma) {
2454 if (adapter->rx_ps_hdr_size)
2455 pci_unmap_single(pdev, buffer_info->dma,
2456 adapter->rx_ps_hdr_size,
2457 PCI_DMA_FROMDEVICE);
2458 else
2459 pci_unmap_single(pdev, buffer_info->dma,
2460 adapter->rx_buffer_len,
2461 PCI_DMA_FROMDEVICE);
2462 buffer_info->dma = 0;
2463 }
2464
2465 if (buffer_info->skb) {
2466 dev_kfree_skb(buffer_info->skb);
2467 buffer_info->skb = NULL;
2468 }
2469 if (buffer_info->page) {
2470 if (buffer_info->page_dma)
2471 pci_unmap_page(pdev, buffer_info->page_dma,
2472 PAGE_SIZE / 2,
2473 PCI_DMA_FROMDEVICE);
2474 put_page(buffer_info->page);
2475 buffer_info->page = NULL;
2476 buffer_info->page_dma = 0;
2477 buffer_info->page_offset = 0;
2478 }
2479 }
2480
2481 size = sizeof(struct igb_buffer) * rx_ring->count;
2482 memset(rx_ring->buffer_info, 0, size);
2483
2484 /* Zero out the descriptor ring */
2485 memset(rx_ring->desc, 0, rx_ring->size);
2486
2487 rx_ring->next_to_clean = 0;
2488 rx_ring->next_to_use = 0;
2489
2490 writel(0, adapter->hw.hw_addr + rx_ring->head);
2491 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2492 }
2493
2494 /**
2495 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2496 * @adapter: board private structure
2497 **/
2498 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2499 {
2500 int i;
2501
2502 for (i = 0; i < adapter->num_rx_queues; i++)
2503 igb_clean_rx_ring(&adapter->rx_ring[i]);
2504 }
2505
2506 /**
2507 * igb_set_mac - Change the Ethernet Address of the NIC
2508 * @netdev: network interface device structure
2509 * @p: pointer to an address structure
2510 *
2511 * Returns 0 on success, negative on failure
2512 **/
2513 static int igb_set_mac(struct net_device *netdev, void *p)
2514 {
2515 struct igb_adapter *adapter = netdev_priv(netdev);
2516 struct e1000_hw *hw = &adapter->hw;
2517 struct sockaddr *addr = p;
2518
2519 if (!is_valid_ether_addr(addr->sa_data))
2520 return -EADDRNOTAVAIL;
2521
2522 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2523 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2524
2525 igb_rar_set(hw, hw->mac.addr, 0);
2526 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2527
2528 return 0;
2529 }
2530
2531 /**
2532 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2533 * @netdev: network interface device structure
2534 *
2535 * The set_rx_mode entry point is called whenever the unicast or multicast
2536 * address lists or the network interface flags are updated. This routine is
2537 * responsible for configuring the hardware for proper unicast, multicast,
2538 * promiscuous mode, and all-multi behavior.
2539 **/
2540 static void igb_set_rx_mode(struct net_device *netdev)
2541 {
2542 struct igb_adapter *adapter = netdev_priv(netdev);
2543 struct e1000_hw *hw = &adapter->hw;
2544 unsigned int rar_entries = hw->mac.rar_entry_count -
2545 (adapter->vfs_allocated_count + 1);
2546 struct dev_mc_list *mc_ptr = netdev->mc_list;
2547 u8 *mta_list = NULL;
2548 u32 rctl;
2549 int i;
2550
2551 /* Check for Promiscuous and All Multicast modes */
2552 rctl = rd32(E1000_RCTL);
2553
2554 if (netdev->flags & IFF_PROMISC) {
2555 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2556 rctl &= ~E1000_RCTL_VFE;
2557 } else {
2558 if (netdev->flags & IFF_ALLMULTI)
2559 rctl |= E1000_RCTL_MPE;
2560 else
2561 rctl &= ~E1000_RCTL_MPE;
2562
2563 if (netdev->uc.count > rar_entries)
2564 rctl |= E1000_RCTL_UPE;
2565 else
2566 rctl &= ~E1000_RCTL_UPE;
2567 rctl |= E1000_RCTL_VFE;
2568 }
2569 wr32(E1000_RCTL, rctl);
2570
2571 if (netdev->uc.count && rar_entries) {
2572 struct netdev_hw_addr *ha;
2573 list_for_each_entry(ha, &netdev->uc.list, list) {
2574 if (!rar_entries)
2575 break;
2576 igb_rar_set(hw, ha->addr, rar_entries);
2577 igb_set_rah_pool(hw, adapter->vfs_allocated_count,
2578 rar_entries);
2579 rar_entries--;
2580 }
2581 }
2582 /* write the addresses in reverse order to avoid write combining */
2583 for (; rar_entries > 0 ; rar_entries--) {
2584 wr32(E1000_RAH(rar_entries), 0);
2585 wr32(E1000_RAL(rar_entries), 0);
2586 }
2587 wrfl();
2588
2589 if (!netdev->mc_count) {
2590 /* nothing to program, so clear mc list */
2591 igb_update_mc_addr_list(hw, NULL, 0);
2592 igb_restore_vf_multicasts(adapter);
2593 return;
2594 }
2595
2596 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2597 if (!mta_list) {
2598 dev_err(&adapter->pdev->dev,
2599 "failed to allocate multicast filter list\n");
2600 return;
2601 }
2602
2603 /* The shared function expects a packed array of only addresses. */
2604 for (i = 0; i < netdev->mc_count; i++) {
2605 if (!mc_ptr)
2606 break;
2607 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2608 mc_ptr = mc_ptr->next;
2609 }
2610 igb_update_mc_addr_list(hw, mta_list, i);
2611 kfree(mta_list);
2612 igb_restore_vf_multicasts(adapter);
2613 }
2614
2615 /* Need to wait a few seconds after link up to get diagnostic information from
2616 * the phy */
2617 static void igb_update_phy_info(unsigned long data)
2618 {
2619 struct igb_adapter *adapter = (struct igb_adapter *) data;
2620 igb_get_phy_info(&adapter->hw);
2621 }
2622
2623 /**
2624 * igb_has_link - check shared code for link and determine up/down
2625 * @adapter: pointer to driver private info
2626 **/
2627 static bool igb_has_link(struct igb_adapter *adapter)
2628 {
2629 struct e1000_hw *hw = &adapter->hw;
2630 bool link_active = false;
2631 s32 ret_val = 0;
2632
2633 /* get_link_status is set on LSC (link status) interrupt or
2634 * rx sequence error interrupt. get_link_status will stay
2635 * false until the e1000_check_for_link establishes link
2636 * for copper adapters ONLY
2637 */
2638 switch (hw->phy.media_type) {
2639 case e1000_media_type_copper:
2640 if (hw->mac.get_link_status) {
2641 ret_val = hw->mac.ops.check_for_link(hw);
2642 link_active = !hw->mac.get_link_status;
2643 } else {
2644 link_active = true;
2645 }
2646 break;
2647 case e1000_media_type_internal_serdes:
2648 ret_val = hw->mac.ops.check_for_link(hw);
2649 link_active = hw->mac.serdes_has_link;
2650 break;
2651 default:
2652 case e1000_media_type_unknown:
2653 break;
2654 }
2655
2656 return link_active;
2657 }
2658
2659 /**
2660 * igb_watchdog - Timer Call-back
2661 * @data: pointer to adapter cast into an unsigned long
2662 **/
2663 static void igb_watchdog(unsigned long data)
2664 {
2665 struct igb_adapter *adapter = (struct igb_adapter *)data;
2666 /* Do the rest outside of interrupt context */
2667 schedule_work(&adapter->watchdog_task);
2668 }
2669
2670 static void igb_watchdog_task(struct work_struct *work)
2671 {
2672 struct igb_adapter *adapter = container_of(work,
2673 struct igb_adapter, watchdog_task);
2674 struct e1000_hw *hw = &adapter->hw;
2675 struct net_device *netdev = adapter->netdev;
2676 struct igb_ring *tx_ring = adapter->tx_ring;
2677 u32 link;
2678 u32 eics = 0;
2679 int i;
2680
2681 link = igb_has_link(adapter);
2682 if ((netif_carrier_ok(netdev)) && link)
2683 goto link_up;
2684
2685 if (link) {
2686 if (!netif_carrier_ok(netdev)) {
2687 u32 ctrl;
2688 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2689 &adapter->link_speed,
2690 &adapter->link_duplex);
2691
2692 ctrl = rd32(E1000_CTRL);
2693 /* Links status message must follow this format */
2694 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2695 "Flow Control: %s\n",
2696 netdev->name,
2697 adapter->link_speed,
2698 adapter->link_duplex == FULL_DUPLEX ?
2699 "Full Duplex" : "Half Duplex",
2700 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2701 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2702 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2703 E1000_CTRL_TFCE) ? "TX" : "None")));
2704
2705 /* tweak tx_queue_len according to speed/duplex and
2706 * adjust the timeout factor */
2707 netdev->tx_queue_len = adapter->tx_queue_len;
2708 adapter->tx_timeout_factor = 1;
2709 switch (adapter->link_speed) {
2710 case SPEED_10:
2711 netdev->tx_queue_len = 10;
2712 adapter->tx_timeout_factor = 14;
2713 break;
2714 case SPEED_100:
2715 netdev->tx_queue_len = 100;
2716 /* maybe add some timeout factor ? */
2717 break;
2718 }
2719
2720 netif_carrier_on(netdev);
2721
2722 igb_ping_all_vfs(adapter);
2723
2724 /* link state has changed, schedule phy info update */
2725 if (!test_bit(__IGB_DOWN, &adapter->state))
2726 mod_timer(&adapter->phy_info_timer,
2727 round_jiffies(jiffies + 2 * HZ));
2728 }
2729 } else {
2730 if (netif_carrier_ok(netdev)) {
2731 adapter->link_speed = 0;
2732 adapter->link_duplex = 0;
2733 /* Links status message must follow this format */
2734 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2735 netdev->name);
2736 netif_carrier_off(netdev);
2737
2738 igb_ping_all_vfs(adapter);
2739
2740 /* link state has changed, schedule phy info update */
2741 if (!test_bit(__IGB_DOWN, &adapter->state))
2742 mod_timer(&adapter->phy_info_timer,
2743 round_jiffies(jiffies + 2 * HZ));
2744 }
2745 }
2746
2747 link_up:
2748 igb_update_stats(adapter);
2749
2750 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2751 adapter->tpt_old = adapter->stats.tpt;
2752 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2753 adapter->colc_old = adapter->stats.colc;
2754
2755 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2756 adapter->gorc_old = adapter->stats.gorc;
2757 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2758 adapter->gotc_old = adapter->stats.gotc;
2759
2760 igb_update_adaptive(&adapter->hw);
2761
2762 if (!netif_carrier_ok(netdev)) {
2763 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2764 /* We've lost link, so the controller stops DMA,
2765 * but we've got queued Tx work that's never going
2766 * to get done, so reset controller to flush Tx.
2767 * (Do the reset outside of interrupt context). */
2768 adapter->tx_timeout_count++;
2769 schedule_work(&adapter->reset_task);
2770 /* return immediately since reset is imminent */
2771 return;
2772 }
2773 }
2774
2775 /* Cause software interrupt to ensure rx ring is cleaned */
2776 if (adapter->msix_entries) {
2777 for (i = 0; i < adapter->num_rx_queues; i++)
2778 eics |= adapter->rx_ring[i].eims_value;
2779 wr32(E1000_EICS, eics);
2780 } else {
2781 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2782 }
2783
2784 /* Force detection of hung controller every watchdog period */
2785 tx_ring->detect_tx_hung = true;
2786
2787 /* Reset the timer */
2788 if (!test_bit(__IGB_DOWN, &adapter->state))
2789 mod_timer(&adapter->watchdog_timer,
2790 round_jiffies(jiffies + 2 * HZ));
2791 }
2792
2793 enum latency_range {
2794 lowest_latency = 0,
2795 low_latency = 1,
2796 bulk_latency = 2,
2797 latency_invalid = 255
2798 };
2799
2800
2801 /**
2802 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2803 *
2804 * Stores a new ITR value based on strictly on packet size. This
2805 * algorithm is less sophisticated than that used in igb_update_itr,
2806 * due to the difficulty of synchronizing statistics across multiple
2807 * receive rings. The divisors and thresholds used by this fuction
2808 * were determined based on theoretical maximum wire speed and testing
2809 * data, in order to minimize response time while increasing bulk
2810 * throughput.
2811 * This functionality is controlled by the InterruptThrottleRate module
2812 * parameter (see igb_param.c)
2813 * NOTE: This function is called only when operating in a multiqueue
2814 * receive environment.
2815 * @rx_ring: pointer to ring
2816 **/
2817 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2818 {
2819 int new_val = rx_ring->itr_val;
2820 int avg_wire_size = 0;
2821 struct igb_adapter *adapter = rx_ring->adapter;
2822
2823 if (!rx_ring->total_packets)
2824 goto clear_counts; /* no packets, so don't do anything */
2825
2826 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2827 * ints/sec - ITR timer value of 120 ticks.
2828 */
2829 if (adapter->link_speed != SPEED_1000) {
2830 new_val = 120;
2831 goto set_itr_val;
2832 }
2833 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2834
2835 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2836 avg_wire_size += 24;
2837
2838 /* Don't starve jumbo frames */
2839 avg_wire_size = min(avg_wire_size, 3000);
2840
2841 /* Give a little boost to mid-size frames */
2842 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2843 new_val = avg_wire_size / 3;
2844 else
2845 new_val = avg_wire_size / 2;
2846
2847 set_itr_val:
2848 if (new_val != rx_ring->itr_val) {
2849 rx_ring->itr_val = new_val;
2850 rx_ring->set_itr = 1;
2851 }
2852 clear_counts:
2853 rx_ring->total_bytes = 0;
2854 rx_ring->total_packets = 0;
2855 }
2856
2857 /**
2858 * igb_update_itr - update the dynamic ITR value based on statistics
2859 * Stores a new ITR value based on packets and byte
2860 * counts during the last interrupt. The advantage of per interrupt
2861 * computation is faster updates and more accurate ITR for the current
2862 * traffic pattern. Constants in this function were computed
2863 * based on theoretical maximum wire speed and thresholds were set based
2864 * on testing data as well as attempting to minimize response time
2865 * while increasing bulk throughput.
2866 * this functionality is controlled by the InterruptThrottleRate module
2867 * parameter (see igb_param.c)
2868 * NOTE: These calculations are only valid when operating in a single-
2869 * queue environment.
2870 * @adapter: pointer to adapter
2871 * @itr_setting: current adapter->itr
2872 * @packets: the number of packets during this measurement interval
2873 * @bytes: the number of bytes during this measurement interval
2874 **/
2875 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2876 int packets, int bytes)
2877 {
2878 unsigned int retval = itr_setting;
2879
2880 if (packets == 0)
2881 goto update_itr_done;
2882
2883 switch (itr_setting) {
2884 case lowest_latency:
2885 /* handle TSO and jumbo frames */
2886 if (bytes/packets > 8000)
2887 retval = bulk_latency;
2888 else if ((packets < 5) && (bytes > 512))
2889 retval = low_latency;
2890 break;
2891 case low_latency: /* 50 usec aka 20000 ints/s */
2892 if (bytes > 10000) {
2893 /* this if handles the TSO accounting */
2894 if (bytes/packets > 8000) {
2895 retval = bulk_latency;
2896 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2897 retval = bulk_latency;
2898 } else if ((packets > 35)) {
2899 retval = lowest_latency;
2900 }
2901 } else if (bytes/packets > 2000) {
2902 retval = bulk_latency;
2903 } else if (packets <= 2 && bytes < 512) {
2904 retval = lowest_latency;
2905 }
2906 break;
2907 case bulk_latency: /* 250 usec aka 4000 ints/s */
2908 if (bytes > 25000) {
2909 if (packets > 35)
2910 retval = low_latency;
2911 } else if (bytes < 1500) {
2912 retval = low_latency;
2913 }
2914 break;
2915 }
2916
2917 update_itr_done:
2918 return retval;
2919 }
2920
2921 static void igb_set_itr(struct igb_adapter *adapter)
2922 {
2923 u16 current_itr;
2924 u32 new_itr = adapter->itr;
2925
2926 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2927 if (adapter->link_speed != SPEED_1000) {
2928 current_itr = 0;
2929 new_itr = 4000;
2930 goto set_itr_now;
2931 }
2932
2933 adapter->rx_itr = igb_update_itr(adapter,
2934 adapter->rx_itr,
2935 adapter->rx_ring->total_packets,
2936 adapter->rx_ring->total_bytes);
2937
2938 if (adapter->rx_ring->buddy) {
2939 adapter->tx_itr = igb_update_itr(adapter,
2940 adapter->tx_itr,
2941 adapter->tx_ring->total_packets,
2942 adapter->tx_ring->total_bytes);
2943 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2944 } else {
2945 current_itr = adapter->rx_itr;
2946 }
2947
2948 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2949 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2950 current_itr = low_latency;
2951
2952 switch (current_itr) {
2953 /* counts and packets in update_itr are dependent on these numbers */
2954 case lowest_latency:
2955 new_itr = 56; /* aka 70,000 ints/sec */
2956 break;
2957 case low_latency:
2958 new_itr = 196; /* aka 20,000 ints/sec */
2959 break;
2960 case bulk_latency:
2961 new_itr = 980; /* aka 4,000 ints/sec */
2962 break;
2963 default:
2964 break;
2965 }
2966
2967 set_itr_now:
2968 adapter->rx_ring->total_bytes = 0;
2969 adapter->rx_ring->total_packets = 0;
2970 if (adapter->rx_ring->buddy) {
2971 adapter->rx_ring->buddy->total_bytes = 0;
2972 adapter->rx_ring->buddy->total_packets = 0;
2973 }
2974
2975 if (new_itr != adapter->itr) {
2976 /* this attempts to bias the interrupt rate towards Bulk
2977 * by adding intermediate steps when interrupt rate is
2978 * increasing */
2979 new_itr = new_itr > adapter->itr ?
2980 max((new_itr * adapter->itr) /
2981 (new_itr + (adapter->itr >> 2)), new_itr) :
2982 new_itr;
2983 /* Don't write the value here; it resets the adapter's
2984 * internal timer, and causes us to delay far longer than
2985 * we should between interrupts. Instead, we write the ITR
2986 * value at the beginning of the next interrupt so the timing
2987 * ends up being correct.
2988 */
2989 adapter->itr = new_itr;
2990 adapter->rx_ring->itr_val = new_itr;
2991 adapter->rx_ring->set_itr = 1;
2992 }
2993
2994 return;
2995 }
2996
2997
2998 #define IGB_TX_FLAGS_CSUM 0x00000001
2999 #define IGB_TX_FLAGS_VLAN 0x00000002
3000 #define IGB_TX_FLAGS_TSO 0x00000004
3001 #define IGB_TX_FLAGS_IPV4 0x00000008
3002 #define IGB_TX_FLAGS_TSTAMP 0x00000010
3003 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3004 #define IGB_TX_FLAGS_VLAN_SHIFT 16
3005
3006 static inline int igb_tso_adv(struct igb_adapter *adapter,
3007 struct igb_ring *tx_ring,
3008 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3009 {
3010 struct e1000_adv_tx_context_desc *context_desc;
3011 unsigned int i;
3012 int err;
3013 struct igb_buffer *buffer_info;
3014 u32 info = 0, tu_cmd = 0;
3015 u32 mss_l4len_idx, l4len;
3016 *hdr_len = 0;
3017
3018 if (skb_header_cloned(skb)) {
3019 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3020 if (err)
3021 return err;
3022 }
3023
3024 l4len = tcp_hdrlen(skb);
3025 *hdr_len += l4len;
3026
3027 if (skb->protocol == htons(ETH_P_IP)) {
3028 struct iphdr *iph = ip_hdr(skb);
3029 iph->tot_len = 0;
3030 iph->check = 0;
3031 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3032 iph->daddr, 0,
3033 IPPROTO_TCP,
3034 0);
3035 } else if (skb_is_gso_v6(skb)) {
3036 ipv6_hdr(skb)->payload_len = 0;
3037 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3038 &ipv6_hdr(skb)->daddr,
3039 0, IPPROTO_TCP, 0);
3040 }
3041
3042 i = tx_ring->next_to_use;
3043
3044 buffer_info = &tx_ring->buffer_info[i];
3045 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3046 /* VLAN MACLEN IPLEN */
3047 if (tx_flags & IGB_TX_FLAGS_VLAN)
3048 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3049 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3050 *hdr_len += skb_network_offset(skb);
3051 info |= skb_network_header_len(skb);
3052 *hdr_len += skb_network_header_len(skb);
3053 context_desc->vlan_macip_lens = cpu_to_le32(info);
3054
3055 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3056 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3057
3058 if (skb->protocol == htons(ETH_P_IP))
3059 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3060 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3061
3062 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3063
3064 /* MSS L4LEN IDX */
3065 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3066 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3067
3068 /* For 82575, context index must be unique per ring. */
3069 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3070 mss_l4len_idx |= tx_ring->queue_index << 4;
3071
3072 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3073 context_desc->seqnum_seed = 0;
3074
3075 buffer_info->time_stamp = jiffies;
3076 buffer_info->next_to_watch = i;
3077 buffer_info->dma = 0;
3078 i++;
3079 if (i == tx_ring->count)
3080 i = 0;
3081
3082 tx_ring->next_to_use = i;
3083
3084 return true;
3085 }
3086
3087 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3088 struct igb_ring *tx_ring,
3089 struct sk_buff *skb, u32 tx_flags)
3090 {
3091 struct e1000_adv_tx_context_desc *context_desc;
3092 unsigned int i;
3093 struct igb_buffer *buffer_info;
3094 u32 info = 0, tu_cmd = 0;
3095
3096 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3097 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3098 i = tx_ring->next_to_use;
3099 buffer_info = &tx_ring->buffer_info[i];
3100 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3101
3102 if (tx_flags & IGB_TX_FLAGS_VLAN)
3103 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3104 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3105 if (skb->ip_summed == CHECKSUM_PARTIAL)
3106 info |= skb_network_header_len(skb);
3107
3108 context_desc->vlan_macip_lens = cpu_to_le32(info);
3109
3110 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3111
3112 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3113 __be16 protocol;
3114
3115 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3116 const struct vlan_ethhdr *vhdr =
3117 (const struct vlan_ethhdr*)skb->data;
3118
3119 protocol = vhdr->h_vlan_encapsulated_proto;
3120 } else {
3121 protocol = skb->protocol;
3122 }
3123
3124 switch (protocol) {
3125 case cpu_to_be16(ETH_P_IP):
3126 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3127 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3128 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3129 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3130 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3131 break;
3132 case cpu_to_be16(ETH_P_IPV6):
3133 /* XXX what about other V6 headers?? */
3134 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3135 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3136 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3137 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3138 break;
3139 default:
3140 if (unlikely(net_ratelimit()))
3141 dev_warn(&adapter->pdev->dev,
3142 "partial checksum but proto=%x!\n",
3143 skb->protocol);
3144 break;
3145 }
3146 }
3147
3148 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3149 context_desc->seqnum_seed = 0;
3150 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3151 context_desc->mss_l4len_idx =
3152 cpu_to_le32(tx_ring->queue_index << 4);
3153 else
3154 context_desc->mss_l4len_idx = 0;
3155
3156 buffer_info->time_stamp = jiffies;
3157 buffer_info->next_to_watch = i;
3158 buffer_info->dma = 0;
3159
3160 i++;
3161 if (i == tx_ring->count)
3162 i = 0;
3163 tx_ring->next_to_use = i;
3164
3165 return true;
3166 }
3167 return false;
3168 }
3169
3170 #define IGB_MAX_TXD_PWR 16
3171 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3172
3173 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3174 struct igb_ring *tx_ring, struct sk_buff *skb,
3175 unsigned int first)
3176 {
3177 struct igb_buffer *buffer_info;
3178 unsigned int len = skb_headlen(skb);
3179 unsigned int count = 0, i;
3180 unsigned int f;
3181 dma_addr_t *map;
3182
3183 i = tx_ring->next_to_use;
3184
3185 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3186 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3187 return 0;
3188 }
3189
3190 map = skb_shinfo(skb)->dma_maps;
3191
3192 buffer_info = &tx_ring->buffer_info[i];
3193 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3194 buffer_info->length = len;
3195 /* set time_stamp *before* dma to help avoid a possible race */
3196 buffer_info->time_stamp = jiffies;
3197 buffer_info->next_to_watch = i;
3198 buffer_info->dma = skb_shinfo(skb)->dma_head;
3199
3200 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3201 struct skb_frag_struct *frag;
3202
3203 i++;
3204 if (i == tx_ring->count)
3205 i = 0;
3206
3207 frag = &skb_shinfo(skb)->frags[f];
3208 len = frag->size;
3209
3210 buffer_info = &tx_ring->buffer_info[i];
3211 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3212 buffer_info->length = len;
3213 buffer_info->time_stamp = jiffies;
3214 buffer_info->next_to_watch = i;
3215 buffer_info->dma = map[count];
3216 count++;
3217 }
3218
3219 tx_ring->buffer_info[i].skb = skb;
3220 tx_ring->buffer_info[first].next_to_watch = i;
3221
3222 return count + 1;
3223 }
3224
3225 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3226 struct igb_ring *tx_ring,
3227 int tx_flags, int count, u32 paylen,
3228 u8 hdr_len)
3229 {
3230 union e1000_adv_tx_desc *tx_desc = NULL;
3231 struct igb_buffer *buffer_info;
3232 u32 olinfo_status = 0, cmd_type_len;
3233 unsigned int i;
3234
3235 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3236 E1000_ADVTXD_DCMD_DEXT);
3237
3238 if (tx_flags & IGB_TX_FLAGS_VLAN)
3239 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3240
3241 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3242 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3243
3244 if (tx_flags & IGB_TX_FLAGS_TSO) {
3245 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3246
3247 /* insert tcp checksum */
3248 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3249
3250 /* insert ip checksum */
3251 if (tx_flags & IGB_TX_FLAGS_IPV4)
3252 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3253
3254 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3255 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3256 }
3257
3258 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3259 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3260 IGB_TX_FLAGS_VLAN)))
3261 olinfo_status |= tx_ring->queue_index << 4;
3262
3263 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3264
3265 i = tx_ring->next_to_use;
3266 while (count--) {
3267 buffer_info = &tx_ring->buffer_info[i];
3268 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3269 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3270 tx_desc->read.cmd_type_len =
3271 cpu_to_le32(cmd_type_len | buffer_info->length);
3272 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3273 i++;
3274 if (i == tx_ring->count)
3275 i = 0;
3276 }
3277
3278 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3279 /* Force memory writes to complete before letting h/w
3280 * know there are new descriptors to fetch. (Only
3281 * applicable for weak-ordered memory model archs,
3282 * such as IA-64). */
3283 wmb();
3284
3285 tx_ring->next_to_use = i;
3286 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3287 /* we need this if more than one processor can write to our tail
3288 * at a time, it syncronizes IO on IA64/Altix systems */
3289 mmiowb();
3290 }
3291
3292 static int __igb_maybe_stop_tx(struct net_device *netdev,
3293 struct igb_ring *tx_ring, int size)
3294 {
3295 struct igb_adapter *adapter = netdev_priv(netdev);
3296
3297 netif_stop_subqueue(netdev, tx_ring->queue_index);
3298
3299 /* Herbert's original patch had:
3300 * smp_mb__after_netif_stop_queue();
3301 * but since that doesn't exist yet, just open code it. */
3302 smp_mb();
3303
3304 /* We need to check again in a case another CPU has just
3305 * made room available. */
3306 if (igb_desc_unused(tx_ring) < size)
3307 return -EBUSY;
3308
3309 /* A reprieve! */
3310 netif_wake_subqueue(netdev, tx_ring->queue_index);
3311 ++adapter->restart_queue;
3312 return 0;
3313 }
3314
3315 static int igb_maybe_stop_tx(struct net_device *netdev,
3316 struct igb_ring *tx_ring, int size)
3317 {
3318 if (igb_desc_unused(tx_ring) >= size)
3319 return 0;
3320 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3321 }
3322
3323 static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3324 struct net_device *netdev,
3325 struct igb_ring *tx_ring)
3326 {
3327 struct igb_adapter *adapter = netdev_priv(netdev);
3328 unsigned int first;
3329 unsigned int tx_flags = 0;
3330 u8 hdr_len = 0;
3331 int count = 0;
3332 int tso = 0;
3333 union skb_shared_tx *shtx;
3334
3335 if (test_bit(__IGB_DOWN, &adapter->state)) {
3336 dev_kfree_skb_any(skb);
3337 return NETDEV_TX_OK;
3338 }
3339
3340 if (skb->len <= 0) {
3341 dev_kfree_skb_any(skb);
3342 return NETDEV_TX_OK;
3343 }
3344
3345 /* need: 1 descriptor per page,
3346 * + 2 desc gap to keep tail from touching head,
3347 * + 1 desc for skb->data,
3348 * + 1 desc for context descriptor,
3349 * otherwise try next time */
3350 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3351 /* this is a hard error */
3352 return NETDEV_TX_BUSY;
3353 }
3354
3355 /*
3356 * TODO: check that there currently is no other packet with
3357 * time stamping in the queue
3358 *
3359 * When doing time stamping, keep the connection to the socket
3360 * a while longer: it is still needed by skb_hwtstamp_tx(),
3361 * called either in igb_tx_hwtstamp() or by our caller when
3362 * doing software time stamping.
3363 */
3364 shtx = skb_tx(skb);
3365 if (unlikely(shtx->hardware)) {
3366 shtx->in_progress = 1;
3367 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3368 }
3369
3370 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3371 tx_flags |= IGB_TX_FLAGS_VLAN;
3372 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3373 }
3374
3375 if (skb->protocol == htons(ETH_P_IP))
3376 tx_flags |= IGB_TX_FLAGS_IPV4;
3377
3378 first = tx_ring->next_to_use;
3379 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3380 &hdr_len) : 0;
3381
3382 if (tso < 0) {
3383 dev_kfree_skb_any(skb);
3384 return NETDEV_TX_OK;
3385 }
3386
3387 if (tso)
3388 tx_flags |= IGB_TX_FLAGS_TSO;
3389 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3390 (skb->ip_summed == CHECKSUM_PARTIAL))
3391 tx_flags |= IGB_TX_FLAGS_CSUM;
3392
3393 /*
3394 * count reflects descriptors mapped, if 0 then mapping error
3395 * has occured and we need to rewind the descriptor queue
3396 */
3397 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3398
3399 if (count) {
3400 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3401 skb->len, hdr_len);
3402 /* Make sure there is space in the ring for the next send. */
3403 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3404 } else {
3405 dev_kfree_skb_any(skb);
3406 tx_ring->buffer_info[first].time_stamp = 0;
3407 tx_ring->next_to_use = first;
3408 }
3409
3410 return NETDEV_TX_OK;
3411 }
3412
3413 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3414 struct net_device *netdev)
3415 {
3416 struct igb_adapter *adapter = netdev_priv(netdev);
3417 struct igb_ring *tx_ring;
3418
3419 int r_idx = 0;
3420 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3421 tx_ring = adapter->multi_tx_table[r_idx];
3422
3423 /* This goes back to the question of how to logically map a tx queue
3424 * to a flow. Right now, performance is impacted slightly negatively
3425 * if using multiple tx queues. If the stack breaks away from a
3426 * single qdisc implementation, we can look at this again. */
3427 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
3428 }
3429
3430 /**
3431 * igb_tx_timeout - Respond to a Tx Hang
3432 * @netdev: network interface device structure
3433 **/
3434 static void igb_tx_timeout(struct net_device *netdev)
3435 {
3436 struct igb_adapter *adapter = netdev_priv(netdev);
3437 struct e1000_hw *hw = &adapter->hw;
3438
3439 /* Do the reset outside of interrupt context */
3440 adapter->tx_timeout_count++;
3441 schedule_work(&adapter->reset_task);
3442 wr32(E1000_EICS,
3443 (adapter->eims_enable_mask & ~adapter->eims_other));
3444 }
3445
3446 static void igb_reset_task(struct work_struct *work)
3447 {
3448 struct igb_adapter *adapter;
3449 adapter = container_of(work, struct igb_adapter, reset_task);
3450
3451 igb_reinit_locked(adapter);
3452 }
3453
3454 /**
3455 * igb_get_stats - Get System Network Statistics
3456 * @netdev: network interface device structure
3457 *
3458 * Returns the address of the device statistics structure.
3459 * The statistics are actually updated from the timer callback.
3460 **/
3461 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3462 {
3463 struct igb_adapter *adapter = netdev_priv(netdev);
3464
3465 /* only return the current stats */
3466 return &adapter->net_stats;
3467 }
3468
3469 /**
3470 * igb_change_mtu - Change the Maximum Transfer Unit
3471 * @netdev: network interface device structure
3472 * @new_mtu: new value for maximum frame size
3473 *
3474 * Returns 0 on success, negative on failure
3475 **/
3476 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3477 {
3478 struct igb_adapter *adapter = netdev_priv(netdev);
3479 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3480
3481 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3482 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3483 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3484 return -EINVAL;
3485 }
3486
3487 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3488 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3489 return -EINVAL;
3490 }
3491
3492 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3493 msleep(1);
3494
3495 /* igb_down has a dependency on max_frame_size */
3496 adapter->max_frame_size = max_frame;
3497 if (netif_running(netdev))
3498 igb_down(adapter);
3499
3500 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3501 * means we reserve 2 more, this pushes us to allocate from the next
3502 * larger slab size.
3503 * i.e. RXBUFFER_2048 --> size-4096 slab
3504 */
3505
3506 if (max_frame <= IGB_RXBUFFER_256)
3507 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3508 else if (max_frame <= IGB_RXBUFFER_512)
3509 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3510 else if (max_frame <= IGB_RXBUFFER_1024)
3511 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3512 else if (max_frame <= IGB_RXBUFFER_2048)
3513 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3514 else
3515 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3516 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3517 #else
3518 adapter->rx_buffer_len = PAGE_SIZE / 2;
3519 #endif
3520
3521 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3522 if (adapter->vfs_allocated_count &&
3523 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3524 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3525
3526 /* adjust allocation if LPE protects us, and we aren't using SBP */
3527 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3528 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3529 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3530
3531 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3532 netdev->mtu, new_mtu);
3533 netdev->mtu = new_mtu;
3534
3535 if (netif_running(netdev))
3536 igb_up(adapter);
3537 else
3538 igb_reset(adapter);
3539
3540 clear_bit(__IGB_RESETTING, &adapter->state);
3541
3542 return 0;
3543 }
3544
3545 /**
3546 * igb_update_stats - Update the board statistics counters
3547 * @adapter: board private structure
3548 **/
3549
3550 void igb_update_stats(struct igb_adapter *adapter)
3551 {
3552 struct e1000_hw *hw = &adapter->hw;
3553 struct pci_dev *pdev = adapter->pdev;
3554 u16 phy_tmp;
3555
3556 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3557
3558 /*
3559 * Prevent stats update while adapter is being reset, or if the pci
3560 * connection is down.
3561 */
3562 if (adapter->link_speed == 0)
3563 return;
3564 if (pci_channel_offline(pdev))
3565 return;
3566
3567 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3568 adapter->stats.gprc += rd32(E1000_GPRC);
3569 adapter->stats.gorc += rd32(E1000_GORCL);
3570 rd32(E1000_GORCH); /* clear GORCL */
3571 adapter->stats.bprc += rd32(E1000_BPRC);
3572 adapter->stats.mprc += rd32(E1000_MPRC);
3573 adapter->stats.roc += rd32(E1000_ROC);
3574
3575 adapter->stats.prc64 += rd32(E1000_PRC64);
3576 adapter->stats.prc127 += rd32(E1000_PRC127);
3577 adapter->stats.prc255 += rd32(E1000_PRC255);
3578 adapter->stats.prc511 += rd32(E1000_PRC511);
3579 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3580 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3581 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3582 adapter->stats.sec += rd32(E1000_SEC);
3583
3584 adapter->stats.mpc += rd32(E1000_MPC);
3585 adapter->stats.scc += rd32(E1000_SCC);
3586 adapter->stats.ecol += rd32(E1000_ECOL);
3587 adapter->stats.mcc += rd32(E1000_MCC);
3588 adapter->stats.latecol += rd32(E1000_LATECOL);
3589 adapter->stats.dc += rd32(E1000_DC);
3590 adapter->stats.rlec += rd32(E1000_RLEC);
3591 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3592 adapter->stats.xontxc += rd32(E1000_XONTXC);
3593 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3594 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3595 adapter->stats.fcruc += rd32(E1000_FCRUC);
3596 adapter->stats.gptc += rd32(E1000_GPTC);
3597 adapter->stats.gotc += rd32(E1000_GOTCL);
3598 rd32(E1000_GOTCH); /* clear GOTCL */
3599 adapter->stats.rnbc += rd32(E1000_RNBC);
3600 adapter->stats.ruc += rd32(E1000_RUC);
3601 adapter->stats.rfc += rd32(E1000_RFC);
3602 adapter->stats.rjc += rd32(E1000_RJC);
3603 adapter->stats.tor += rd32(E1000_TORH);
3604 adapter->stats.tot += rd32(E1000_TOTH);
3605 adapter->stats.tpr += rd32(E1000_TPR);
3606
3607 adapter->stats.ptc64 += rd32(E1000_PTC64);
3608 adapter->stats.ptc127 += rd32(E1000_PTC127);
3609 adapter->stats.ptc255 += rd32(E1000_PTC255);
3610 adapter->stats.ptc511 += rd32(E1000_PTC511);
3611 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3612 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3613
3614 adapter->stats.mptc += rd32(E1000_MPTC);
3615 adapter->stats.bptc += rd32(E1000_BPTC);
3616
3617 /* used for adaptive IFS */
3618
3619 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3620 adapter->stats.tpt += hw->mac.tx_packet_delta;
3621 hw->mac.collision_delta = rd32(E1000_COLC);
3622 adapter->stats.colc += hw->mac.collision_delta;
3623
3624 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3625 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3626 adapter->stats.tncrs += rd32(E1000_TNCRS);
3627 adapter->stats.tsctc += rd32(E1000_TSCTC);
3628 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3629
3630 adapter->stats.iac += rd32(E1000_IAC);
3631 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3632 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3633 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3634 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3635 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3636 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3637 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3638 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3639
3640 /* Fill out the OS statistics structure */
3641 adapter->net_stats.multicast = adapter->stats.mprc;
3642 adapter->net_stats.collisions = adapter->stats.colc;
3643
3644 /* Rx Errors */
3645
3646 if (hw->mac.type != e1000_82575) {
3647 u32 rqdpc_tmp;
3648 u64 rqdpc_total = 0;
3649 int i;
3650 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3651 * Queue Drop Packet Count) stats only gets incremented, if
3652 * the DROP_EN but it set (in the SRRCTL register for that
3653 * queue). If DROP_EN bit is NOT set, then the some what
3654 * equivalent count is stored in RNBC (not per queue basis).
3655 * Also note the drop count is due to lack of available
3656 * descriptors.
3657 */
3658 for (i = 0; i < adapter->num_rx_queues; i++) {
3659 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3660 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3661 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
3662 }
3663 adapter->net_stats.rx_fifo_errors = rqdpc_total;
3664 }
3665
3666 /* Note RNBC (Receive No Buffers Count) is an not an exact
3667 * drop count as the hardware FIFO might save the day. Thats
3668 * one of the reason for saving it in rx_fifo_errors, as its
3669 * potentially not a true drop.
3670 */
3671 adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3672
3673 /* RLEC on some newer hardware can be incorrect so build
3674 * our own version based on RUC and ROC */
3675 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3676 adapter->stats.crcerrs + adapter->stats.algnerrc +
3677 adapter->stats.ruc + adapter->stats.roc +
3678 adapter->stats.cexterr;
3679 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3680 adapter->stats.roc;
3681 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3682 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3683 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3684
3685 /* Tx Errors */
3686 adapter->net_stats.tx_errors = adapter->stats.ecol +
3687 adapter->stats.latecol;
3688 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3689 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3690 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3691
3692 /* Tx Dropped needs to be maintained elsewhere */
3693
3694 /* Phy Stats */
3695 if (hw->phy.media_type == e1000_media_type_copper) {
3696 if ((adapter->link_speed == SPEED_1000) &&
3697 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3698 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3699 adapter->phy_stats.idle_errors += phy_tmp;
3700 }
3701 }
3702
3703 /* Management Stats */
3704 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3705 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3706 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3707 }
3708
3709 static irqreturn_t igb_msix_other(int irq, void *data)
3710 {
3711 struct net_device *netdev = data;
3712 struct igb_adapter *adapter = netdev_priv(netdev);
3713 struct e1000_hw *hw = &adapter->hw;
3714 u32 icr = rd32(E1000_ICR);
3715
3716 /* reading ICR causes bit 31 of EICR to be cleared */
3717
3718 if(icr & E1000_ICR_DOUTSYNC) {
3719 /* HW is reporting DMA is out of sync */
3720 adapter->stats.doosync++;
3721 }
3722
3723 /* Check for a mailbox event */
3724 if (icr & E1000_ICR_VMMB)
3725 igb_msg_task(adapter);
3726
3727 if (icr & E1000_ICR_LSC) {
3728 hw->mac.get_link_status = 1;
3729 /* guard against interrupt when we're going down */
3730 if (!test_bit(__IGB_DOWN, &adapter->state))
3731 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3732 }
3733
3734 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3735 wr32(E1000_EIMS, adapter->eims_other);
3736
3737 return IRQ_HANDLED;
3738 }
3739
3740 static irqreturn_t igb_msix_tx(int irq, void *data)
3741 {
3742 struct igb_ring *tx_ring = data;
3743 struct igb_adapter *adapter = tx_ring->adapter;
3744 struct e1000_hw *hw = &adapter->hw;
3745
3746 #ifdef CONFIG_IGB_DCA
3747 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3748 igb_update_tx_dca(tx_ring);
3749 #endif
3750
3751 tx_ring->total_bytes = 0;
3752 tx_ring->total_packets = 0;
3753
3754 /* auto mask will automatically reenable the interrupt when we write
3755 * EICS */
3756 if (!igb_clean_tx_irq(tx_ring))
3757 /* Ring was not completely cleaned, so fire another interrupt */
3758 wr32(E1000_EICS, tx_ring->eims_value);
3759 else
3760 wr32(E1000_EIMS, tx_ring->eims_value);
3761
3762 return IRQ_HANDLED;
3763 }
3764
3765 static void igb_write_itr(struct igb_ring *ring)
3766 {
3767 struct e1000_hw *hw = &ring->adapter->hw;
3768 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3769 switch (hw->mac.type) {
3770 case e1000_82576:
3771 wr32(ring->itr_register, ring->itr_val |
3772 0x80000000);
3773 break;
3774 default:
3775 wr32(ring->itr_register, ring->itr_val |
3776 (ring->itr_val << 16));
3777 break;
3778 }
3779 ring->set_itr = 0;
3780 }
3781 }
3782
3783 static irqreturn_t igb_msix_rx(int irq, void *data)
3784 {
3785 struct igb_ring *rx_ring = data;
3786
3787 /* Write the ITR value calculated at the end of the
3788 * previous interrupt.
3789 */
3790
3791 igb_write_itr(rx_ring);
3792
3793 if (napi_schedule_prep(&rx_ring->napi))
3794 __napi_schedule(&rx_ring->napi);
3795
3796 #ifdef CONFIG_IGB_DCA
3797 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3798 igb_update_rx_dca(rx_ring);
3799 #endif
3800 return IRQ_HANDLED;
3801 }
3802
3803 #ifdef CONFIG_IGB_DCA
3804 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3805 {
3806 u32 dca_rxctrl;
3807 struct igb_adapter *adapter = rx_ring->adapter;
3808 struct e1000_hw *hw = &adapter->hw;
3809 int cpu = get_cpu();
3810 int q = rx_ring->reg_idx;
3811
3812 if (rx_ring->cpu != cpu) {
3813 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3814 if (hw->mac.type == e1000_82576) {
3815 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3816 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3817 E1000_DCA_RXCTRL_CPUID_SHIFT;
3818 } else {
3819 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3820 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3821 }
3822 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3823 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3824 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3825 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3826 rx_ring->cpu = cpu;
3827 }
3828 put_cpu();
3829 }
3830
3831 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3832 {
3833 u32 dca_txctrl;
3834 struct igb_adapter *adapter = tx_ring->adapter;
3835 struct e1000_hw *hw = &adapter->hw;
3836 int cpu = get_cpu();
3837 int q = tx_ring->reg_idx;
3838
3839 if (tx_ring->cpu != cpu) {
3840 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3841 if (hw->mac.type == e1000_82576) {
3842 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3843 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3844 E1000_DCA_TXCTRL_CPUID_SHIFT;
3845 } else {
3846 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3847 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3848 }
3849 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3850 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3851 tx_ring->cpu = cpu;
3852 }
3853 put_cpu();
3854 }
3855
3856 static void igb_setup_dca(struct igb_adapter *adapter)
3857 {
3858 struct e1000_hw *hw = &adapter->hw;
3859 int i;
3860
3861 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3862 return;
3863
3864 /* Always use CB2 mode, difference is masked in the CB driver. */
3865 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3866
3867 for (i = 0; i < adapter->num_tx_queues; i++) {
3868 adapter->tx_ring[i].cpu = -1;
3869 igb_update_tx_dca(&adapter->tx_ring[i]);
3870 }
3871 for (i = 0; i < adapter->num_rx_queues; i++) {
3872 adapter->rx_ring[i].cpu = -1;
3873 igb_update_rx_dca(&adapter->rx_ring[i]);
3874 }
3875 }
3876
3877 static int __igb_notify_dca(struct device *dev, void *data)
3878 {
3879 struct net_device *netdev = dev_get_drvdata(dev);
3880 struct igb_adapter *adapter = netdev_priv(netdev);
3881 struct e1000_hw *hw = &adapter->hw;
3882 unsigned long event = *(unsigned long *)data;
3883
3884 switch (event) {
3885 case DCA_PROVIDER_ADD:
3886 /* if already enabled, don't do it again */
3887 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3888 break;
3889 /* Always use CB2 mode, difference is masked
3890 * in the CB driver. */
3891 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3892 if (dca_add_requester(dev) == 0) {
3893 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3894 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3895 igb_setup_dca(adapter);
3896 break;
3897 }
3898 /* Fall Through since DCA is disabled. */
3899 case DCA_PROVIDER_REMOVE:
3900 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3901 /* without this a class_device is left
3902 * hanging around in the sysfs model */
3903 dca_remove_requester(dev);
3904 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3905 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3906 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3907 }
3908 break;
3909 }
3910
3911 return 0;
3912 }
3913
3914 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3915 void *p)
3916 {
3917 int ret_val;
3918
3919 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3920 __igb_notify_dca);
3921
3922 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3923 }
3924 #endif /* CONFIG_IGB_DCA */
3925
3926 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3927 {
3928 struct e1000_hw *hw = &adapter->hw;
3929 u32 ping;
3930 int i;
3931
3932 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3933 ping = E1000_PF_CONTROL_MSG;
3934 if (adapter->vf_data[i].clear_to_send)
3935 ping |= E1000_VT_MSGTYPE_CTS;
3936 igb_write_mbx(hw, &ping, 1, i);
3937 }
3938 }
3939
3940 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3941 u32 *msgbuf, u32 vf)
3942 {
3943 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3944 u16 *hash_list = (u16 *)&msgbuf[1];
3945 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3946 int i;
3947
3948 /* only up to 30 hash values supported */
3949 if (n > 30)
3950 n = 30;
3951
3952 /* salt away the number of multi cast addresses assigned
3953 * to this VF for later use to restore when the PF multi cast
3954 * list changes
3955 */
3956 vf_data->num_vf_mc_hashes = n;
3957
3958 /* VFs are limited to using the MTA hash table for their multicast
3959 * addresses */
3960 for (i = 0; i < n; i++)
3961 vf_data->vf_mc_hashes[i] = hash_list[i];
3962
3963 /* Flush and reset the mta with the new values */
3964 igb_set_rx_mode(adapter->netdev);
3965
3966 return 0;
3967 }
3968
3969 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3970 {
3971 struct e1000_hw *hw = &adapter->hw;
3972 struct vf_data_storage *vf_data;
3973 int i, j;
3974
3975 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3976 vf_data = &adapter->vf_data[i];
3977 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3978 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3979 }
3980 }
3981
3982 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3983 {
3984 struct e1000_hw *hw = &adapter->hw;
3985 u32 pool_mask, reg, vid;
3986 int i;
3987
3988 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3989
3990 /* Find the vlan filter for this id */
3991 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3992 reg = rd32(E1000_VLVF(i));
3993
3994 /* remove the vf from the pool */
3995 reg &= ~pool_mask;
3996
3997 /* if pool is empty then remove entry from vfta */
3998 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3999 (reg & E1000_VLVF_VLANID_ENABLE)) {
4000 reg = 0;
4001 vid = reg & E1000_VLVF_VLANID_MASK;
4002 igb_vfta_set(hw, vid, false);
4003 }
4004
4005 wr32(E1000_VLVF(i), reg);
4006 }
4007
4008 adapter->vf_data[vf].vlans_enabled = 0;
4009 }
4010
4011 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4012 {
4013 struct e1000_hw *hw = &adapter->hw;
4014 u32 reg, i;
4015
4016 /* It is an error to call this function when VFs are not enabled */
4017 if (!adapter->vfs_allocated_count)
4018 return -1;
4019
4020 /* Find the vlan filter for this id */
4021 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4022 reg = rd32(E1000_VLVF(i));
4023 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4024 vid == (reg & E1000_VLVF_VLANID_MASK))
4025 break;
4026 }
4027
4028 if (add) {
4029 if (i == E1000_VLVF_ARRAY_SIZE) {
4030 /* Did not find a matching VLAN ID entry that was
4031 * enabled. Search for a free filter entry, i.e.
4032 * one without the enable bit set
4033 */
4034 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4035 reg = rd32(E1000_VLVF(i));
4036 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4037 break;
4038 }
4039 }
4040 if (i < E1000_VLVF_ARRAY_SIZE) {
4041 /* Found an enabled/available entry */
4042 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4043
4044 /* if !enabled we need to set this up in vfta */
4045 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
4046 /* add VID to filter table, if bit already set
4047 * PF must have added it outside of table */
4048 if (igb_vfta_set(hw, vid, true))
4049 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4050 adapter->vfs_allocated_count);
4051 reg |= E1000_VLVF_VLANID_ENABLE;
4052 }
4053 reg &= ~E1000_VLVF_VLANID_MASK;
4054 reg |= vid;
4055
4056 wr32(E1000_VLVF(i), reg);
4057
4058 /* do not modify RLPML for PF devices */
4059 if (vf >= adapter->vfs_allocated_count)
4060 return 0;
4061
4062 if (!adapter->vf_data[vf].vlans_enabled) {
4063 u32 size;
4064 reg = rd32(E1000_VMOLR(vf));
4065 size = reg & E1000_VMOLR_RLPML_MASK;
4066 size += 4;
4067 reg &= ~E1000_VMOLR_RLPML_MASK;
4068 reg |= size;
4069 wr32(E1000_VMOLR(vf), reg);
4070 }
4071 adapter->vf_data[vf].vlans_enabled++;
4072
4073 return 0;
4074 }
4075 } else {
4076 if (i < E1000_VLVF_ARRAY_SIZE) {
4077 /* remove vf from the pool */
4078 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4079 /* if pool is empty then remove entry from vfta */
4080 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4081 reg = 0;
4082 igb_vfta_set(hw, vid, false);
4083 }
4084 wr32(E1000_VLVF(i), reg);
4085
4086 /* do not modify RLPML for PF devices */
4087 if (vf >= adapter->vfs_allocated_count)
4088 return 0;
4089
4090 adapter->vf_data[vf].vlans_enabled--;
4091 if (!adapter->vf_data[vf].vlans_enabled) {
4092 u32 size;
4093 reg = rd32(E1000_VMOLR(vf));
4094 size = reg & E1000_VMOLR_RLPML_MASK;
4095 size -= 4;
4096 reg &= ~E1000_VMOLR_RLPML_MASK;
4097 reg |= size;
4098 wr32(E1000_VMOLR(vf), reg);
4099 }
4100 return 0;
4101 }
4102 }
4103 return -1;
4104 }
4105
4106 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4107 {
4108 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4109 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4110
4111 return igb_vlvf_set(adapter, vid, add, vf);
4112 }
4113
4114 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4115 {
4116 struct e1000_hw *hw = &adapter->hw;
4117
4118 /* disable mailbox functionality for vf */
4119 adapter->vf_data[vf].clear_to_send = false;
4120
4121 /* reset offloads to defaults */
4122 igb_set_vmolr(hw, vf);
4123
4124 /* reset vlans for device */
4125 igb_clear_vf_vfta(adapter, vf);
4126
4127 /* reset multicast table array for vf */
4128 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4129
4130 /* Flush and reset the mta with the new values */
4131 igb_set_rx_mode(adapter->netdev);
4132 }
4133
4134 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4135 {
4136 struct e1000_hw *hw = &adapter->hw;
4137 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4138 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4139 u32 reg, msgbuf[3];
4140 u8 *addr = (u8 *)(&msgbuf[1]);
4141
4142 /* process all the same items cleared in a function level reset */
4143 igb_vf_reset_event(adapter, vf);
4144
4145 /* set vf mac address */
4146 igb_rar_set(hw, vf_mac, rar_entry);
4147 igb_set_rah_pool(hw, vf, rar_entry);
4148
4149 /* enable transmit and receive for vf */
4150 reg = rd32(E1000_VFTE);
4151 wr32(E1000_VFTE, reg | (1 << vf));
4152 reg = rd32(E1000_VFRE);
4153 wr32(E1000_VFRE, reg | (1 << vf));
4154
4155 /* enable mailbox functionality for vf */
4156 adapter->vf_data[vf].clear_to_send = true;
4157
4158 /* reply to reset with ack and vf mac address */
4159 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4160 memcpy(addr, vf_mac, 6);
4161 igb_write_mbx(hw, msgbuf, 3, vf);
4162 }
4163
4164 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4165 {
4166 unsigned char *addr = (char *)&msg[1];
4167 int err = -1;
4168
4169 if (is_valid_ether_addr(addr))
4170 err = igb_set_vf_mac(adapter, vf, addr);
4171
4172 return err;
4173
4174 }
4175
4176 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4177 {
4178 struct e1000_hw *hw = &adapter->hw;
4179 u32 msg = E1000_VT_MSGTYPE_NACK;
4180
4181 /* if device isn't clear to send it shouldn't be reading either */
4182 if (!adapter->vf_data[vf].clear_to_send)
4183 igb_write_mbx(hw, &msg, 1, vf);
4184 }
4185
4186
4187 static void igb_msg_task(struct igb_adapter *adapter)
4188 {
4189 struct e1000_hw *hw = &adapter->hw;
4190 u32 vf;
4191
4192 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4193 /* process any reset requests */
4194 if (!igb_check_for_rst(hw, vf)) {
4195 adapter->vf_data[vf].clear_to_send = false;
4196 igb_vf_reset_event(adapter, vf);
4197 }
4198
4199 /* process any messages pending */
4200 if (!igb_check_for_msg(hw, vf))
4201 igb_rcv_msg_from_vf(adapter, vf);
4202
4203 /* process any acks */
4204 if (!igb_check_for_ack(hw, vf))
4205 igb_rcv_ack_from_vf(adapter, vf);
4206
4207 }
4208 }
4209
4210 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4211 {
4212 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4213 u32 msgbuf[mbx_size];
4214 struct e1000_hw *hw = &adapter->hw;
4215 s32 retval;
4216
4217 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4218
4219 if (retval)
4220 dev_err(&adapter->pdev->dev,
4221 "Error receiving message from VF\n");
4222
4223 /* this is a message we already processed, do nothing */
4224 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4225 return retval;
4226
4227 /*
4228 * until the vf completes a reset it should not be
4229 * allowed to start any configuration.
4230 */
4231
4232 if (msgbuf[0] == E1000_VF_RESET) {
4233 igb_vf_reset_msg(adapter, vf);
4234
4235 return retval;
4236 }
4237
4238 if (!adapter->vf_data[vf].clear_to_send) {
4239 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4240 igb_write_mbx(hw, msgbuf, 1, vf);
4241 return retval;
4242 }
4243
4244 switch ((msgbuf[0] & 0xFFFF)) {
4245 case E1000_VF_SET_MAC_ADDR:
4246 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4247 break;
4248 case E1000_VF_SET_MULTICAST:
4249 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4250 break;
4251 case E1000_VF_SET_LPE:
4252 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4253 break;
4254 case E1000_VF_SET_VLAN:
4255 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4256 break;
4257 default:
4258 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4259 retval = -1;
4260 break;
4261 }
4262
4263 /* notify the VF of the results of what it sent us */
4264 if (retval)
4265 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4266 else
4267 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4268
4269 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4270
4271 igb_write_mbx(hw, msgbuf, 1, vf);
4272
4273 return retval;
4274 }
4275
4276 /**
4277 * igb_intr_msi - Interrupt Handler
4278 * @irq: interrupt number
4279 * @data: pointer to a network interface device structure
4280 **/
4281 static irqreturn_t igb_intr_msi(int irq, void *data)
4282 {
4283 struct net_device *netdev = data;
4284 struct igb_adapter *adapter = netdev_priv(netdev);
4285 struct e1000_hw *hw = &adapter->hw;
4286 /* read ICR disables interrupts using IAM */
4287 u32 icr = rd32(E1000_ICR);
4288
4289 igb_write_itr(adapter->rx_ring);
4290
4291 if(icr & E1000_ICR_DOUTSYNC) {
4292 /* HW is reporting DMA is out of sync */
4293 adapter->stats.doosync++;
4294 }
4295
4296 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4297 hw->mac.get_link_status = 1;
4298 if (!test_bit(__IGB_DOWN, &adapter->state))
4299 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4300 }
4301
4302 napi_schedule(&adapter->rx_ring[0].napi);
4303
4304 return IRQ_HANDLED;
4305 }
4306
4307 /**
4308 * igb_intr - Legacy Interrupt Handler
4309 * @irq: interrupt number
4310 * @data: pointer to a network interface device structure
4311 **/
4312 static irqreturn_t igb_intr(int irq, void *data)
4313 {
4314 struct net_device *netdev = data;
4315 struct igb_adapter *adapter = netdev_priv(netdev);
4316 struct e1000_hw *hw = &adapter->hw;
4317 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4318 * need for the IMC write */
4319 u32 icr = rd32(E1000_ICR);
4320 if (!icr)
4321 return IRQ_NONE; /* Not our interrupt */
4322
4323 igb_write_itr(adapter->rx_ring);
4324
4325 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4326 * not set, then the adapter didn't send an interrupt */
4327 if (!(icr & E1000_ICR_INT_ASSERTED))
4328 return IRQ_NONE;
4329
4330 if(icr & E1000_ICR_DOUTSYNC) {
4331 /* HW is reporting DMA is out of sync */
4332 adapter->stats.doosync++;
4333 }
4334
4335 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4336 hw->mac.get_link_status = 1;
4337 /* guard against interrupt when we're going down */
4338 if (!test_bit(__IGB_DOWN, &adapter->state))
4339 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4340 }
4341
4342 napi_schedule(&adapter->rx_ring[0].napi);
4343
4344 return IRQ_HANDLED;
4345 }
4346
4347 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4348 {
4349 struct igb_adapter *adapter = rx_ring->adapter;
4350 struct e1000_hw *hw = &adapter->hw;
4351
4352 if (adapter->itr_setting & 3) {
4353 if (adapter->num_rx_queues == 1)
4354 igb_set_itr(adapter);
4355 else
4356 igb_update_ring_itr(rx_ring);
4357 }
4358
4359 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4360 if (adapter->msix_entries)
4361 wr32(E1000_EIMS, rx_ring->eims_value);
4362 else
4363 igb_irq_enable(adapter);
4364 }
4365 }
4366
4367 /**
4368 * igb_poll - NAPI Rx polling callback
4369 * @napi: napi polling structure
4370 * @budget: count of how many packets we should handle
4371 **/
4372 static int igb_poll(struct napi_struct *napi, int budget)
4373 {
4374 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4375 int work_done = 0;
4376
4377 #ifdef CONFIG_IGB_DCA
4378 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4379 igb_update_rx_dca(rx_ring);
4380 #endif
4381 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4382
4383 if (rx_ring->buddy) {
4384 #ifdef CONFIG_IGB_DCA
4385 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4386 igb_update_tx_dca(rx_ring->buddy);
4387 #endif
4388 if (!igb_clean_tx_irq(rx_ring->buddy))
4389 work_done = budget;
4390 }
4391
4392 /* If not enough Rx work done, exit the polling mode */
4393 if (work_done < budget) {
4394 napi_complete(napi);
4395 igb_rx_irq_enable(rx_ring);
4396 }
4397
4398 return work_done;
4399 }
4400
4401 /**
4402 * igb_hwtstamp - utility function which checks for TX time stamp
4403 * @adapter: board private structure
4404 * @skb: packet that was just sent
4405 *
4406 * If we were asked to do hardware stamping and such a time stamp is
4407 * available, then it must have been for this skb here because we only
4408 * allow only one such packet into the queue.
4409 */
4410 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4411 {
4412 union skb_shared_tx *shtx = skb_tx(skb);
4413 struct e1000_hw *hw = &adapter->hw;
4414
4415 if (unlikely(shtx->hardware)) {
4416 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4417 if (valid) {
4418 u64 regval = rd32(E1000_TXSTMPL);
4419 u64 ns;
4420 struct skb_shared_hwtstamps shhwtstamps;
4421
4422 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4423 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4424 ns = timecounter_cyc2time(&adapter->clock,
4425 regval);
4426 timecompare_update(&adapter->compare, ns);
4427 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4428 shhwtstamps.syststamp =
4429 timecompare_transform(&adapter->compare, ns);
4430 skb_tstamp_tx(skb, &shhwtstamps);
4431 }
4432 }
4433 }
4434
4435 /**
4436 * igb_clean_tx_irq - Reclaim resources after transmit completes
4437 * @adapter: board private structure
4438 * returns true if ring is completely cleaned
4439 **/
4440 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4441 {
4442 struct igb_adapter *adapter = tx_ring->adapter;
4443 struct net_device *netdev = adapter->netdev;
4444 struct e1000_hw *hw = &adapter->hw;
4445 struct igb_buffer *buffer_info;
4446 struct sk_buff *skb;
4447 union e1000_adv_tx_desc *tx_desc, *eop_desc;
4448 unsigned int total_bytes = 0, total_packets = 0;
4449 unsigned int i, eop, count = 0;
4450 bool cleaned = false;
4451
4452 i = tx_ring->next_to_clean;
4453 eop = tx_ring->buffer_info[i].next_to_watch;
4454 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4455
4456 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4457 (count < tx_ring->count)) {
4458 for (cleaned = false; !cleaned; count++) {
4459 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4460 buffer_info = &tx_ring->buffer_info[i];
4461 cleaned = (i == eop);
4462 skb = buffer_info->skb;
4463
4464 if (skb) {
4465 unsigned int segs, bytecount;
4466 /* gso_segs is currently only valid for tcp */
4467 segs = skb_shinfo(skb)->gso_segs ?: 1;
4468 /* multiply data chunks by size of headers */
4469 bytecount = ((segs - 1) * skb_headlen(skb)) +
4470 skb->len;
4471 total_packets += segs;
4472 total_bytes += bytecount;
4473
4474 igb_tx_hwtstamp(adapter, skb);
4475 }
4476
4477 igb_unmap_and_free_tx_resource(adapter, buffer_info);
4478 tx_desc->wb.status = 0;
4479
4480 i++;
4481 if (i == tx_ring->count)
4482 i = 0;
4483 }
4484 eop = tx_ring->buffer_info[i].next_to_watch;
4485 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4486 }
4487
4488 tx_ring->next_to_clean = i;
4489
4490 if (unlikely(count &&
4491 netif_carrier_ok(netdev) &&
4492 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4493 /* Make sure that anybody stopping the queue after this
4494 * sees the new next_to_clean.
4495 */
4496 smp_mb();
4497 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4498 !(test_bit(__IGB_DOWN, &adapter->state))) {
4499 netif_wake_subqueue(netdev, tx_ring->queue_index);
4500 ++adapter->restart_queue;
4501 }
4502 }
4503
4504 if (tx_ring->detect_tx_hung) {
4505 /* Detect a transmit hang in hardware, this serializes the
4506 * check with the clearing of time_stamp and movement of i */
4507 tx_ring->detect_tx_hung = false;
4508 if (tx_ring->buffer_info[i].time_stamp &&
4509 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4510 (adapter->tx_timeout_factor * HZ))
4511 && !(rd32(E1000_STATUS) &
4512 E1000_STATUS_TXOFF)) {
4513
4514 /* detected Tx unit hang */
4515 dev_err(&adapter->pdev->dev,
4516 "Detected Tx Unit Hang\n"
4517 " Tx Queue <%d>\n"
4518 " TDH <%x>\n"
4519 " TDT <%x>\n"
4520 " next_to_use <%x>\n"
4521 " next_to_clean <%x>\n"
4522 "buffer_info[next_to_clean]\n"
4523 " time_stamp <%lx>\n"
4524 " next_to_watch <%x>\n"
4525 " jiffies <%lx>\n"
4526 " desc.status <%x>\n",
4527 tx_ring->queue_index,
4528 readl(adapter->hw.hw_addr + tx_ring->head),
4529 readl(adapter->hw.hw_addr + tx_ring->tail),
4530 tx_ring->next_to_use,
4531 tx_ring->next_to_clean,
4532 tx_ring->buffer_info[i].time_stamp,
4533 eop,
4534 jiffies,
4535 eop_desc->wb.status);
4536 netif_stop_subqueue(netdev, tx_ring->queue_index);
4537 }
4538 }
4539 tx_ring->total_bytes += total_bytes;
4540 tx_ring->total_packets += total_packets;
4541 tx_ring->tx_stats.bytes += total_bytes;
4542 tx_ring->tx_stats.packets += total_packets;
4543 adapter->net_stats.tx_bytes += total_bytes;
4544 adapter->net_stats.tx_packets += total_packets;
4545 return (count < tx_ring->count);
4546 }
4547
4548 /**
4549 * igb_receive_skb - helper function to handle rx indications
4550 * @ring: pointer to receive ring receving this packet
4551 * @status: descriptor status field as written by hardware
4552 * @rx_desc: receive descriptor containing vlan and type information.
4553 * @skb: pointer to sk_buff to be indicated to stack
4554 **/
4555 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4556 union e1000_adv_rx_desc * rx_desc,
4557 struct sk_buff *skb)
4558 {
4559 struct igb_adapter * adapter = ring->adapter;
4560 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4561
4562 skb_record_rx_queue(skb, ring->queue_index);
4563 if (vlan_extracted && adapter->vlgrp)
4564 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4565 le16_to_cpu(rx_desc->wb.upper.vlan),
4566 skb);
4567 else
4568 napi_gro_receive(&ring->napi, skb);
4569 }
4570
4571 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4572 u32 status_err, struct sk_buff *skb)
4573 {
4574 skb->ip_summed = CHECKSUM_NONE;
4575
4576 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4577 if ((status_err & E1000_RXD_STAT_IXSM) ||
4578 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
4579 return;
4580 /* TCP/UDP checksum error bit is set */
4581 if (status_err &
4582 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4583 /*
4584 * work around errata with sctp packets where the TCPE aka
4585 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4586 * packets, (aka let the stack check the crc32c)
4587 */
4588 if (!((adapter->hw.mac.type == e1000_82576) &&
4589 (skb->len == 60)))
4590 adapter->hw_csum_err++;
4591 /* let the stack verify checksum errors */
4592 return;
4593 }
4594 /* It must be a TCP or UDP packet with a valid checksum */
4595 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4596 skb->ip_summed = CHECKSUM_UNNECESSARY;
4597
4598 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4599 adapter->hw_csum_good++;
4600 }
4601
4602 static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4603 union e1000_adv_rx_desc *rx_desc)
4604 {
4605 /* HW will not DMA in data larger than the given buffer, even if it
4606 * parses the (NFS, of course) header to be larger. In that case, it
4607 * fills the header buffer and spills the rest into the page.
4608 */
4609 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4610 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4611 if (hlen > adapter->rx_ps_hdr_size)
4612 hlen = adapter->rx_ps_hdr_size;
4613 return hlen;
4614 }
4615
4616 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4617 int *work_done, int budget)
4618 {
4619 struct igb_adapter *adapter = rx_ring->adapter;
4620 struct net_device *netdev = adapter->netdev;
4621 struct e1000_hw *hw = &adapter->hw;
4622 struct pci_dev *pdev = adapter->pdev;
4623 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4624 struct igb_buffer *buffer_info , *next_buffer;
4625 struct sk_buff *skb;
4626 bool cleaned = false;
4627 int cleaned_count = 0;
4628 unsigned int total_bytes = 0, total_packets = 0;
4629 unsigned int i;
4630 u32 staterr;
4631 u16 length;
4632
4633 i = rx_ring->next_to_clean;
4634 buffer_info = &rx_ring->buffer_info[i];
4635 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4636 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4637
4638 while (staterr & E1000_RXD_STAT_DD) {
4639 if (*work_done >= budget)
4640 break;
4641 (*work_done)++;
4642
4643 skb = buffer_info->skb;
4644 prefetch(skb->data - NET_IP_ALIGN);
4645 buffer_info->skb = NULL;
4646
4647 i++;
4648 if (i == rx_ring->count)
4649 i = 0;
4650 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4651 prefetch(next_rxd);
4652 next_buffer = &rx_ring->buffer_info[i];
4653
4654 length = le16_to_cpu(rx_desc->wb.upper.length);
4655 cleaned = true;
4656 cleaned_count++;
4657
4658 /* this is the fast path for the non-packet split case */
4659 if (!adapter->rx_ps_hdr_size) {
4660 pci_unmap_single(pdev, buffer_info->dma,
4661 adapter->rx_buffer_len,
4662 PCI_DMA_FROMDEVICE);
4663 buffer_info->dma = 0;
4664 skb_put(skb, length);
4665 goto send_up;
4666 }
4667
4668 if (buffer_info->dma) {
4669 u16 hlen = igb_get_hlen(adapter, rx_desc);
4670 pci_unmap_single(pdev, buffer_info->dma,
4671 adapter->rx_ps_hdr_size,
4672 PCI_DMA_FROMDEVICE);
4673 buffer_info->dma = 0;
4674 skb_put(skb, hlen);
4675 }
4676
4677 if (length) {
4678 pci_unmap_page(pdev, buffer_info->page_dma,
4679 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4680 buffer_info->page_dma = 0;
4681
4682 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4683 buffer_info->page,
4684 buffer_info->page_offset,
4685 length);
4686
4687 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4688 (page_count(buffer_info->page) != 1))
4689 buffer_info->page = NULL;
4690 else
4691 get_page(buffer_info->page);
4692
4693 skb->len += length;
4694 skb->data_len += length;
4695
4696 skb->truesize += length;
4697 }
4698
4699 if (!(staterr & E1000_RXD_STAT_EOP)) {
4700 buffer_info->skb = next_buffer->skb;
4701 buffer_info->dma = next_buffer->dma;
4702 next_buffer->skb = skb;
4703 next_buffer->dma = 0;
4704 goto next_desc;
4705 }
4706 send_up:
4707 /*
4708 * If this bit is set, then the RX registers contain
4709 * the time stamp. No other packet will be time
4710 * stamped until we read these registers, so read the
4711 * registers to make them available again. Because
4712 * only one packet can be time stamped at a time, we
4713 * know that the register values must belong to this
4714 * one here and therefore we don't need to compare
4715 * any of the additional attributes stored for it.
4716 *
4717 * If nothing went wrong, then it should have a
4718 * skb_shared_tx that we can turn into a
4719 * skb_shared_hwtstamps.
4720 *
4721 * TODO: can time stamping be triggered (thus locking
4722 * the registers) without the packet reaching this point
4723 * here? In that case RX time stamping would get stuck.
4724 *
4725 * TODO: in "time stamp all packets" mode this bit is
4726 * not set. Need a global flag for this mode and then
4727 * always read the registers. Cannot be done without
4728 * a race condition.
4729 */
4730 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4731 u64 regval;
4732 u64 ns;
4733 struct skb_shared_hwtstamps *shhwtstamps =
4734 skb_hwtstamps(skb);
4735
4736 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4737 "igb: no RX time stamp available for time stamped packet");
4738 regval = rd32(E1000_RXSTMPL);
4739 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4740 ns = timecounter_cyc2time(&adapter->clock, regval);
4741 timecompare_update(&adapter->compare, ns);
4742 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4743 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4744 shhwtstamps->syststamp =
4745 timecompare_transform(&adapter->compare, ns);
4746 }
4747
4748 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4749 dev_kfree_skb_irq(skb);
4750 goto next_desc;
4751 }
4752
4753 total_bytes += skb->len;
4754 total_packets++;
4755
4756 igb_rx_checksum_adv(adapter, staterr, skb);
4757
4758 skb->protocol = eth_type_trans(skb, netdev);
4759
4760 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4761
4762 next_desc:
4763 rx_desc->wb.upper.status_error = 0;
4764
4765 /* return some buffers to hardware, one at a time is too slow */
4766 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4767 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4768 cleaned_count = 0;
4769 }
4770
4771 /* use prefetched values */
4772 rx_desc = next_rxd;
4773 buffer_info = next_buffer;
4774 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4775 }
4776
4777 rx_ring->next_to_clean = i;
4778 cleaned_count = igb_desc_unused(rx_ring);
4779
4780 if (cleaned_count)
4781 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4782
4783 rx_ring->total_packets += total_packets;
4784 rx_ring->total_bytes += total_bytes;
4785 rx_ring->rx_stats.packets += total_packets;
4786 rx_ring->rx_stats.bytes += total_bytes;
4787 adapter->net_stats.rx_bytes += total_bytes;
4788 adapter->net_stats.rx_packets += total_packets;
4789 return cleaned;
4790 }
4791
4792 /**
4793 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4794 * @adapter: address of board private structure
4795 **/
4796 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4797 int cleaned_count)
4798 {
4799 struct igb_adapter *adapter = rx_ring->adapter;
4800 struct net_device *netdev = adapter->netdev;
4801 struct pci_dev *pdev = adapter->pdev;
4802 union e1000_adv_rx_desc *rx_desc;
4803 struct igb_buffer *buffer_info;
4804 struct sk_buff *skb;
4805 unsigned int i;
4806 int bufsz;
4807
4808 i = rx_ring->next_to_use;
4809 buffer_info = &rx_ring->buffer_info[i];
4810
4811 if (adapter->rx_ps_hdr_size)
4812 bufsz = adapter->rx_ps_hdr_size;
4813 else
4814 bufsz = adapter->rx_buffer_len;
4815
4816 while (cleaned_count--) {
4817 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4818
4819 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4820 if (!buffer_info->page) {
4821 buffer_info->page = alloc_page(GFP_ATOMIC);
4822 if (!buffer_info->page) {
4823 adapter->alloc_rx_buff_failed++;
4824 goto no_buffers;
4825 }
4826 buffer_info->page_offset = 0;
4827 } else {
4828 buffer_info->page_offset ^= PAGE_SIZE / 2;
4829 }
4830 buffer_info->page_dma =
4831 pci_map_page(pdev, buffer_info->page,
4832 buffer_info->page_offset,
4833 PAGE_SIZE / 2,
4834 PCI_DMA_FROMDEVICE);
4835 }
4836
4837 if (!buffer_info->skb) {
4838 skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
4839 if (!skb) {
4840 adapter->alloc_rx_buff_failed++;
4841 goto no_buffers;
4842 }
4843
4844 /* Make buffer alignment 2 beyond a 16 byte boundary
4845 * this will result in a 16 byte aligned IP header after
4846 * the 14 byte MAC header is removed
4847 */
4848 skb_reserve(skb, NET_IP_ALIGN);
4849
4850 buffer_info->skb = skb;
4851 buffer_info->dma = pci_map_single(pdev, skb->data,
4852 bufsz,
4853 PCI_DMA_FROMDEVICE);
4854 }
4855 /* Refresh the desc even if buffer_addrs didn't change because
4856 * each write-back erases this info. */
4857 if (adapter->rx_ps_hdr_size) {
4858 rx_desc->read.pkt_addr =
4859 cpu_to_le64(buffer_info->page_dma);
4860 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4861 } else {
4862 rx_desc->read.pkt_addr =
4863 cpu_to_le64(buffer_info->dma);
4864 rx_desc->read.hdr_addr = 0;
4865 }
4866
4867 i++;
4868 if (i == rx_ring->count)
4869 i = 0;
4870 buffer_info = &rx_ring->buffer_info[i];
4871 }
4872
4873 no_buffers:
4874 if (rx_ring->next_to_use != i) {
4875 rx_ring->next_to_use = i;
4876 if (i == 0)
4877 i = (rx_ring->count - 1);
4878 else
4879 i--;
4880
4881 /* Force memory writes to complete before letting h/w
4882 * know there are new descriptors to fetch. (Only
4883 * applicable for weak-ordered memory model archs,
4884 * such as IA-64). */
4885 wmb();
4886 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4887 }
4888 }
4889
4890 /**
4891 * igb_mii_ioctl -
4892 * @netdev:
4893 * @ifreq:
4894 * @cmd:
4895 **/
4896 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4897 {
4898 struct igb_adapter *adapter = netdev_priv(netdev);
4899 struct mii_ioctl_data *data = if_mii(ifr);
4900
4901 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4902 return -EOPNOTSUPP;
4903
4904 switch (cmd) {
4905 case SIOCGMIIPHY:
4906 data->phy_id = adapter->hw.phy.addr;
4907 break;
4908 case SIOCGMIIREG:
4909 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4910 &data->val_out))
4911 return -EIO;
4912 break;
4913 case SIOCSMIIREG:
4914 default:
4915 return -EOPNOTSUPP;
4916 }
4917 return 0;
4918 }
4919
4920 /**
4921 * igb_hwtstamp_ioctl - control hardware time stamping
4922 * @netdev:
4923 * @ifreq:
4924 * @cmd:
4925 *
4926 * Outgoing time stamping can be enabled and disabled. Play nice and
4927 * disable it when requested, although it shouldn't case any overhead
4928 * when no packet needs it. At most one packet in the queue may be
4929 * marked for time stamping, otherwise it would be impossible to tell
4930 * for sure to which packet the hardware time stamp belongs.
4931 *
4932 * Incoming time stamping has to be configured via the hardware
4933 * filters. Not all combinations are supported, in particular event
4934 * type has to be specified. Matching the kind of event packet is
4935 * not supported, with the exception of "all V2 events regardless of
4936 * level 2 or 4".
4937 *
4938 **/
4939 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4940 struct ifreq *ifr, int cmd)
4941 {
4942 struct igb_adapter *adapter = netdev_priv(netdev);
4943 struct e1000_hw *hw = &adapter->hw;
4944 struct hwtstamp_config config;
4945 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4946 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4947 u32 tsync_rx_ctl_type = 0;
4948 u32 tsync_rx_cfg = 0;
4949 int is_l4 = 0;
4950 int is_l2 = 0;
4951 short port = 319; /* PTP */
4952 u32 regval;
4953
4954 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4955 return -EFAULT;
4956
4957 /* reserved for future extensions */
4958 if (config.flags)
4959 return -EINVAL;
4960
4961 switch (config.tx_type) {
4962 case HWTSTAMP_TX_OFF:
4963 tsync_tx_ctl_bit = 0;
4964 break;
4965 case HWTSTAMP_TX_ON:
4966 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4967 break;
4968 default:
4969 return -ERANGE;
4970 }
4971
4972 switch (config.rx_filter) {
4973 case HWTSTAMP_FILTER_NONE:
4974 tsync_rx_ctl_bit = 0;
4975 break;
4976 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4977 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4978 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4979 case HWTSTAMP_FILTER_ALL:
4980 /*
4981 * register TSYNCRXCFG must be set, therefore it is not
4982 * possible to time stamp both Sync and Delay_Req messages
4983 * => fall back to time stamping all packets
4984 */
4985 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4986 config.rx_filter = HWTSTAMP_FILTER_ALL;
4987 break;
4988 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4989 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4990 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4991 is_l4 = 1;
4992 break;
4993 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4994 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4995 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4996 is_l4 = 1;
4997 break;
4998 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4999 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5000 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5001 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5002 is_l2 = 1;
5003 is_l4 = 1;
5004 config.rx_filter = HWTSTAMP_FILTER_SOME;
5005 break;
5006 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5007 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5008 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5009 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5010 is_l2 = 1;
5011 is_l4 = 1;
5012 config.rx_filter = HWTSTAMP_FILTER_SOME;
5013 break;
5014 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5015 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5016 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5017 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5018 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5019 is_l2 = 1;
5020 break;
5021 default:
5022 return -ERANGE;
5023 }
5024
5025 /* enable/disable TX */
5026 regval = rd32(E1000_TSYNCTXCTL);
5027 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5028 wr32(E1000_TSYNCTXCTL, regval);
5029
5030 /* enable/disable RX, define which PTP packets are time stamped */
5031 regval = rd32(E1000_TSYNCRXCTL);
5032 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5033 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5034 wr32(E1000_TSYNCRXCTL, regval);
5035 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5036
5037 /*
5038 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5039 * (Ethertype to filter on)
5040 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5041 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5042 */
5043 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5044
5045 /* L4 Queue Filter[0]: only filter by source and destination port */
5046 wr32(E1000_SPQF0, htons(port));
5047 wr32(E1000_IMIREXT(0), is_l4 ?
5048 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5049 wr32(E1000_IMIR(0), is_l4 ?
5050 (htons(port)
5051 | (0<<16) /* immediate interrupt disabled */
5052 | 0 /* (1<<17) bit cleared: do not bypass
5053 destination port check */)
5054 : 0);
5055 wr32(E1000_FTQF0, is_l4 ?
5056 (0x11 /* UDP */
5057 | (1<<15) /* VF not compared */
5058 | (1<<27) /* Enable Timestamping */
5059 | (7<<28) /* only source port filter enabled,
5060 source/target address and protocol
5061 masked */)
5062 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5063 enabled */));
5064
5065 wrfl();
5066
5067 adapter->hwtstamp_config = config;
5068
5069 /* clear TX/RX time stamp registers, just to be sure */
5070 regval = rd32(E1000_TXSTMPH);
5071 regval = rd32(E1000_RXSTMPH);
5072
5073 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5074 -EFAULT : 0;
5075 }
5076
5077 /**
5078 * igb_ioctl -
5079 * @netdev:
5080 * @ifreq:
5081 * @cmd:
5082 **/
5083 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5084 {
5085 switch (cmd) {
5086 case SIOCGMIIPHY:
5087 case SIOCGMIIREG:
5088 case SIOCSMIIREG:
5089 return igb_mii_ioctl(netdev, ifr, cmd);
5090 case SIOCSHWTSTAMP:
5091 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
5092 default:
5093 return -EOPNOTSUPP;
5094 }
5095 }
5096
5097 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5098 {
5099 struct igb_adapter *adapter = hw->back;
5100 u16 cap_offset;
5101
5102 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5103 if (!cap_offset)
5104 return -E1000_ERR_CONFIG;
5105
5106 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5107
5108 return 0;
5109 }
5110
5111 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5112 {
5113 struct igb_adapter *adapter = hw->back;
5114 u16 cap_offset;
5115
5116 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5117 if (!cap_offset)
5118 return -E1000_ERR_CONFIG;
5119
5120 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5121
5122 return 0;
5123 }
5124
5125 static void igb_vlan_rx_register(struct net_device *netdev,
5126 struct vlan_group *grp)
5127 {
5128 struct igb_adapter *adapter = netdev_priv(netdev);
5129 struct e1000_hw *hw = &adapter->hw;
5130 u32 ctrl, rctl;
5131
5132 igb_irq_disable(adapter);
5133 adapter->vlgrp = grp;
5134
5135 if (grp) {
5136 /* enable VLAN tag insert/strip */
5137 ctrl = rd32(E1000_CTRL);
5138 ctrl |= E1000_CTRL_VME;
5139 wr32(E1000_CTRL, ctrl);
5140
5141 /* enable VLAN receive filtering */
5142 rctl = rd32(E1000_RCTL);
5143 rctl &= ~E1000_RCTL_CFIEN;
5144 wr32(E1000_RCTL, rctl);
5145 igb_update_mng_vlan(adapter);
5146 } else {
5147 /* disable VLAN tag insert/strip */
5148 ctrl = rd32(E1000_CTRL);
5149 ctrl &= ~E1000_CTRL_VME;
5150 wr32(E1000_CTRL, ctrl);
5151
5152 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5153 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5154 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5155 }
5156 }
5157
5158 igb_rlpml_set(adapter);
5159
5160 if (!test_bit(__IGB_DOWN, &adapter->state))
5161 igb_irq_enable(adapter);
5162 }
5163
5164 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5165 {
5166 struct igb_adapter *adapter = netdev_priv(netdev);
5167 struct e1000_hw *hw = &adapter->hw;
5168 int pf_id = adapter->vfs_allocated_count;
5169
5170 if ((hw->mng_cookie.status &
5171 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5172 (vid == adapter->mng_vlan_id))
5173 return;
5174
5175 /* add vid to vlvf if sr-iov is enabled,
5176 * if that fails add directly to filter table */
5177 if (igb_vlvf_set(adapter, vid, true, pf_id))
5178 igb_vfta_set(hw, vid, true);
5179
5180 }
5181
5182 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5183 {
5184 struct igb_adapter *adapter = netdev_priv(netdev);
5185 struct e1000_hw *hw = &adapter->hw;
5186 int pf_id = adapter->vfs_allocated_count;
5187
5188 igb_irq_disable(adapter);
5189 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5190
5191 if (!test_bit(__IGB_DOWN, &adapter->state))
5192 igb_irq_enable(adapter);
5193
5194 if ((adapter->hw.mng_cookie.status &
5195 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5196 (vid == adapter->mng_vlan_id)) {
5197 /* release control to f/w */
5198 igb_release_hw_control(adapter);
5199 return;
5200 }
5201
5202 /* remove vid from vlvf if sr-iov is enabled,
5203 * if not in vlvf remove from vfta */
5204 if (igb_vlvf_set(adapter, vid, false, pf_id))
5205 igb_vfta_set(hw, vid, false);
5206 }
5207
5208 static void igb_restore_vlan(struct igb_adapter *adapter)
5209 {
5210 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5211
5212 if (adapter->vlgrp) {
5213 u16 vid;
5214 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5215 if (!vlan_group_get_device(adapter->vlgrp, vid))
5216 continue;
5217 igb_vlan_rx_add_vid(adapter->netdev, vid);
5218 }
5219 }
5220 }
5221
5222 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5223 {
5224 struct e1000_mac_info *mac = &adapter->hw.mac;
5225
5226 mac->autoneg = 0;
5227
5228 switch (spddplx) {
5229 case SPEED_10 + DUPLEX_HALF:
5230 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5231 break;
5232 case SPEED_10 + DUPLEX_FULL:
5233 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5234 break;
5235 case SPEED_100 + DUPLEX_HALF:
5236 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5237 break;
5238 case SPEED_100 + DUPLEX_FULL:
5239 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5240 break;
5241 case SPEED_1000 + DUPLEX_FULL:
5242 mac->autoneg = 1;
5243 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5244 break;
5245 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5246 default:
5247 dev_err(&adapter->pdev->dev,
5248 "Unsupported Speed/Duplex configuration\n");
5249 return -EINVAL;
5250 }
5251 return 0;
5252 }
5253
5254 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5255 {
5256 struct net_device *netdev = pci_get_drvdata(pdev);
5257 struct igb_adapter *adapter = netdev_priv(netdev);
5258 struct e1000_hw *hw = &adapter->hw;
5259 u32 ctrl, rctl, status;
5260 u32 wufc = adapter->wol;
5261 #ifdef CONFIG_PM
5262 int retval = 0;
5263 #endif
5264
5265 netif_device_detach(netdev);
5266
5267 if (netif_running(netdev))
5268 igb_close(netdev);
5269
5270 igb_reset_interrupt_capability(adapter);
5271
5272 igb_free_queues(adapter);
5273
5274 #ifdef CONFIG_PM
5275 retval = pci_save_state(pdev);
5276 if (retval)
5277 return retval;
5278 #endif
5279
5280 status = rd32(E1000_STATUS);
5281 if (status & E1000_STATUS_LU)
5282 wufc &= ~E1000_WUFC_LNKC;
5283
5284 if (wufc) {
5285 igb_setup_rctl(adapter);
5286 igb_set_rx_mode(netdev);
5287
5288 /* turn on all-multi mode if wake on multicast is enabled */
5289 if (wufc & E1000_WUFC_MC) {
5290 rctl = rd32(E1000_RCTL);
5291 rctl |= E1000_RCTL_MPE;
5292 wr32(E1000_RCTL, rctl);
5293 }
5294
5295 ctrl = rd32(E1000_CTRL);
5296 /* advertise wake from D3Cold */
5297 #define E1000_CTRL_ADVD3WUC 0x00100000
5298 /* phy power management enable */
5299 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5300 ctrl |= E1000_CTRL_ADVD3WUC;
5301 wr32(E1000_CTRL, ctrl);
5302
5303 /* Allow time for pending master requests to run */
5304 igb_disable_pcie_master(&adapter->hw);
5305
5306 wr32(E1000_WUC, E1000_WUC_PME_EN);
5307 wr32(E1000_WUFC, wufc);
5308 } else {
5309 wr32(E1000_WUC, 0);
5310 wr32(E1000_WUFC, 0);
5311 }
5312
5313 *enable_wake = wufc || adapter->en_mng_pt;
5314 if (!*enable_wake)
5315 igb_shutdown_serdes_link_82575(hw);
5316
5317 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5318 * would have already happened in close and is redundant. */
5319 igb_release_hw_control(adapter);
5320
5321 pci_disable_device(pdev);
5322
5323 return 0;
5324 }
5325
5326 #ifdef CONFIG_PM
5327 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5328 {
5329 int retval;
5330 bool wake;
5331
5332 retval = __igb_shutdown(pdev, &wake);
5333 if (retval)
5334 return retval;
5335
5336 if (wake) {
5337 pci_prepare_to_sleep(pdev);
5338 } else {
5339 pci_wake_from_d3(pdev, false);
5340 pci_set_power_state(pdev, PCI_D3hot);
5341 }
5342
5343 return 0;
5344 }
5345
5346 static int igb_resume(struct pci_dev *pdev)
5347 {
5348 struct net_device *netdev = pci_get_drvdata(pdev);
5349 struct igb_adapter *adapter = netdev_priv(netdev);
5350 struct e1000_hw *hw = &adapter->hw;
5351 u32 err;
5352
5353 pci_set_power_state(pdev, PCI_D0);
5354 pci_restore_state(pdev);
5355
5356 err = pci_enable_device_mem(pdev);
5357 if (err) {
5358 dev_err(&pdev->dev,
5359 "igb: Cannot enable PCI device from suspend\n");
5360 return err;
5361 }
5362 pci_set_master(pdev);
5363
5364 pci_enable_wake(pdev, PCI_D3hot, 0);
5365 pci_enable_wake(pdev, PCI_D3cold, 0);
5366
5367 igb_set_interrupt_capability(adapter);
5368
5369 if (igb_alloc_queues(adapter)) {
5370 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5371 return -ENOMEM;
5372 }
5373
5374 /* e1000_power_up_phy(adapter); */
5375
5376 igb_reset(adapter);
5377
5378 /* let the f/w know that the h/w is now under the control of the
5379 * driver. */
5380 igb_get_hw_control(adapter);
5381
5382 wr32(E1000_WUS, ~0);
5383
5384 if (netif_running(netdev)) {
5385 err = igb_open(netdev);
5386 if (err)
5387 return err;
5388 }
5389
5390 netif_device_attach(netdev);
5391
5392 return 0;
5393 }
5394 #endif
5395
5396 static void igb_shutdown(struct pci_dev *pdev)
5397 {
5398 bool wake;
5399
5400 __igb_shutdown(pdev, &wake);
5401
5402 if (system_state == SYSTEM_POWER_OFF) {
5403 pci_wake_from_d3(pdev, wake);
5404 pci_set_power_state(pdev, PCI_D3hot);
5405 }
5406 }
5407
5408 #ifdef CONFIG_NET_POLL_CONTROLLER
5409 /*
5410 * Polling 'interrupt' - used by things like netconsole to send skbs
5411 * without having to re-enable interrupts. It's not called while
5412 * the interrupt routine is executing.
5413 */
5414 static void igb_netpoll(struct net_device *netdev)
5415 {
5416 struct igb_adapter *adapter = netdev_priv(netdev);
5417 struct e1000_hw *hw = &adapter->hw;
5418 int i;
5419
5420 if (!adapter->msix_entries) {
5421 igb_irq_disable(adapter);
5422 napi_schedule(&adapter->rx_ring[0].napi);
5423 return;
5424 }
5425
5426 for (i = 0; i < adapter->num_tx_queues; i++) {
5427 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5428 wr32(E1000_EIMC, tx_ring->eims_value);
5429 igb_clean_tx_irq(tx_ring);
5430 wr32(E1000_EIMS, tx_ring->eims_value);
5431 }
5432
5433 for (i = 0; i < adapter->num_rx_queues; i++) {
5434 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5435 wr32(E1000_EIMC, rx_ring->eims_value);
5436 napi_schedule(&rx_ring->napi);
5437 }
5438 }
5439 #endif /* CONFIG_NET_POLL_CONTROLLER */
5440
5441 /**
5442 * igb_io_error_detected - called when PCI error is detected
5443 * @pdev: Pointer to PCI device
5444 * @state: The current pci connection state
5445 *
5446 * This function is called after a PCI bus error affecting
5447 * this device has been detected.
5448 */
5449 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5450 pci_channel_state_t state)
5451 {
5452 struct net_device *netdev = pci_get_drvdata(pdev);
5453 struct igb_adapter *adapter = netdev_priv(netdev);
5454
5455 netif_device_detach(netdev);
5456
5457 if (state == pci_channel_io_perm_failure)
5458 return PCI_ERS_RESULT_DISCONNECT;
5459
5460 if (netif_running(netdev))
5461 igb_down(adapter);
5462 pci_disable_device(pdev);
5463
5464 /* Request a slot slot reset. */
5465 return PCI_ERS_RESULT_NEED_RESET;
5466 }
5467
5468 /**
5469 * igb_io_slot_reset - called after the pci bus has been reset.
5470 * @pdev: Pointer to PCI device
5471 *
5472 * Restart the card from scratch, as if from a cold-boot. Implementation
5473 * resembles the first-half of the igb_resume routine.
5474 */
5475 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5476 {
5477 struct net_device *netdev = pci_get_drvdata(pdev);
5478 struct igb_adapter *adapter = netdev_priv(netdev);
5479 struct e1000_hw *hw = &adapter->hw;
5480 pci_ers_result_t result;
5481 int err;
5482
5483 if (pci_enable_device_mem(pdev)) {
5484 dev_err(&pdev->dev,
5485 "Cannot re-enable PCI device after reset.\n");
5486 result = PCI_ERS_RESULT_DISCONNECT;
5487 } else {
5488 pci_set_master(pdev);
5489 pci_restore_state(pdev);
5490
5491 pci_enable_wake(pdev, PCI_D3hot, 0);
5492 pci_enable_wake(pdev, PCI_D3cold, 0);
5493
5494 igb_reset(adapter);
5495 wr32(E1000_WUS, ~0);
5496 result = PCI_ERS_RESULT_RECOVERED;
5497 }
5498
5499 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5500 if (err) {
5501 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5502 "failed 0x%0x\n", err);
5503 /* non-fatal, continue */
5504 }
5505
5506 return result;
5507 }
5508
5509 /**
5510 * igb_io_resume - called when traffic can start flowing again.
5511 * @pdev: Pointer to PCI device
5512 *
5513 * This callback is called when the error recovery driver tells us that
5514 * its OK to resume normal operation. Implementation resembles the
5515 * second-half of the igb_resume routine.
5516 */
5517 static void igb_io_resume(struct pci_dev *pdev)
5518 {
5519 struct net_device *netdev = pci_get_drvdata(pdev);
5520 struct igb_adapter *adapter = netdev_priv(netdev);
5521
5522 if (netif_running(netdev)) {
5523 if (igb_up(adapter)) {
5524 dev_err(&pdev->dev, "igb_up failed after reset\n");
5525 return;
5526 }
5527 }
5528
5529 netif_device_attach(netdev);
5530
5531 /* let the f/w know that the h/w is now under the control of the
5532 * driver. */
5533 igb_get_hw_control(adapter);
5534 }
5535
5536 static int igb_set_vf_mac(struct igb_adapter *adapter,
5537 int vf, unsigned char *mac_addr)
5538 {
5539 struct e1000_hw *hw = &adapter->hw;
5540 /* VF MAC addresses start at end of receive addresses and moves
5541 * torwards the first, as a result a collision should not be possible */
5542 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5543
5544 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5545
5546 igb_rar_set(hw, mac_addr, rar_entry);
5547 igb_set_rah_pool(hw, vf, rar_entry);
5548
5549 return 0;
5550 }
5551
5552 static void igb_vmm_control(struct igb_adapter *adapter)
5553 {
5554 struct e1000_hw *hw = &adapter->hw;
5555 u32 reg_data;
5556
5557 if (!adapter->vfs_allocated_count)
5558 return;
5559
5560 /* VF's need PF reset indication before they
5561 * can send/receive mail */
5562 reg_data = rd32(E1000_CTRL_EXT);
5563 reg_data |= E1000_CTRL_EXT_PFRSTD;
5564 wr32(E1000_CTRL_EXT, reg_data);
5565
5566 igb_vmdq_set_loopback_pf(hw, true);
5567 igb_vmdq_set_replication_pf(hw, true);
5568 }
5569
5570 /* igb_main.c */
Linux MOXA ART SoC ARM port