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init from v2.6.32.60
[mach-moxart.git] / drivers / net / ixgbe / ixgbe_82599.c
blob23e521f7e89f0b9108a742966d871468f67d4aef
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
40
41 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg,
50 bool autoneg_wait_to_complete);
51 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
52 ixgbe_link_speed *speed,
53 bool *autoneg);
54 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
58 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
59
60 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
61 {
62 struct ixgbe_mac_info *mac = &hw->mac;
63 if (hw->phy.multispeed_fiber) {
64 /* Set up dual speed SFP+ support */
65 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
66 } else {
67 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
68 }
69 }
70
71 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
72 {
73 s32 ret_val = 0;
74 u16 list_offset, data_offset, data_value;
75
76 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
77 ixgbe_init_mac_link_ops_82599(hw);
78
79 hw->phy.ops.reset = NULL;
80
81 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
82 &data_offset);
83
84 if (ret_val != 0)
85 goto setup_sfp_out;
86
87 /* PHY config will finish before releasing the semaphore */
88 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
89 if (ret_val != 0) {
90 ret_val = IXGBE_ERR_SWFW_SYNC;
91 goto setup_sfp_out;
92 }
93
94 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
95 while (data_value != 0xffff) {
96 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
97 IXGBE_WRITE_FLUSH(hw);
98 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
99 }
100 /* Now restart DSP by setting Restart_AN */
101 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
102 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
103
104 /* Release the semaphore */
105 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
106 /* Delay obtaining semaphore again to allow FW access */
107 msleep(hw->eeprom.semaphore_delay);
108 }
109
110 setup_sfp_out:
111 return ret_val;
112 }
113
114 /**
115 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
116 * @hw: pointer to hardware structure
117 *
118 * Read PCIe configuration space, and get the MSI-X vector count from
119 * the capabilities table.
120 **/
121 static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
122 {
123 struct ixgbe_adapter *adapter = hw->back;
124 u16 msix_count;
125 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
126 &msix_count);
127 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
128
129 /* MSI-X count is zero-based in HW, so increment to give proper value */
130 msix_count++;
131
132 return msix_count;
133 }
134
135 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
136 {
137 struct ixgbe_mac_info *mac = &hw->mac;
138
139 ixgbe_init_mac_link_ops_82599(hw);
140
141 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
142 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
143 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
144 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
145 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
146 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
147
148 return 0;
149 }
150
151 /**
152 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
153 * @hw: pointer to hardware structure
154 *
155 * Initialize any function pointers that were not able to be
156 * set during get_invariants because the PHY/SFP type was
157 * not known. Perform the SFP init if necessary.
158 *
159 **/
160 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
161 {
162 struct ixgbe_mac_info *mac = &hw->mac;
163 struct ixgbe_phy_info *phy = &hw->phy;
164 s32 ret_val = 0;
165
166 /* Identify the PHY or SFP module */
167 ret_val = phy->ops.identify(hw);
168
169 /* Setup function pointers based on detected SFP module and speeds */
170 ixgbe_init_mac_link_ops_82599(hw);
171
172 /* If copper media, overwrite with copper function pointers */
173 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
174 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
175 mac->ops.get_link_capabilities =
176 &ixgbe_get_copper_link_capabilities_82599;
177 }
178
179 /* Set necessary function pointers based on phy type */
180 switch (hw->phy.type) {
181 case ixgbe_phy_tn:
182 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
183 phy->ops.get_firmware_version =
184 &ixgbe_get_phy_firmware_version_tnx;
185 break;
186 default:
187 break;
188 }
189
190 return ret_val;
191 }
192
193 /**
194 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
195 * @hw: pointer to hardware structure
196 * @speed: pointer to link speed
197 * @negotiation: true when autoneg or autotry is enabled
198 *
199 * Determines the link capabilities by reading the AUTOC register.
200 **/
201 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
202 ixgbe_link_speed *speed,
203 bool *negotiation)
204 {
205 s32 status = 0;
206 u32 autoc = 0;
207
208 /*
209 * Determine link capabilities based on the stored value of AUTOC,
210 * which represents EEPROM defaults. If AUTOC value has not been
211 * stored, use the current register value.
212 */
213 if (hw->mac.orig_link_settings_stored)
214 autoc = hw->mac.orig_autoc;
215 else
216 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
217
218 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
219 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
220 *speed = IXGBE_LINK_SPEED_1GB_FULL;
221 *negotiation = false;
222 break;
223
224 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
225 *speed = IXGBE_LINK_SPEED_10GB_FULL;
226 *negotiation = false;
227 break;
228
229 case IXGBE_AUTOC_LMS_1G_AN:
230 *speed = IXGBE_LINK_SPEED_1GB_FULL;
231 *negotiation = true;
232 break;
233
234 case IXGBE_AUTOC_LMS_10G_SERIAL:
235 *speed = IXGBE_LINK_SPEED_10GB_FULL;
236 *negotiation = false;
237 break;
238
239 case IXGBE_AUTOC_LMS_KX4_KX_KR:
240 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
241 *speed = IXGBE_LINK_SPEED_UNKNOWN;
242 if (autoc & IXGBE_AUTOC_KR_SUPP)
243 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
244 if (autoc & IXGBE_AUTOC_KX4_SUPP)
245 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
246 if (autoc & IXGBE_AUTOC_KX_SUPP)
247 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
248 *negotiation = true;
249 break;
250
251 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
252 *speed = IXGBE_LINK_SPEED_100_FULL;
253 if (autoc & IXGBE_AUTOC_KR_SUPP)
254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
255 if (autoc & IXGBE_AUTOC_KX4_SUPP)
256 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
257 if (autoc & IXGBE_AUTOC_KX_SUPP)
258 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = true;
260 break;
261
262 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
263 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
264 *negotiation = false;
265 break;
266
267 default:
268 status = IXGBE_ERR_LINK_SETUP;
269 goto out;
270 break;
271 }
272
273 if (hw->phy.multispeed_fiber) {
274 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
275 IXGBE_LINK_SPEED_1GB_FULL;
276 *negotiation = true;
277 }
278
279 out:
280 return status;
281 }
282
283 /**
284 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
285 * @hw: pointer to hardware structure
286 * @speed: pointer to link speed
287 * @autoneg: boolean auto-negotiation value
288 *
289 * Determines the link capabilities by reading the AUTOC register.
290 **/
291 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
292 ixgbe_link_speed *speed,
293 bool *autoneg)
294 {
295 s32 status = IXGBE_ERR_LINK_SETUP;
296 u16 speed_ability;
297
298 *speed = 0;
299 *autoneg = true;
300
301 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
302 &speed_ability);
303
304 if (status == 0) {
305 if (speed_ability & MDIO_SPEED_10G)
306 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
307 if (speed_ability & MDIO_PMA_SPEED_1000)
308 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
309 }
310
311 return status;
312 }
313
314 /**
315 * ixgbe_get_media_type_82599 - Get media type
316 * @hw: pointer to hardware structure
317 *
318 * Returns the media type (fiber, copper, backplane)
319 **/
320 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
321 {
322 enum ixgbe_media_type media_type;
323
324 /* Detect if there is a copper PHY attached. */
325 if (hw->phy.type == ixgbe_phy_cu_unknown ||
326 hw->phy.type == ixgbe_phy_tn) {
327 media_type = ixgbe_media_type_copper;
328 goto out;
329 }
330
331 switch (hw->device_id) {
332 case IXGBE_DEV_ID_82599_KX4:
333 case IXGBE_DEV_ID_82599_KX4_MEZZ:
334 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
335 case IXGBE_DEV_ID_82599_KR:
336 case IXGBE_DEV_ID_82599_XAUI_LOM:
337 /* Default device ID is mezzanine card KX/KX4 */
338 media_type = ixgbe_media_type_backplane;
339 break;
340 case IXGBE_DEV_ID_82599_SFP:
341 case IXGBE_DEV_ID_82599_SFP_EM:
342 media_type = ixgbe_media_type_fiber;
343 break;
344 case IXGBE_DEV_ID_82599_CX4:
345 media_type = ixgbe_media_type_cx4;
346 break;
347 default:
348 media_type = ixgbe_media_type_unknown;
349 break;
350 }
351 out:
352 return media_type;
353 }
354
355 /**
356 * ixgbe_start_mac_link_82599 - Setup MAC link settings
357 * @hw: pointer to hardware structure
358 * @autoneg_wait_to_complete: true when waiting for completion is needed
359 *
360 * Configures link settings based on values in the ixgbe_hw struct.
361 * Restarts the link. Performs autonegotiation if needed.
362 **/
363 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
364 bool autoneg_wait_to_complete)
365 {
366 u32 autoc_reg;
367 u32 links_reg;
368 u32 i;
369 s32 status = 0;
370
371 /* Restart link */
372 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
373 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
374 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
375
376 /* Only poll for autoneg to complete if specified to do so */
377 if (autoneg_wait_to_complete) {
378 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
379 IXGBE_AUTOC_LMS_KX4_KX_KR ||
380 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
381 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
382 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
383 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
384 links_reg = 0; /* Just in case Autoneg time = 0 */
385 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
386 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
387 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
388 break;
389 msleep(100);
390 }
391 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
392 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
393 hw_dbg(hw, "Autoneg did not complete.\n");
394 }
395 }
396 }
397
398 /* Add delay to filter out noises during initial link setup */
399 msleep(50);
400
401 return status;
402 }
403
404 /**
405 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
406 * @hw: pointer to hardware structure
407 * @speed: new link speed
408 * @autoneg: true if autonegotiation enabled
409 * @autoneg_wait_to_complete: true when waiting for completion is needed
410 *
411 * Set the link speed in the AUTOC register and restarts link.
412 **/
413 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
414 ixgbe_link_speed speed,
415 bool autoneg,
416 bool autoneg_wait_to_complete)
417 {
418 s32 status = 0;
419 ixgbe_link_speed phy_link_speed;
420 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
421 u32 speedcnt = 0;
422 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
423 bool link_up = false;
424 bool negotiation;
425 int i;
426
427 /* Mask off requested but non-supported speeds */
428 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
429 speed &= phy_link_speed;
430
431 /*
432 * When the driver changes the link speeds that it can support,
433 * it sets autotry_restart to true to indicate that we need to
434 * initiate a new autotry session with the link partner. To do
435 * so, we set the speed then disable and re-enable the tx laser, to
436 * alert the link partner that it also needs to restart autotry on its
437 * end. This is consistent with true clause 37 autoneg, which also
438 * involves a loss of signal.
439 */
440
441 /*
442 * Try each speed one by one, highest priority first. We do this in
443 * software because 10gb fiber doesn't support speed autonegotiation.
444 */
445 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
446 speedcnt++;
447 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
448
449 /* If we already have link at this speed, just jump out */
450 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
451
452 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
453 goto out;
454
455 /* Set the module link speed */
456 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
457 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
458
459 /* Allow module to change analog characteristics (1G->10G) */
460 msleep(40);
461
462 status = ixgbe_setup_mac_link_82599(hw,
463 IXGBE_LINK_SPEED_10GB_FULL,
464 autoneg,
465 autoneg_wait_to_complete);
466 if (status != 0)
467 return status;
468
469 /* Flap the tx laser if it has not already been done */
470 if (hw->mac.autotry_restart) {
471 /* Disable tx laser; allow 100us to go dark per spec */
472 esdp_reg |= IXGBE_ESDP_SDP3;
473 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
474 udelay(100);
475
476 /* Enable tx laser; allow 2ms to light up per spec */
477 esdp_reg &= ~IXGBE_ESDP_SDP3;
478 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
479 msleep(2);
480
481 hw->mac.autotry_restart = false;
482 }
483
484 /* The controller may take up to 500ms at 10g to acquire link */
485 for (i = 0; i < 5; i++) {
486 /* Wait for the link partner to also set speed */
487 msleep(100);
488
489 /* If we have link, just jump out */
490 hw->mac.ops.check_link(hw, &phy_link_speed,
491 &link_up, false);
492 if (link_up)
493 goto out;
494 }
495 }
496
497 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
498 speedcnt++;
499 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
500 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
501
502 /* If we already have link at this speed, just jump out */
503 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
504
505 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
506 goto out;
507
508 /* Set the module link speed */
509 esdp_reg &= ~IXGBE_ESDP_SDP5;
510 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
511 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
512
513 /* Allow module to change analog characteristics (10G->1G) */
514 msleep(40);
515
516 status = ixgbe_setup_mac_link_82599(hw,
517 IXGBE_LINK_SPEED_1GB_FULL,
518 autoneg,
519 autoneg_wait_to_complete);
520 if (status != 0)
521 return status;
522
523 /* Flap the tx laser if it has not already been done */
524 if (hw->mac.autotry_restart) {
525 /* Disable tx laser; allow 100us to go dark per spec */
526 esdp_reg |= IXGBE_ESDP_SDP3;
527 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
528 udelay(100);
529
530 /* Enable tx laser; allow 2ms to light up per spec */
531 esdp_reg &= ~IXGBE_ESDP_SDP3;
532 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
533 msleep(2);
534
535 hw->mac.autotry_restart = false;
536 }
537
538 /* Wait for the link partner to also set speed */
539 msleep(100);
540
541 /* If we have link, just jump out */
542 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
543 if (link_up)
544 goto out;
545 }
546
547 /*
548 * We didn't get link. Configure back to the highest speed we tried,
549 * (if there was more than one). We call ourselves back with just the
550 * single highest speed that the user requested.
551 */
552 if (speedcnt > 1)
553 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
554 highest_link_speed,
555 autoneg,
556 autoneg_wait_to_complete);
557
558 out:
559 /* Set autoneg_advertised value based on input link speed */
560 hw->phy.autoneg_advertised = 0;
561
562 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
563 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
564
565 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
566 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
567
568 return status;
569 }
570
571 /**
572 * ixgbe_check_mac_link_82599 - Determine link and speed status
573 * @hw: pointer to hardware structure
574 * @speed: pointer to link speed
575 * @link_up: true when link is up
576 * @link_up_wait_to_complete: bool used to wait for link up or not
577 *
578 * Reads the links register to determine if link is up and the current speed
579 **/
580 static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
581 ixgbe_link_speed *speed,
582 bool *link_up,
583 bool link_up_wait_to_complete)
584 {
585 u32 links_reg;
586 u32 i;
587
588 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
589 if (link_up_wait_to_complete) {
590 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
591 if (links_reg & IXGBE_LINKS_UP) {
592 *link_up = true;
593 break;
594 } else {
595 *link_up = false;
596 }
597 msleep(100);
598 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
599 }
600 } else {
601 if (links_reg & IXGBE_LINKS_UP)
602 *link_up = true;
603 else
604 *link_up = false;
605 }
606
607 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
608 IXGBE_LINKS_SPEED_10G_82599)
609 *speed = IXGBE_LINK_SPEED_10GB_FULL;
610 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
611 IXGBE_LINKS_SPEED_1G_82599)
612 *speed = IXGBE_LINK_SPEED_1GB_FULL;
613 else
614 *speed = IXGBE_LINK_SPEED_100_FULL;
615
616 /* if link is down, zero out the current_mode */
617 if (*link_up == false) {
618 hw->fc.current_mode = ixgbe_fc_none;
619 hw->fc.fc_was_autonegged = false;
620 }
621
622 return 0;
623 }
624
625 /**
626 * ixgbe_setup_mac_link_82599 - Set MAC link speed
627 * @hw: pointer to hardware structure
628 * @speed: new link speed
629 * @autoneg: true if autonegotiation enabled
630 * @autoneg_wait_to_complete: true when waiting for completion is needed
631 *
632 * Set the link speed in the AUTOC register and restarts link.
633 **/
634 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
635 ixgbe_link_speed speed, bool autoneg,
636 bool autoneg_wait_to_complete)
637 {
638 s32 status = 0;
639 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
640 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
641 u32 start_autoc = autoc;
642 u32 orig_autoc = 0;
643 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
644 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
645 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
646 u32 links_reg;
647 u32 i;
648 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
649
650 /* Check to see if speed passed in is supported. */
651 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
652 speed &= link_capabilities;
653
654 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
655 status = IXGBE_ERR_LINK_SETUP;
656 goto out;
657 }
658
659 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
660 if (hw->mac.orig_link_settings_stored)
661 orig_autoc = hw->mac.orig_autoc;
662 else
663 orig_autoc = autoc;
664
665
666 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
667 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
668 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
669 /* Set KX4/KX/KR support according to speed requested */
670 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
671 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
672 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
673 autoc |= IXGBE_AUTOC_KX4_SUPP;
674 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
675 autoc |= IXGBE_AUTOC_KR_SUPP;
676 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
677 autoc |= IXGBE_AUTOC_KX_SUPP;
678 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
679 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
680 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
681 /* Switch from 1G SFI to 10G SFI if requested */
682 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
683 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
684 autoc &= ~IXGBE_AUTOC_LMS_MASK;
685 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
686 }
687 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
688 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
689 /* Switch from 10G SFI to 1G SFI if requested */
690 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
691 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
692 autoc &= ~IXGBE_AUTOC_LMS_MASK;
693 if (autoneg)
694 autoc |= IXGBE_AUTOC_LMS_1G_AN;
695 else
696 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
697 }
698 }
699
700 if (autoc != start_autoc) {
701 /* Restart link */
702 autoc |= IXGBE_AUTOC_AN_RESTART;
703 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
704
705 /* Only poll for autoneg to complete if specified to do so */
706 if (autoneg_wait_to_complete) {
707 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
708 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
709 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
710 links_reg = 0; /*Just in case Autoneg time=0*/
711 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
712 links_reg =
713 IXGBE_READ_REG(hw, IXGBE_LINKS);
714 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
715 break;
716 msleep(100);
717 }
718 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
719 status =
720 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
721 hw_dbg(hw, "Autoneg did not "
722 "complete.\n");
723 }
724 }
725 }
726
727 /* Add delay to filter out noises during initial link setup */
728 msleep(50);
729 }
730
731 out:
732 return status;
733 }
734
735 /**
736 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
737 * @hw: pointer to hardware structure
738 * @speed: new link speed
739 * @autoneg: true if autonegotiation enabled
740 * @autoneg_wait_to_complete: true if waiting is needed to complete
741 *
742 * Restarts link on PHY and MAC based on settings passed in.
743 **/
744 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
745 ixgbe_link_speed speed,
746 bool autoneg,
747 bool autoneg_wait_to_complete)
748 {
749 s32 status;
750
751 /* Setup the PHY according to input speed */
752 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
753 autoneg_wait_to_complete);
754 /* Set up MAC */
755 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
756
757 return status;
758 }
759
760 /**
761 * ixgbe_reset_hw_82599 - Perform hardware reset
762 * @hw: pointer to hardware structure
763 *
764 * Resets the hardware by resetting the transmit and receive units, masks
765 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
766 * reset.
767 **/
768 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
769 {
770 s32 status = 0;
771 u32 ctrl, ctrl_ext;
772 u32 i;
773 u32 autoc;
774 u32 autoc2;
775
776 /* Call adapter stop to disable tx/rx and clear interrupts */
777 hw->mac.ops.stop_adapter(hw);
778
779 /* PHY ops must be identified and initialized prior to reset */
780
781 /* Init PHY and function pointers, perform SFP setup */
782 status = hw->phy.ops.init(hw);
783
784 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
785 goto reset_hw_out;
786
787 /* Setup SFP module if there is one present. */
788 if (hw->phy.sfp_setup_needed) {
789 status = hw->mac.ops.setup_sfp(hw);
790 hw->phy.sfp_setup_needed = false;
791 }
792
793 /* Reset PHY */
794 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
795 hw->phy.ops.reset(hw);
796
797 /*
798 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
799 * access and verify no pending requests before reset
800 */
801 status = ixgbe_disable_pcie_master(hw);
802 if (status != 0) {
803 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
804 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
805 }
806
807 /*
808 * Issue global reset to the MAC. This needs to be a SW reset.
809 * If link reset is used, it might reset the MAC when mng is using it
810 */
811 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
812 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
813 IXGBE_WRITE_FLUSH(hw);
814
815 /* Poll for reset bit to self-clear indicating reset is complete */
816 for (i = 0; i < 10; i++) {
817 udelay(1);
818 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
819 if (!(ctrl & IXGBE_CTRL_RST))
820 break;
821 }
822 if (ctrl & IXGBE_CTRL_RST) {
823 status = IXGBE_ERR_RESET_FAILED;
824 hw_dbg(hw, "Reset polling failed to complete.\n");
825 }
826 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
827 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
828 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
829 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
830
831 msleep(50);
832
833
834
835 /*
836 * Store the original AUTOC/AUTOC2 values if they have not been
837 * stored off yet. Otherwise restore the stored original
838 * values since the reset operation sets back to defaults.
839 */
840 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
841 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
842 if (hw->mac.orig_link_settings_stored == false) {
843 hw->mac.orig_autoc = autoc;
844 hw->mac.orig_autoc2 = autoc2;
845 hw->mac.orig_link_settings_stored = true;
846 } else {
847 if (autoc != hw->mac.orig_autoc)
848 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
849 IXGBE_AUTOC_AN_RESTART));
850
851 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
852 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
853 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
854 autoc2 |= (hw->mac.orig_autoc2 &
855 IXGBE_AUTOC2_UPPER_MASK);
856 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
857 }
858 }
859
860 /*
861 * Store MAC address from RAR0, clear receive address registers, and
862 * clear the multicast table. Also reset num_rar_entries to 128,
863 * since we modify this value when programming the SAN MAC address.
864 */
865 hw->mac.num_rar_entries = 128;
866 hw->mac.ops.init_rx_addrs(hw);
867
868 /* Store the permanent mac address */
869 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
870
871 /* Store the permanent SAN mac address */
872 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
873
874 /* Add the SAN MAC address to the RAR only if it's a valid address */
875 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
876 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
877 hw->mac.san_addr, 0, IXGBE_RAH_AV);
878
879 /* Reserve the last RAR for the SAN MAC address */
880 hw->mac.num_rar_entries--;
881 }
882
883 reset_hw_out:
884 return status;
885 }
886
887 /**
888 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
889 * @hw: pointer to hardware struct
890 * @rar: receive address register index to disassociate
891 * @vmdq: VMDq pool index to remove from the rar
892 **/
893 static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
894 {
895 u32 mpsar_lo, mpsar_hi;
896 u32 rar_entries = hw->mac.num_rar_entries;
897
898 if (rar < rar_entries) {
899 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
900 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
901
902 if (!mpsar_lo && !mpsar_hi)
903 goto done;
904
905 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
906 if (mpsar_lo) {
907 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
908 mpsar_lo = 0;
909 }
910 if (mpsar_hi) {
911 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
912 mpsar_hi = 0;
913 }
914 } else if (vmdq < 32) {
915 mpsar_lo &= ~(1 << vmdq);
916 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
917 } else {
918 mpsar_hi &= ~(1 << (vmdq - 32));
919 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
920 }
921
922 /* was that the last pool using this rar? */
923 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
924 hw->mac.ops.clear_rar(hw, rar);
925 } else {
926 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
927 }
928
929 done:
930 return 0;
931 }
932
933 /**
934 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
935 * @hw: pointer to hardware struct
936 * @rar: receive address register index to associate with a VMDq index
937 * @vmdq: VMDq pool index
938 **/
939 static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
940 {
941 u32 mpsar;
942 u32 rar_entries = hw->mac.num_rar_entries;
943
944 if (rar < rar_entries) {
945 if (vmdq < 32) {
946 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
947 mpsar |= 1 << vmdq;
948 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
949 } else {
950 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
951 mpsar |= 1 << (vmdq - 32);
952 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
953 }
954 } else {
955 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
956 }
957 return 0;
958 }
959
960 /**
961 * ixgbe_set_vfta_82599 - Set VLAN filter table
962 * @hw: pointer to hardware structure
963 * @vlan: VLAN id to write to VLAN filter
964 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
965 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
966 *
967 * Turn on/off specified VLAN in the VLAN filter table.
968 **/
969 static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
970 bool vlan_on)
971 {
972 u32 regindex;
973 u32 bitindex;
974 u32 bits;
975 u32 first_empty_slot;
976
977 if (vlan > 4095)
978 return IXGBE_ERR_PARAM;
979
980 /*
981 * this is a 2 part operation - first the VFTA, then the
982 * VLVF and VLVFB if vind is set
983 */
984
985 /* Part 1
986 * The VFTA is a bitstring made up of 128 32-bit registers
987 * that enable the particular VLAN id, much like the MTA:
988 * bits[11-5]: which register
989 * bits[4-0]: which bit in the register
990 */
991 regindex = (vlan >> 5) & 0x7F;
992 bitindex = vlan & 0x1F;
993 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
994 if (vlan_on)
995 bits |= (1 << bitindex);
996 else
997 bits &= ~(1 << bitindex);
998 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
999
1000
1001 /* Part 2
1002 * If the vind is set
1003 * Either vlan_on
1004 * make sure the vlan is in VLVF
1005 * set the vind bit in the matching VLVFB
1006 * Or !vlan_on
1007 * clear the pool bit and possibly the vind
1008 */
1009 if (vind) {
1010 /* find the vlanid or the first empty slot */
1011 first_empty_slot = 0;
1012
1013 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1014 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1015 if (!bits && !first_empty_slot)
1016 first_empty_slot = regindex;
1017 else if ((bits & 0x0FFF) == vlan)
1018 break;
1019 }
1020
1021 if (regindex >= IXGBE_VLVF_ENTRIES) {
1022 if (first_empty_slot)
1023 regindex = first_empty_slot;
1024 else {
1025 hw_dbg(hw, "No space in VLVF.\n");
1026 goto out;
1027 }
1028 }
1029
1030 if (vlan_on) {
1031 /* set the pool bit */
1032 if (vind < 32) {
1033 bits = IXGBE_READ_REG(hw,
1034 IXGBE_VLVFB(regindex * 2));
1035 bits |= (1 << vind);
1036 IXGBE_WRITE_REG(hw,
1037 IXGBE_VLVFB(regindex * 2), bits);
1038 } else {
1039 bits = IXGBE_READ_REG(hw,
1040 IXGBE_VLVFB((regindex * 2) + 1));
1041 bits |= (1 << vind);
1042 IXGBE_WRITE_REG(hw,
1043 IXGBE_VLVFB((regindex * 2) + 1), bits);
1044 }
1045 } else {
1046 /* clear the pool bit */
1047 if (vind < 32) {
1048 bits = IXGBE_READ_REG(hw,
1049 IXGBE_VLVFB(regindex * 2));
1050 bits &= ~(1 << vind);
1051 IXGBE_WRITE_REG(hw,
1052 IXGBE_VLVFB(regindex * 2), bits);
1053 bits |= IXGBE_READ_REG(hw,
1054 IXGBE_VLVFB((regindex * 2) + 1));
1055 } else {
1056 bits = IXGBE_READ_REG(hw,
1057 IXGBE_VLVFB((regindex * 2) + 1));
1058 bits &= ~(1 << vind);
1059 IXGBE_WRITE_REG(hw,
1060 IXGBE_VLVFB((regindex * 2) + 1), bits);
1061 bits |= IXGBE_READ_REG(hw,
1062 IXGBE_VLVFB(regindex * 2));
1063 }
1064 }
1065
1066 if (bits)
1067 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1068 (IXGBE_VLVF_VIEN | vlan));
1069 else
1070 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1071 }
1072
1073 out:
1074 return 0;
1075 }
1076
1077 /**
1078 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1079 * @hw: pointer to hardware structure
1080 *
1081 * Clears the VLAN filer table, and the VMDq index associated with the filter
1082 **/
1083 static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1084 {
1085 u32 offset;
1086
1087 for (offset = 0; offset < hw->mac.vft_size; offset++)
1088 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1089
1090 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1091 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1092 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1093 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1094 }
1095
1096 return 0;
1097 }
1098
1099 /**
1100 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1101 * @hw: pointer to hardware structure
1102 **/
1103 static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1104 {
1105 int i;
1106 hw_dbg(hw, " Clearing UTA\n");
1107
1108 for (i = 0; i < 128; i++)
1109 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1110
1111 return 0;
1112 }
1113
1114 /**
1115 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1116 * @hw: pointer to hardware structure
1117 **/
1118 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1119 {
1120 int i;
1121 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1122 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1123
1124 /*
1125 * Before starting reinitialization process,
1126 * FDIRCMD.CMD must be zero.
1127 */
1128 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1129 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1130 IXGBE_FDIRCMD_CMD_MASK))
1131 break;
1132 udelay(10);
1133 }
1134 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1135 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1136 "aborting table re-initialization. \n");
1137 return IXGBE_ERR_FDIR_REINIT_FAILED;
1138 }
1139
1140 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1141 IXGBE_WRITE_FLUSH(hw);
1142 /*
1143 * 82599 adapters flow director init flow cannot be restarted,
1144 * Workaround 82599 silicon errata by performing the following steps
1145 * before re-writing the FDIRCTRL control register with the same value.
1146 * - write 1 to bit 8 of FDIRCMD register &
1147 * - write 0 to bit 8 of FDIRCMD register
1148 */
1149 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1150 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1151 IXGBE_FDIRCMD_CLEARHT));
1152 IXGBE_WRITE_FLUSH(hw);
1153 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1154 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1155 ~IXGBE_FDIRCMD_CLEARHT));
1156 IXGBE_WRITE_FLUSH(hw);
1157 /*
1158 * Clear FDIR Hash register to clear any leftover hashes
1159 * waiting to be programmed.
1160 */
1161 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1162 IXGBE_WRITE_FLUSH(hw);
1163
1164 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1165 IXGBE_WRITE_FLUSH(hw);
1166
1167 /* Poll init-done after we write FDIRCTRL register */
1168 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1169 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1170 IXGBE_FDIRCTRL_INIT_DONE)
1171 break;
1172 udelay(10);
1173 }
1174 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1175 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1176 return IXGBE_ERR_FDIR_REINIT_FAILED;
1177 }
1178
1179 /* Clear FDIR statistics registers (read to clear) */
1180 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1181 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1182 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1183 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1184 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1185
1186 return 0;
1187 }
1188
1189 /**
1190 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1191 * @hw: pointer to hardware structure
1192 * @pballoc: which mode to allocate filters with
1193 **/
1194 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1195 {
1196 u32 fdirctrl = 0;
1197 u32 pbsize;
1198 int i;
1199
1200 /*
1201 * Before enabling Flow Director, the Rx Packet Buffer size
1202 * must be reduced. The new value is the current size minus
1203 * flow director memory usage size.
1204 */
1205 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1206 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1207 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1208
1209 /*
1210 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1211 * intialized to zero for non DCB mode otherwise actual total RX PB
1212 * would be bigger than programmed and filter space would run into
1213 * the PB 0 region.
1214 */
1215 for (i = 1; i < 8; i++)
1216 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1217
1218 /* Send interrupt when 64 filters are left */
1219 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1220
1221 /* Set the maximum length per hash bucket to 0xA filters */
1222 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1223
1224 switch (pballoc) {
1225 case IXGBE_FDIR_PBALLOC_64K:
1226 /* 8k - 1 signature filters */
1227 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1228 break;
1229 case IXGBE_FDIR_PBALLOC_128K:
1230 /* 16k - 1 signature filters */
1231 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1232 break;
1233 case IXGBE_FDIR_PBALLOC_256K:
1234 /* 32k - 1 signature filters */
1235 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1236 break;
1237 default:
1238 /* bad value */
1239 return IXGBE_ERR_CONFIG;
1240 };
1241
1242 /* Move the flexible bytes to use the ethertype - shift 6 words */
1243 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1244
1245 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1246
1247 /* Prime the keys for hashing */
1248 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1249 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1250 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1251 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1252
1253 /*
1254 * Poll init-done after we write the register. Estimated times:
1255 * 10G: PBALLOC = 11b, timing is 60us
1256 * 1G: PBALLOC = 11b, timing is 600us
1257 * 100M: PBALLOC = 11b, timing is 6ms
1258 *
1259 * Multiple these timings by 4 if under full Rx load
1260 *
1261 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1262 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1263 * this might not finish in our poll time, but we can live with that
1264 * for now.
1265 */
1266 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1267 IXGBE_WRITE_FLUSH(hw);
1268 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1269 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1270 IXGBE_FDIRCTRL_INIT_DONE)
1271 break;
1272 msleep(1);
1273 }
1274 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1275 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1276
1277 return 0;
1278 }
1279
1280 /**
1281 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1282 * @hw: pointer to hardware structure
1283 * @pballoc: which mode to allocate filters with
1284 **/
1285 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1286 {
1287 u32 fdirctrl = 0;
1288 u32 pbsize;
1289 int i;
1290
1291 /*
1292 * Before enabling Flow Director, the Rx Packet Buffer size
1293 * must be reduced. The new value is the current size minus
1294 * flow director memory usage size.
1295 */
1296 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1297 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1298 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1299
1300 /*
1301 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1302 * intialized to zero for non DCB mode otherwise actual total RX PB
1303 * would be bigger than programmed and filter space would run into
1304 * the PB 0 region.
1305 */
1306 for (i = 1; i < 8; i++)
1307 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1308
1309 /* Send interrupt when 64 filters are left */
1310 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1311
1312 switch (pballoc) {
1313 case IXGBE_FDIR_PBALLOC_64K:
1314 /* 2k - 1 perfect filters */
1315 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1316 break;
1317 case IXGBE_FDIR_PBALLOC_128K:
1318 /* 4k - 1 perfect filters */
1319 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1320 break;
1321 case IXGBE_FDIR_PBALLOC_256K:
1322 /* 8k - 1 perfect filters */
1323 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1324 break;
1325 default:
1326 /* bad value */
1327 return IXGBE_ERR_CONFIG;
1328 };
1329
1330 /* Turn perfect match filtering on */
1331 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1332 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1333
1334 /* Move the flexible bytes to use the ethertype - shift 6 words */
1335 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1336
1337 /* Prime the keys for hashing */
1338 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1339 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1340 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1341 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1342
1343 /*
1344 * Poll init-done after we write the register. Estimated times:
1345 * 10G: PBALLOC = 11b, timing is 60us
1346 * 1G: PBALLOC = 11b, timing is 600us
1347 * 100M: PBALLOC = 11b, timing is 6ms
1348 *
1349 * Multiple these timings by 4 if under full Rx load
1350 *
1351 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1352 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1353 * this might not finish in our poll time, but we can live with that
1354 * for now.
1355 */
1356
1357 /* Set the maximum length per hash bucket to 0xA filters */
1358 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1359
1360 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1361 IXGBE_WRITE_FLUSH(hw);
1362 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1363 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1364 IXGBE_FDIRCTRL_INIT_DONE)
1365 break;
1366 msleep(1);
1367 }
1368 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1369 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1370
1371 return 0;
1372 }
1373
1374
1375 /**
1376 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1377 * @stream: input bitstream to compute the hash on
1378 * @key: 32-bit hash key
1379 **/
1380 static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1381 u32 key)
1382 {
1383 /*
1384 * The algorithm is as follows:
1385 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1386 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1387 * and A[n] x B[n] is bitwise AND between same length strings
1388 *
1389 * K[n] is 16 bits, defined as:
1390 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1391 * for n modulo 32 < 15, K[n] =
1392 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1393 *
1394 * S[n] is 16 bits, defined as:
1395 * for n >= 15, S[n] = S[n:n - 15]
1396 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1397 *
1398 * To simplify for programming, the algorithm is implemented
1399 * in software this way:
1400 *
1401 * Key[31:0], Stream[335:0]
1402 *
1403 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1404 * int_key[350:0] = tmp_key[351:1]
1405 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1406 *
1407 * hash[15:0] = 0;
1408 * for (i = 0; i < 351; i++) {
1409 * if (int_key[i])
1410 * hash ^= int_stream[(i + 15):i];
1411 * }
1412 */
1413
1414 union {
1415 u64 fill[6];
1416 u32 key[11];
1417 u8 key_stream[44];
1418 } tmp_key;
1419
1420 u8 *stream = (u8 *)atr_input;
1421 u8 int_key[44]; /* upper-most bit unused */
1422 u8 hash_str[46]; /* upper-most 2 bits unused */
1423 u16 hash_result = 0;
1424 int i, j, k, h;
1425
1426 /*
1427 * Initialize the fill member to prevent warnings
1428 * on some compilers
1429 */
1430 tmp_key.fill[0] = 0;
1431
1432 /* First load the temporary key stream */
1433 for (i = 0; i < 6; i++) {
1434 u64 fillkey = ((u64)key << 32) | key;
1435 tmp_key.fill[i] = fillkey;
1436 }
1437
1438 /*
1439 * Set the interim key for the hashing. Bit 352 is unused, so we must
1440 * shift and compensate when building the key.
1441 */
1442
1443 int_key[0] = tmp_key.key_stream[0] >> 1;
1444 for (i = 1, j = 0; i < 44; i++) {
1445 unsigned int this_key = tmp_key.key_stream[j] << 7;
1446 j++;
1447 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1448 }
1449
1450 /*
1451 * Set the interim bit string for the hashing. Bits 368 and 367 are
1452 * unused, so shift and compensate when building the string.
1453 */
1454 hash_str[0] = (stream[40] & 0x7f) >> 1;
1455 for (i = 1, j = 40; i < 46; i++) {
1456 unsigned int this_str = stream[j] << 7;
1457 j++;
1458 if (j > 41)
1459 j = 0;
1460 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1461 }
1462
1463 /*
1464 * Now compute the hash. i is the index into hash_str, j is into our
1465 * key stream, k is counting the number of bits, and h interates within
1466 * each byte.
1467 */
1468 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1469 for (h = 0; h < 8 && k < 351; h++, k++) {
1470 if (int_key[j] & (1 << h)) {
1471 /*
1472 * Key bit is set, XOR in the current 16-bit
1473 * string. Example of processing:
1474 * h = 0,
1475 * tmp = (hash_str[i - 2] & 0 << 16) |
1476 * (hash_str[i - 1] & 0xff << 8) |
1477 * (hash_str[i] & 0xff >> 0)
1478 * So tmp = hash_str[15 + k:k], since the
1479 * i + 2 clause rolls off the 16-bit value
1480 * h = 7,
1481 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1482 * (hash_str[i - 1] & 0xff << 1) |
1483 * (hash_str[i] & 0x80 >> 7)
1484 */
1485 int tmp = (hash_str[i] >> h);
1486 tmp |= (hash_str[i - 1] << (8 - h));
1487 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1488 << (16 - h);
1489 hash_result ^= (u16)tmp;
1490 }
1491 }
1492 }
1493
1494 return hash_result;
1495 }
1496
1497 /**
1498 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1499 * @input: input stream to modify
1500 * @vlan: the VLAN id to load
1501 **/
1502 s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1503 {
1504 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1505 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1506
1507 return 0;
1508 }
1509
1510 /**
1511 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1512 * @input: input stream to modify
1513 * @src_addr: the IP address to load
1514 **/
1515 s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1516 {
1517 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1518 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1519 (src_addr >> 16) & 0xff;
1520 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1521 (src_addr >> 8) & 0xff;
1522 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1523
1524 return 0;
1525 }
1526
1527 /**
1528 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1529 * @input: input stream to modify
1530 * @dst_addr: the IP address to load
1531 **/
1532 s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1533 {
1534 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1535 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1536 (dst_addr >> 16) & 0xff;
1537 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1538 (dst_addr >> 8) & 0xff;
1539 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1540
1541 return 0;
1542 }
1543
1544 /**
1545 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1546 * @input: input stream to modify
1547 * @src_addr_1: the first 4 bytes of the IP address to load
1548 * @src_addr_2: the second 4 bytes of the IP address to load
1549 * @src_addr_3: the third 4 bytes of the IP address to load
1550 * @src_addr_4: the fourth 4 bytes of the IP address to load
1551 **/
1552 s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
1553 u32 src_addr_1, u32 src_addr_2,
1554 u32 src_addr_3, u32 src_addr_4)
1555 {
1556 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1557 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1558 (src_addr_4 >> 8) & 0xff;
1559 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1560 (src_addr_4 >> 16) & 0xff;
1561 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1562
1563 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1564 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1565 (src_addr_3 >> 8) & 0xff;
1566 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1567 (src_addr_3 >> 16) & 0xff;
1568 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1569
1570 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1571 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1572 (src_addr_2 >> 8) & 0xff;
1573 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1574 (src_addr_2 >> 16) & 0xff;
1575 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1576
1577 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1578 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1579 (src_addr_1 >> 8) & 0xff;
1580 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1581 (src_addr_1 >> 16) & 0xff;
1582 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1583
1584 return 0;
1585 }
1586
1587 /**
1588 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1589 * @input: input stream to modify
1590 * @dst_addr_1: the first 4 bytes of the IP address to load
1591 * @dst_addr_2: the second 4 bytes of the IP address to load
1592 * @dst_addr_3: the third 4 bytes of the IP address to load
1593 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1594 **/
1595 s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
1596 u32 dst_addr_1, u32 dst_addr_2,
1597 u32 dst_addr_3, u32 dst_addr_4)
1598 {
1599 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1600 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1601 (dst_addr_4 >> 8) & 0xff;
1602 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1603 (dst_addr_4 >> 16) & 0xff;
1604 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1605
1606 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1607 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1608 (dst_addr_3 >> 8) & 0xff;
1609 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1610 (dst_addr_3 >> 16) & 0xff;
1611 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1612
1613 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1614 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1615 (dst_addr_2 >> 8) & 0xff;
1616 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1617 (dst_addr_2 >> 16) & 0xff;
1618 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1619
1620 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1621 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1622 (dst_addr_1 >> 8) & 0xff;
1623 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1624 (dst_addr_1 >> 16) & 0xff;
1625 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1626
1627 return 0;
1628 }
1629
1630 /**
1631 * ixgbe_atr_set_src_port_82599 - Sets the source port
1632 * @input: input stream to modify
1633 * @src_port: the source port to load
1634 **/
1635 s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1636 {
1637 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1638 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1639
1640 return 0;
1641 }
1642
1643 /**
1644 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1645 * @input: input stream to modify
1646 * @dst_port: the destination port to load
1647 **/
1648 s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1649 {
1650 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1651 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1652
1653 return 0;
1654 }
1655
1656 /**
1657 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1658 * @input: input stream to modify
1659 * @flex_bytes: the flexible bytes to load
1660 **/
1661 s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1662 {
1663 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1664 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1665
1666 return 0;
1667 }
1668
1669 /**
1670 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1671 * @input: input stream to modify
1672 * @vm_pool: the Virtual Machine pool to load
1673 **/
1674 s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1675 u8 vm_pool)
1676 {
1677 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1678
1679 return 0;
1680 }
1681
1682 /**
1683 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1684 * @input: input stream to modify
1685 * @l4type: the layer 4 type value to load
1686 **/
1687 s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1688 {
1689 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1690
1691 return 0;
1692 }
1693
1694 /**
1695 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1696 * @input: input stream to search
1697 * @vlan: the VLAN id to load
1698 **/
1699 static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1700 u16 *vlan)
1701 {
1702 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1703 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1704
1705 return 0;
1706 }
1707
1708 /**
1709 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1710 * @input: input stream to search
1711 * @src_addr: the IP address to load
1712 **/
1713 static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1714 u32 *src_addr)
1715 {
1716 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1717 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1718 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1719 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1720
1721 return 0;
1722 }
1723
1724 /**
1725 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1726 * @input: input stream to search
1727 * @dst_addr: the IP address to load
1728 **/
1729 static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1730 u32 *dst_addr)
1731 {
1732 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1733 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1734 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1735 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1736
1737 return 0;
1738 }
1739
1740 /**
1741 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1742 * @input: input stream to search
1743 * @src_addr_1: the first 4 bytes of the IP address to load
1744 * @src_addr_2: the second 4 bytes of the IP address to load
1745 * @src_addr_3: the third 4 bytes of the IP address to load
1746 * @src_addr_4: the fourth 4 bytes of the IP address to load
1747 **/
1748 static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1749 u32 *src_addr_1, u32 *src_addr_2,
1750 u32 *src_addr_3, u32 *src_addr_4)
1751 {
1752 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1753 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1754 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1755 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1756
1757 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1758 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1759 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1760 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1761
1762 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1763 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1764 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1765 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1766
1767 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1768 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1769 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1770 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1771
1772 return 0;
1773 }
1774
1775 /**
1776 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1777 * @input: input stream to search
1778 * @dst_addr_1: the first 4 bytes of the IP address to load
1779 * @dst_addr_2: the second 4 bytes of the IP address to load
1780 * @dst_addr_3: the third 4 bytes of the IP address to load
1781 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1782 **/
1783 s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
1784 u32 *dst_addr_1, u32 *dst_addr_2,
1785 u32 *dst_addr_3, u32 *dst_addr_4)
1786 {
1787 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1788 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1789 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1790 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1791
1792 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1793 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1794 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1795 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1796
1797 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1798 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1799 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1800 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1801
1802 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1803 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1804 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1805 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1806
1807 return 0;
1808 }
1809
1810 /**
1811 * ixgbe_atr_get_src_port_82599 - Gets the source port
1812 * @input: input stream to modify
1813 * @src_port: the source port to load
1814 *
1815 * Even though the input is given in big-endian, the FDIRPORT registers
1816 * expect the ports to be programmed in little-endian. Hence the need to swap
1817 * endianness when retrieving the data. This can be confusing since the
1818 * internal hash engine expects it to be big-endian.
1819 **/
1820 static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1821 u16 *src_port)
1822 {
1823 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1824 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1825
1826 return 0;
1827 }
1828
1829 /**
1830 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1831 * @input: input stream to modify
1832 * @dst_port: the destination port to load
1833 *
1834 * Even though the input is given in big-endian, the FDIRPORT registers
1835 * expect the ports to be programmed in little-endian. Hence the need to swap
1836 * endianness when retrieving the data. This can be confusing since the
1837 * internal hash engine expects it to be big-endian.
1838 **/
1839 static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1840 u16 *dst_port)
1841 {
1842 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1843 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1844
1845 return 0;
1846 }
1847
1848 /**
1849 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1850 * @input: input stream to modify
1851 * @flex_bytes: the flexible bytes to load
1852 **/
1853 static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1854 u16 *flex_byte)
1855 {
1856 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1857 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1858
1859 return 0;
1860 }
1861
1862 /**
1863 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1864 * @input: input stream to modify
1865 * @vm_pool: the Virtual Machine pool to load
1866 **/
1867 s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1868 u8 *vm_pool)
1869 {
1870 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1871
1872 return 0;
1873 }
1874
1875 /**
1876 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1877 * @input: input stream to modify
1878 * @l4type: the layer 4 type value to load
1879 **/
1880 static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1881 u8 *l4type)
1882 {
1883 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1884
1885 return 0;
1886 }
1887
1888 /**
1889 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1890 * @hw: pointer to hardware structure
1891 * @stream: input bitstream
1892 * @queue: queue index to direct traffic to
1893 **/
1894 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1895 struct ixgbe_atr_input *input,
1896 u8 queue)
1897 {
1898 u64 fdirhashcmd;
1899 u64 fdircmd;
1900 u32 fdirhash;
1901 u16 bucket_hash, sig_hash;
1902 u8 l4type;
1903
1904 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1905 IXGBE_ATR_BUCKET_HASH_KEY);
1906
1907 /* bucket_hash is only 15 bits */
1908 bucket_hash &= IXGBE_ATR_HASH_MASK;
1909
1910 sig_hash = ixgbe_atr_compute_hash_82599(input,
1911 IXGBE_ATR_SIGNATURE_HASH_KEY);
1912
1913 /* Get the l4type in order to program FDIRCMD properly */
1914 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1915 ixgbe_atr_get_l4type_82599(input, &l4type);
1916
1917 /*
1918 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1919 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1920 */
1921 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1922
1923 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1924 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1925
1926 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1927 case IXGBE_ATR_L4TYPE_TCP:
1928 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1929 break;
1930 case IXGBE_ATR_L4TYPE_UDP:
1931 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1932 break;
1933 case IXGBE_ATR_L4TYPE_SCTP:
1934 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1935 break;
1936 default:
1937 hw_dbg(hw, "Error on l4type input\n");
1938 return IXGBE_ERR_CONFIG;
1939 }
1940
1941 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1942 fdircmd |= IXGBE_FDIRCMD_IPV6;
1943
1944 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1945 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1946
1947 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1948
1949 return 0;
1950 }
1951
1952 /**
1953 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1954 * @hw: pointer to hardware structure
1955 * @input: input bitstream
1956 * @queue: queue index to direct traffic to
1957 *
1958 * Note that the caller to this function must lock before calling, since the
1959 * hardware writes must be protected from one another.
1960 **/
1961 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1962 struct ixgbe_atr_input *input,
1963 u16 soft_id,
1964 u8 queue)
1965 {
1966 u32 fdircmd = 0;
1967 u32 fdirhash;
1968 u32 src_ipv4, dst_ipv4;
1969 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1970 u16 src_port, dst_port, vlan_id, flex_bytes;
1971 u16 bucket_hash;
1972 u8 l4type;
1973
1974 /* Get our input values */
1975 ixgbe_atr_get_l4type_82599(input, &l4type);
1976
1977 /*
1978 * Check l4type formatting, and bail out before we touch the hardware
1979 * if there's a configuration issue
1980 */
1981 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1982 case IXGBE_ATR_L4TYPE_TCP:
1983 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1984 break;
1985 case IXGBE_ATR_L4TYPE_UDP:
1986 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1987 break;
1988 case IXGBE_ATR_L4TYPE_SCTP:
1989 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1990 break;
1991 default:
1992 hw_dbg(hw, "Error on l4type input\n");
1993 return IXGBE_ERR_CONFIG;
1994 }
1995
1996 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1997 IXGBE_ATR_BUCKET_HASH_KEY);
1998
1999 /* bucket_hash is only 15 bits */
2000 bucket_hash &= IXGBE_ATR_HASH_MASK;
2001
2002 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2003 ixgbe_atr_get_src_port_82599(input, &src_port);
2004 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2005 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2006
2007 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2008
2009 /* Now figure out if we're IPv4 or IPv6 */
2010 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2011 /* IPv6 */
2012 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2013 &src_ipv6_3, &src_ipv6_4);
2014
2015 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2016 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2017 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2018 /* The last 4 bytes is the same register as IPv4 */
2019 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2020
2021 fdircmd |= IXGBE_FDIRCMD_IPV6;
2022 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2023 } else {
2024 /* IPv4 */
2025 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2026 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2027
2028 }
2029
2030 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2031 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2032
2033 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2034 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2035 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2036 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2037
2038 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2039 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2040 fdircmd |= IXGBE_FDIRCMD_LAST;
2041 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2042 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2043
2044 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2045 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2046
2047 return 0;
2048 }
2049 /**
2050 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2051 * @hw: pointer to hardware structure
2052 * @reg: analog register to read
2053 * @val: read value
2054 *
2055 * Performs read operation to Omer analog register specified.
2056 **/
2057 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2058 {
2059 u32 core_ctl;
2060
2061 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2062 (reg << 8));
2063 IXGBE_WRITE_FLUSH(hw);
2064 udelay(10);
2065 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2066 *val = (u8)core_ctl;
2067
2068 return 0;
2069 }
2070
2071 /**
2072 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2073 * @hw: pointer to hardware structure
2074 * @reg: atlas register to write
2075 * @val: value to write
2076 *
2077 * Performs write operation to Omer analog register specified.
2078 **/
2079 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2080 {
2081 u32 core_ctl;
2082
2083 core_ctl = (reg << 8) | val;
2084 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2085 IXGBE_WRITE_FLUSH(hw);
2086 udelay(10);
2087
2088 return 0;
2089 }
2090
2091 /**
2092 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2093 * @hw: pointer to hardware structure
2094 *
2095 * Starts the hardware using the generic start_hw function.
2096 * Then performs device-specific:
2097 * Clears the rate limiter registers.
2098 **/
2099 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2100 {
2101 u32 q_num;
2102 s32 ret_val;
2103
2104 ret_val = ixgbe_start_hw_generic(hw);
2105
2106 /* Clear the rate limiters */
2107 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2108 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2109 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2110 }
2111 IXGBE_WRITE_FLUSH(hw);
2112
2113 /* We need to run link autotry after the driver loads */
2114 hw->mac.autotry_restart = true;
2115
2116 if (ret_val == 0)
2117 ret_val = ixgbe_verify_fw_version_82599(hw);
2118
2119 return ret_val;
2120 }
2121
2122 /**
2123 * ixgbe_identify_phy_82599 - Get physical layer module
2124 * @hw: pointer to hardware structure
2125 *
2126 * Determines the physical layer module found on the current adapter.
2127 **/
2128 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2129 {
2130 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2131 status = ixgbe_identify_phy_generic(hw);
2132 if (status != 0)
2133 status = ixgbe_identify_sfp_module_generic(hw);
2134 return status;
2135 }
2136
2137 /**
2138 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2139 * @hw: pointer to hardware structure
2140 *
2141 * Determines physical layer capabilities of the current configuration.
2142 **/
2143 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2144 {
2145 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2146 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2147 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2148 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2149 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2150 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2151 u16 ext_ability = 0;
2152 u8 comp_codes_10g = 0;
2153
2154 hw->phy.ops.identify(hw);
2155
2156 if (hw->phy.type == ixgbe_phy_tn ||
2157 hw->phy.type == ixgbe_phy_cu_unknown) {
2158 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2159 &ext_ability);
2160 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2161 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2162 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
2163 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2164 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2165 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2166 goto out;
2167 }
2168
2169 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2170 case IXGBE_AUTOC_LMS_1G_AN:
2171 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2172 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2173 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2174 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2175 goto out;
2176 } else
2177 /* SFI mode so read SFP module */
2178 goto sfp_check;
2179 break;
2180 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2181 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2182 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2183 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2184 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2185 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2186 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2187 goto out;
2188 break;
2189 case IXGBE_AUTOC_LMS_10G_SERIAL:
2190 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2191 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2192 goto out;
2193 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2194 goto sfp_check;
2195 break;
2196 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2197 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2198 if (autoc & IXGBE_AUTOC_KX_SUPP)
2199 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2200 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2201 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2202 if (autoc & IXGBE_AUTOC_KR_SUPP)
2203 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2204 goto out;
2205 break;
2206 default:
2207 goto out;
2208 break;
2209 }
2210
2211 sfp_check:
2212 /* SFP check must be done last since DA modules are sometimes used to
2213 * test KR mode - we need to id KR mode correctly before SFP module.
2214 * Call identify_sfp because the pluggable module may have changed */
2215 hw->phy.ops.identify_sfp(hw);
2216 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2217 goto out;
2218
2219 switch (hw->phy.type) {
2220 case ixgbe_phy_tw_tyco:
2221 case ixgbe_phy_tw_unknown:
2222 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2223 break;
2224 case ixgbe_phy_sfp_avago:
2225 case ixgbe_phy_sfp_ftl:
2226 case ixgbe_phy_sfp_intel:
2227 case ixgbe_phy_sfp_unknown:
2228 hw->phy.ops.read_i2c_eeprom(hw,
2229 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2230 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2231 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2232 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2233 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2234 break;
2235 default:
2236 break;
2237 }
2238
2239 out:
2240 return physical_layer;
2241 }
2242
2243 /**
2244 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2245 * @hw: pointer to hardware structure
2246 * @regval: register value to write to RXCTRL
2247 *
2248 * Enables the Rx DMA unit for 82599
2249 **/
2250 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2251 {
2252 #define IXGBE_MAX_SECRX_POLL 30
2253 int i;
2254 int secrxreg;
2255
2256 /*
2257 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2258 * If traffic is incoming before we enable the Rx unit, it could hang
2259 * the Rx DMA unit. Therefore, make sure the security engine is
2260 * completely disabled prior to enabling the Rx unit.
2261 */
2262 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2263 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2264 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2265 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2266 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2267 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2268 break;
2269 else
2270 udelay(10);
2271 }
2272
2273 /* For informational purposes only */
2274 if (i >= IXGBE_MAX_SECRX_POLL)
2275 hw_dbg(hw, "Rx unit being enabled before security "
2276 "path fully disabled. Continuing with init.\n");
2277
2278 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2279 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2280 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2281 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2282 IXGBE_WRITE_FLUSH(hw);
2283
2284 return 0;
2285 }
2286
2287 /**
2288 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2289 * @hw: pointer to hardware structure
2290 * @device_caps: the EEPROM word with the extra device capabilities
2291 *
2292 * This function will read the EEPROM location for the device capabilities,
2293 * and return the word through device_caps.
2294 **/
2295 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2296 {
2297 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2298
2299 return 0;
2300 }
2301
2302 /**
2303 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2304 * @hw: pointer to hardware structure
2305 * @san_mac_offset: SAN MAC address offset
2306 *
2307 * This function will read the EEPROM location for the SAN MAC address
2308 * pointer, and returns the value at that location. This is used in both
2309 * get and set mac_addr routines.
2310 **/
2311 static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2312 u16 *san_mac_offset)
2313 {
2314 /*
2315 * First read the EEPROM pointer to see if the MAC addresses are
2316 * available.
2317 */
2318 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2319
2320 return 0;
2321 }
2322
2323 /**
2324 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2325 * @hw: pointer to hardware structure
2326 * @san_mac_addr: SAN MAC address
2327 *
2328 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2329 * per-port, so set_lan_id() must be called before reading the addresses.
2330 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2331 * upon for non-SFP connections, so we must call it here.
2332 **/
2333 static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
2334 {
2335 u16 san_mac_data, san_mac_offset;
2336 u8 i;
2337
2338 /*
2339 * First read the EEPROM pointer to see if the MAC addresses are
2340 * available. If they're not, no point in calling set_lan_id() here.
2341 */
2342 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2343
2344 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2345 /*
2346 * No addresses available in this EEPROM. It's not an
2347 * error though, so just wipe the local address and return.
2348 */
2349 for (i = 0; i < 6; i++)
2350 san_mac_addr[i] = 0xFF;
2351
2352 goto san_mac_addr_out;
2353 }
2354
2355 /* make sure we know which port we need to program */
2356 hw->mac.ops.set_lan_id(hw);
2357 /* apply the port offset to the address offset */
2358 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2359 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2360 for (i = 0; i < 3; i++) {
2361 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2362 san_mac_addr[i * 2] = (u8)(san_mac_data);
2363 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2364 san_mac_offset++;
2365 }
2366
2367 san_mac_addr_out:
2368 return 0;
2369 }
2370
2371 /**
2372 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2373 * @hw: pointer to hardware structure
2374 *
2375 * Verifies that installed the firmware version is 0.6 or higher
2376 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2377 *
2378 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2379 * if the FW version is not supported.
2380 **/
2381 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2382 {
2383 s32 status = IXGBE_ERR_EEPROM_VERSION;
2384 u16 fw_offset, fw_ptp_cfg_offset;
2385 u16 fw_version = 0;
2386
2387 /* firmware check is only necessary for SFI devices */
2388 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2389 status = 0;
2390 goto fw_version_out;
2391 }
2392
2393 /* get the offset to the Firmware Module block */
2394 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2395
2396 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2397 goto fw_version_out;
2398
2399 /* get the offset to the Pass Through Patch Configuration block */
2400 hw->eeprom.ops.read(hw, (fw_offset +
2401 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2402 &fw_ptp_cfg_offset);
2403
2404 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2405 goto fw_version_out;
2406
2407 /* get the firmware version */
2408 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2409 IXGBE_FW_PATCH_VERSION_4),
2410 &fw_version);
2411
2412 if (fw_version > 0x5)
2413 status = 0;
2414
2415 fw_version_out:
2416 return status;
2417 }
2418
2419 static struct ixgbe_mac_operations mac_ops_82599 = {
2420 .init_hw = &ixgbe_init_hw_generic,
2421 .reset_hw = &ixgbe_reset_hw_82599,
2422 .start_hw = &ixgbe_start_hw_82599,
2423 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2424 .get_media_type = &ixgbe_get_media_type_82599,
2425 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2426 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2427 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2428 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
2429 .get_device_caps = &ixgbe_get_device_caps_82599,
2430 .stop_adapter = &ixgbe_stop_adapter_generic,
2431 .get_bus_info = &ixgbe_get_bus_info_generic,
2432 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2433 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2434 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2435 .setup_link = &ixgbe_setup_mac_link_82599,
2436 .check_link = &ixgbe_check_mac_link_82599,
2437 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2438 .led_on = &ixgbe_led_on_generic,
2439 .led_off = &ixgbe_led_off_generic,
2440 .blink_led_start = &ixgbe_blink_led_start_generic,
2441 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2442 .set_rar = &ixgbe_set_rar_generic,
2443 .clear_rar = &ixgbe_clear_rar_generic,
2444 .set_vmdq = &ixgbe_set_vmdq_82599,
2445 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2446 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2447 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2448 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2449 .enable_mc = &ixgbe_enable_mc_generic,
2450 .disable_mc = &ixgbe_disable_mc_generic,
2451 .clear_vfta = &ixgbe_clear_vfta_82599,
2452 .set_vfta = &ixgbe_set_vfta_82599,
2453 .fc_enable = &ixgbe_fc_enable_generic,
2454 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2455 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2456 };
2457
2458 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2459 .init_params = &ixgbe_init_eeprom_params_generic,
2460 .read = &ixgbe_read_eeprom_generic,
2461 .write = &ixgbe_write_eeprom_generic,
2462 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2463 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2464 };
2465
2466 static struct ixgbe_phy_operations phy_ops_82599 = {
2467 .identify = &ixgbe_identify_phy_82599,
2468 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2469 .init = &ixgbe_init_phy_ops_82599,
2470 .reset = &ixgbe_reset_phy_generic,
2471 .read_reg = &ixgbe_read_phy_reg_generic,
2472 .write_reg = &ixgbe_write_phy_reg_generic,
2473 .setup_link = &ixgbe_setup_phy_link_generic,
2474 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2475 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2476 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2477 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2478 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2479 };
2480
2481 struct ixgbe_info ixgbe_82599_info = {
2482 .mac = ixgbe_mac_82599EB,
2483 .get_invariants = &ixgbe_get_invariants_82599,
2484 .mac_ops = &mac_ops_82599,
2485 .eeprom_ops = &eeprom_ops_82599,
2486 .phy_ops = &phy_ops_82599,
2487 };
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