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init from v2.6.32.60
[mach-moxart.git] / drivers / net / wireless / ath / ath9k / hw.c
blob2570b72a7d5689f9040816ac7986a28e346904ad
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19 #include <linux/pci.h>
20
21 #include "ath9k.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
30 enum ath9k_ht_macmode macmode);
31 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
32 struct ar5416_eeprom_def *pEepData,
33 u32 reg, u32 value);
34 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
36
37 /********************/
38 /* Helper Functions */
39 /********************/
40
41 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
42 {
43 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
44
45 if (!ah->curchan) /* should really check for CCK instead */
46 return clks / ATH9K_CLOCK_RATE_CCK;
47 if (conf->channel->band == IEEE80211_BAND_2GHZ)
48 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
49
50 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
51 }
52
53 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
54 {
55 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
56
57 if (conf_is_ht40(conf))
58 return ath9k_hw_mac_usec(ah, clks) / 2;
59 else
60 return ath9k_hw_mac_usec(ah, clks);
61 }
62
63 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
64 {
65 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
66
67 if (!ah->curchan) /* should really check for CCK instead */
68 return usecs *ATH9K_CLOCK_RATE_CCK;
69 if (conf->channel->band == IEEE80211_BAND_2GHZ)
70 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
71 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
72 }
73
74 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
75 {
76 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
77
78 if (conf_is_ht40(conf))
79 return ath9k_hw_mac_clks(ah, usecs) * 2;
80 else
81 return ath9k_hw_mac_clks(ah, usecs);
82 }
83
84 /*
85 * Read and write, they both share the same lock. We do this to serialize
86 * reads and writes on Atheros 802.11n PCI devices only. This is required
87 * as the FIFO on these devices can only accept sanely 2 requests. After
88 * that the device goes bananas. Serializing the reads/writes prevents this
89 * from happening.
90 */
91
92 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
93 {
94 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
95 unsigned long flags;
96 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
97 iowrite32(val, ah->ah_sc->mem + reg_offset);
98 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
99 } else
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101 }
102
103 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
104 {
105 u32 val;
106 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
107 unsigned long flags;
108 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
109 val = ioread32(ah->ah_sc->mem + reg_offset);
110 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
111 } else
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 return val;
114 }
115
116 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
117 {
118 int i;
119
120 BUG_ON(timeout < AH_TIME_QUANTUM);
121
122 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
123 if ((REG_READ(ah, reg) & mask) == val)
124 return true;
125
126 udelay(AH_TIME_QUANTUM);
127 }
128
129 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
131 timeout, reg, REG_READ(ah, reg), mask, val);
132
133 return false;
134 }
135
136 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
137 {
138 u32 retval;
139 int i;
140
141 for (i = 0, retval = 0; i < n; i++) {
142 retval = (retval << 1) | (val & 1);
143 val >>= 1;
144 }
145 return retval;
146 }
147
148 bool ath9k_get_channel_edges(struct ath_hw *ah,
149 u16 flags, u16 *low,
150 u16 *high)
151 {
152 struct ath9k_hw_capabilities *pCap = &ah->caps;
153
154 if (flags & CHANNEL_5GHZ) {
155 *low = pCap->low_5ghz_chan;
156 *high = pCap->high_5ghz_chan;
157 return true;
158 }
159 if ((flags & CHANNEL_2GHZ)) {
160 *low = pCap->low_2ghz_chan;
161 *high = pCap->high_2ghz_chan;
162 return true;
163 }
164 return false;
165 }
166
167 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
168 const struct ath_rate_table *rates,
169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
171 {
172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
173 u32 kbps;
174
175 kbps = rates->info[rateix].ratekbps;
176
177 if (kbps == 0)
178 return 0;
179
180 switch (rates->info[rateix].phy) {
181 case WLAN_RC_PHY_CCK:
182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
183 if (shortPreamble && rates->info[rateix].short_preamble)
184 phyTime >>= 1;
185 numBits = frameLen << 3;
186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
187 break;
188 case WLAN_RC_PHY_OFDM:
189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
191 numBits = OFDM_PLCP_BITS + (frameLen << 3);
192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
193 txTime = OFDM_SIFS_TIME_QUARTER
194 + OFDM_PREAMBLE_TIME_QUARTER
195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
196 } else if (ah->curchan &&
197 IS_CHAN_HALF_RATE(ah->curchan)) {
198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
199 numBits = OFDM_PLCP_BITS + (frameLen << 3);
200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
201 txTime = OFDM_SIFS_TIME_HALF +
202 OFDM_PREAMBLE_TIME_HALF
203 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
204 } else {
205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
206 numBits = OFDM_PLCP_BITS + (frameLen << 3);
207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
209 + (numSymbols * OFDM_SYMBOL_TIME);
210 }
211 break;
212 default:
213 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
214 "Unknown phy %u (rate ix %u)\n",
215 rates->info[rateix].phy, rateix);
216 txTime = 0;
217 break;
218 }
219
220 return txTime;
221 }
222
223 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
224 struct ath9k_channel *chan,
225 struct chan_centers *centers)
226 {
227 int8_t extoff;
228
229 if (!IS_CHAN_HT40(chan)) {
230 centers->ctl_center = centers->ext_center =
231 centers->synth_center = chan->channel;
232 return;
233 }
234
235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
236 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
237 centers->synth_center =
238 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
239 extoff = 1;
240 } else {
241 centers->synth_center =
242 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
243 extoff = -1;
244 }
245
246 centers->ctl_center =
247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
248 centers->ext_center =
249 centers->synth_center + (extoff *
250 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
251 HT40_CHANNEL_CENTER_SHIFT : 15));
252 }
253
254 /******************/
255 /* Chip Revisions */
256 /******************/
257
258 static void ath9k_hw_read_revisions(struct ath_hw *ah)
259 {
260 u32 val;
261
262 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
263
264 if (val == 0xFF) {
265 val = REG_READ(ah, AR_SREV);
266 ah->hw_version.macVersion =
267 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
269 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
270 } else {
271 if (!AR_SREV_9100(ah))
272 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
273
274 ah->hw_version.macRev = val & AR_SREV_REVISION;
275
276 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
277 ah->is_pciexpress = true;
278 }
279 }
280
281 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
282 {
283 u32 val;
284 int i;
285
286 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
287
288 for (i = 0; i < 8; i++)
289 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
290 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
291 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
292
293 return ath9k_hw_reverse_bits(val, 8);
294 }
295
296 /************************************/
297 /* HW Attach, Detach, Init Routines */
298 /************************************/
299
300 static void ath9k_hw_disablepcie(struct ath_hw *ah)
301 {
302 if (AR_SREV_9100(ah))
303 return;
304
305 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
306 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
307 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
314
315 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
316 }
317
318 static bool ath9k_hw_chip_test(struct ath_hw *ah)
319 {
320 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
321 u32 regHold[2];
322 u32 patternData[4] = { 0x55555555,
323 0xaaaaaaaa,
324 0x66666666,
325 0x99999999 };
326 int i, j;
327
328 for (i = 0; i < 2; i++) {
329 u32 addr = regAddr[i];
330 u32 wrData, rdData;
331
332 regHold[i] = REG_READ(ah, addr);
333 for (j = 0; j < 0x100; j++) {
334 wrData = (j << 16) | j;
335 REG_WRITE(ah, addr, wrData);
336 rdData = REG_READ(ah, addr);
337 if (rdData != wrData) {
338 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
339 "address test failed "
340 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
341 addr, wrData, rdData);
342 return false;
343 }
344 }
345 for (j = 0; j < 4; j++) {
346 wrData = patternData[j];
347 REG_WRITE(ah, addr, wrData);
348 rdData = REG_READ(ah, addr);
349 if (wrData != rdData) {
350 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
351 "address test failed "
352 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
353 addr, wrData, rdData);
354 return false;
355 }
356 }
357 REG_WRITE(ah, regAddr[i], regHold[i]);
358 }
359 udelay(100);
360
361 return true;
362 }
363
364 static const char *ath9k_hw_devname(u16 devid)
365 {
366 switch (devid) {
367 case AR5416_DEVID_PCI:
368 return "Atheros 5416";
369 case AR5416_DEVID_PCIE:
370 return "Atheros 5418";
371 case AR9160_DEVID_PCI:
372 return "Atheros 9160";
373 case AR5416_AR9100_DEVID:
374 return "Atheros 9100";
375 case AR9280_DEVID_PCI:
376 case AR9280_DEVID_PCIE:
377 return "Atheros 9280";
378 case AR9285_DEVID_PCIE:
379 return "Atheros 9285";
380 case AR5416_DEVID_AR9287_PCI:
381 case AR5416_DEVID_AR9287_PCIE:
382 return "Atheros 9287";
383 }
384
385 return NULL;
386 }
387
388 static void ath9k_hw_init_config(struct ath_hw *ah)
389 {
390 int i;
391
392 ah->config.dma_beacon_response_time = 2;
393 ah->config.sw_beacon_response_time = 10;
394 ah->config.additional_swba_backoff = 0;
395 ah->config.ack_6mb = 0x0;
396 ah->config.cwm_ignore_extcca = 0;
397 ah->config.pcie_powersave_enable = 0;
398 ah->config.pcie_clock_req = 0;
399 ah->config.pcie_waen = 0;
400 ah->config.analog_shiftreg = 1;
401 ah->config.ofdm_trig_low = 200;
402 ah->config.ofdm_trig_high = 500;
403 ah->config.cck_trig_high = 200;
404 ah->config.cck_trig_low = 100;
405 ah->config.enable_ani = 1;
406 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
407 ah->config.antenna_switch_swap = 0;
408
409 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
410 ah->config.spurchans[i][0] = AR_NO_SPUR;
411 ah->config.spurchans[i][1] = AR_NO_SPUR;
412 }
413
414 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
415 ah->config.ht_enable = 1;
416 else
417 ah->config.ht_enable = 0;
418
419 ah->config.intr_mitigation = true;
420
421 /*
422 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
423 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
424 * This means we use it for all AR5416 devices, and the few
425 * minor PCI AR9280 devices out there.
426 *
427 * Serialization is required because these devices do not handle
428 * well the case of two concurrent reads/writes due to the latency
429 * involved. During one read/write another read/write can be issued
430 * on another CPU while the previous read/write may still be working
431 * on our hardware, if we hit this case the hardware poops in a loop.
432 * We prevent this by serializing reads and writes.
433 *
434 * This issue is not present on PCI-Express devices or pre-AR5416
435 * devices (legacy, 802.11abg).
436 */
437 if (num_possible_cpus() > 1)
438 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
439 }
440
441 static void ath9k_hw_init_defaults(struct ath_hw *ah)
442 {
443 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
444
445 regulatory->country_code = CTRY_DEFAULT;
446 regulatory->power_limit = MAX_RATE_POWER;
447 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
448
449 ah->hw_version.magic = AR5416_MAGIC;
450 ah->hw_version.subvendorid = 0;
451
452 ah->ah_flags = 0;
453 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
454 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
455 if (!AR_SREV_9100(ah))
456 ah->ah_flags = AH_USE_EEPROM;
457
458 ah->atim_window = 0;
459 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
460 ah->beacon_interval = 100;
461 ah->enable_32kHz_clock = DONT_USE_32KHZ;
462 ah->slottime = (u32) -1;
463 ah->acktimeout = (u32) -1;
464 ah->ctstimeout = (u32) -1;
465 ah->globaltxtimeout = (u32) -1;
466
467 ah->gbeacon_rate = 0;
468
469 ah->power_mode = ATH9K_PM_UNDEFINED;
470 }
471
472 static int ath9k_hw_rfattach(struct ath_hw *ah)
473 {
474 bool rfStatus = false;
475 int ecode = 0;
476
477 rfStatus = ath9k_hw_init_rf(ah, &ecode);
478 if (!rfStatus) {
479 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
480 "RF setup failed, status: %u\n", ecode);
481 return ecode;
482 }
483
484 return 0;
485 }
486
487 static int ath9k_hw_rf_claim(struct ath_hw *ah)
488 {
489 u32 val;
490
491 REG_WRITE(ah, AR_PHY(0), 0x00000007);
492
493 val = ath9k_hw_get_radiorev(ah);
494 switch (val & AR_RADIO_SREV_MAJOR) {
495 case 0:
496 val = AR_RAD5133_SREV_MAJOR;
497 break;
498 case AR_RAD5133_SREV_MAJOR:
499 case AR_RAD5122_SREV_MAJOR:
500 case AR_RAD2133_SREV_MAJOR:
501 case AR_RAD2122_SREV_MAJOR:
502 break;
503 default:
504 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
505 "Radio Chip Rev 0x%02X not supported\n",
506 val & AR_RADIO_SREV_MAJOR);
507 return -EOPNOTSUPP;
508 }
509
510 ah->hw_version.analog5GhzRev = val;
511
512 return 0;
513 }
514
515 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
516 {
517 u32 sum;
518 int i;
519 u16 eeval;
520
521 sum = 0;
522 for (i = 0; i < 3; i++) {
523 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
524 sum += eeval;
525 ah->macaddr[2 * i] = eeval >> 8;
526 ah->macaddr[2 * i + 1] = eeval & 0xff;
527 }
528 if (sum == 0 || sum == 0xffff * 3)
529 return -EADDRNOTAVAIL;
530
531 return 0;
532 }
533
534 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
535 {
536 u32 rxgain_type;
537
538 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
539 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
540
541 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
542 INIT_INI_ARRAY(&ah->iniModesRxGain,
543 ar9280Modes_backoff_13db_rxgain_9280_2,
544 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
545 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
546 INIT_INI_ARRAY(&ah->iniModesRxGain,
547 ar9280Modes_backoff_23db_rxgain_9280_2,
548 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
549 else
550 INIT_INI_ARRAY(&ah->iniModesRxGain,
551 ar9280Modes_original_rxgain_9280_2,
552 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
553 } else {
554 INIT_INI_ARRAY(&ah->iniModesRxGain,
555 ar9280Modes_original_rxgain_9280_2,
556 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
557 }
558 }
559
560 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
561 {
562 u32 txgain_type;
563
564 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
565 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
566
567 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
568 INIT_INI_ARRAY(&ah->iniModesTxGain,
569 ar9280Modes_high_power_tx_gain_9280_2,
570 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
571 else
572 INIT_INI_ARRAY(&ah->iniModesTxGain,
573 ar9280Modes_original_tx_gain_9280_2,
574 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
575 } else {
576 INIT_INI_ARRAY(&ah->iniModesTxGain,
577 ar9280Modes_original_tx_gain_9280_2,
578 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
579 }
580 }
581
582 static int ath9k_hw_post_init(struct ath_hw *ah)
583 {
584 int ecode;
585
586 if (!ath9k_hw_chip_test(ah))
587 return -ENODEV;
588
589 ecode = ath9k_hw_rf_claim(ah);
590 if (ecode != 0)
591 return ecode;
592
593 ecode = ath9k_hw_eeprom_init(ah);
594 if (ecode != 0)
595 return ecode;
596
597 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
598 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
599
600 ecode = ath9k_hw_rfattach(ah);
601 if (ecode != 0)
602 return ecode;
603
604 if (!AR_SREV_9100(ah)) {
605 ath9k_hw_ani_setup(ah);
606 ath9k_hw_ani_init(ah);
607 }
608
609 return 0;
610 }
611
612 static bool ath9k_hw_devid_supported(u16 devid)
613 {
614 switch (devid) {
615 case AR5416_DEVID_PCI:
616 case AR5416_DEVID_PCIE:
617 case AR5416_AR9100_DEVID:
618 case AR9160_DEVID_PCI:
619 case AR9280_DEVID_PCI:
620 case AR9280_DEVID_PCIE:
621 case AR9285_DEVID_PCIE:
622 case AR5416_DEVID_AR9287_PCI:
623 case AR5416_DEVID_AR9287_PCIE:
624 case AR2427_DEVID_PCIE:
625 return true;
626 default:
627 break;
628 }
629 return false;
630 }
631
632 static bool ath9k_hw_macversion_supported(u32 macversion)
633 {
634 switch (macversion) {
635 case AR_SREV_VERSION_5416_PCI:
636 case AR_SREV_VERSION_5416_PCIE:
637 case AR_SREV_VERSION_9160:
638 case AR_SREV_VERSION_9100:
639 case AR_SREV_VERSION_9280:
640 case AR_SREV_VERSION_9285:
641 case AR_SREV_VERSION_9287:
642 return true;
643 /* Not yet */
644 case AR_SREV_VERSION_9271:
645 default:
646 break;
647 }
648 return false;
649 }
650
651 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
652 {
653 if (AR_SREV_9160_10_OR_LATER(ah)) {
654 if (AR_SREV_9280_10_OR_LATER(ah)) {
655 ah->iq_caldata.calData = &iq_cal_single_sample;
656 ah->adcgain_caldata.calData =
657 &adc_gain_cal_single_sample;
658 ah->adcdc_caldata.calData =
659 &adc_dc_cal_single_sample;
660 ah->adcdc_calinitdata.calData =
661 &adc_init_dc_cal;
662 } else {
663 ah->iq_caldata.calData = &iq_cal_multi_sample;
664 ah->adcgain_caldata.calData =
665 &adc_gain_cal_multi_sample;
666 ah->adcdc_caldata.calData =
667 &adc_dc_cal_multi_sample;
668 ah->adcdc_calinitdata.calData =
669 &adc_init_dc_cal;
670 }
671 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
672 }
673 }
674
675 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
676 {
677 if (AR_SREV_9271(ah)) {
678 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
679 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
680 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
681 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
682 return;
683 }
684
685 if (AR_SREV_9287_11_OR_LATER(ah)) {
686 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
687 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
688 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
689 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
690 if (ah->config.pcie_clock_req)
691 INIT_INI_ARRAY(&ah->iniPcieSerdes,
692 ar9287PciePhy_clkreq_off_L1_9287_1_1,
693 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
694 else
695 INIT_INI_ARRAY(&ah->iniPcieSerdes,
696 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
697 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
698 2);
699 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
700 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
701 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
702 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
703 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
704
705 if (ah->config.pcie_clock_req)
706 INIT_INI_ARRAY(&ah->iniPcieSerdes,
707 ar9287PciePhy_clkreq_off_L1_9287_1_0,
708 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
709 else
710 INIT_INI_ARRAY(&ah->iniPcieSerdes,
711 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
712 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
713 2);
714 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
715
716
717 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
718 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
719 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
720 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
721
722 if (ah->config.pcie_clock_req) {
723 INIT_INI_ARRAY(&ah->iniPcieSerdes,
724 ar9285PciePhy_clkreq_off_L1_9285_1_2,
725 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
726 } else {
727 INIT_INI_ARRAY(&ah->iniPcieSerdes,
728 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
729 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
730 2);
731 }
732 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
733 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
734 ARRAY_SIZE(ar9285Modes_9285), 6);
735 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
736 ARRAY_SIZE(ar9285Common_9285), 2);
737
738 if (ah->config.pcie_clock_req) {
739 INIT_INI_ARRAY(&ah->iniPcieSerdes,
740 ar9285PciePhy_clkreq_off_L1_9285,
741 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
742 } else {
743 INIT_INI_ARRAY(&ah->iniPcieSerdes,
744 ar9285PciePhy_clkreq_always_on_L1_9285,
745 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
746 }
747 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
748 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
749 ARRAY_SIZE(ar9280Modes_9280_2), 6);
750 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
751 ARRAY_SIZE(ar9280Common_9280_2), 2);
752
753 if (ah->config.pcie_clock_req) {
754 INIT_INI_ARRAY(&ah->iniPcieSerdes,
755 ar9280PciePhy_clkreq_off_L1_9280,
756 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
757 } else {
758 INIT_INI_ARRAY(&ah->iniPcieSerdes,
759 ar9280PciePhy_clkreq_always_on_L1_9280,
760 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
761 }
762 INIT_INI_ARRAY(&ah->iniModesAdditional,
763 ar9280Modes_fast_clock_9280_2,
764 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
765 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
766 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
767 ARRAY_SIZE(ar9280Modes_9280), 6);
768 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
769 ARRAY_SIZE(ar9280Common_9280), 2);
770 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
771 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
772 ARRAY_SIZE(ar5416Modes_9160), 6);
773 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
774 ARRAY_SIZE(ar5416Common_9160), 2);
775 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
776 ARRAY_SIZE(ar5416Bank0_9160), 2);
777 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
778 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
779 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
780 ARRAY_SIZE(ar5416Bank1_9160), 2);
781 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
782 ARRAY_SIZE(ar5416Bank2_9160), 2);
783 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
784 ARRAY_SIZE(ar5416Bank3_9160), 3);
785 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
786 ARRAY_SIZE(ar5416Bank6_9160), 3);
787 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
788 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
789 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
790 ARRAY_SIZE(ar5416Bank7_9160), 2);
791 if (AR_SREV_9160_11(ah)) {
792 INIT_INI_ARRAY(&ah->iniAddac,
793 ar5416Addac_91601_1,
794 ARRAY_SIZE(ar5416Addac_91601_1), 2);
795 } else {
796 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
797 ARRAY_SIZE(ar5416Addac_9160), 2);
798 }
799 } else if (AR_SREV_9100_OR_LATER(ah)) {
800 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
801 ARRAY_SIZE(ar5416Modes_9100), 6);
802 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
803 ARRAY_SIZE(ar5416Common_9100), 2);
804 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
805 ARRAY_SIZE(ar5416Bank0_9100), 2);
806 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
807 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
808 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
809 ARRAY_SIZE(ar5416Bank1_9100), 2);
810 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
811 ARRAY_SIZE(ar5416Bank2_9100), 2);
812 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
813 ARRAY_SIZE(ar5416Bank3_9100), 3);
814 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
815 ARRAY_SIZE(ar5416Bank6_9100), 3);
816 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
817 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
818 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
819 ARRAY_SIZE(ar5416Bank7_9100), 2);
820 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
821 ARRAY_SIZE(ar5416Addac_9100), 2);
822 } else {
823 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
824 ARRAY_SIZE(ar5416Modes), 6);
825 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
826 ARRAY_SIZE(ar5416Common), 2);
827 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
828 ARRAY_SIZE(ar5416Bank0), 2);
829 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
830 ARRAY_SIZE(ar5416BB_RfGain), 3);
831 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
832 ARRAY_SIZE(ar5416Bank1), 2);
833 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
834 ARRAY_SIZE(ar5416Bank2), 2);
835 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
836 ARRAY_SIZE(ar5416Bank3), 3);
837 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
838 ARRAY_SIZE(ar5416Bank6), 3);
839 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
840 ARRAY_SIZE(ar5416Bank6TPC), 3);
841 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
842 ARRAY_SIZE(ar5416Bank7), 2);
843 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
844 ARRAY_SIZE(ar5416Addac), 2);
845 }
846 }
847
848 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
849 {
850 if (AR_SREV_9287_11_OR_LATER(ah))
851 INIT_INI_ARRAY(&ah->iniModesRxGain,
852 ar9287Modes_rx_gain_9287_1_1,
853 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
854 else if (AR_SREV_9287_10(ah))
855 INIT_INI_ARRAY(&ah->iniModesRxGain,
856 ar9287Modes_rx_gain_9287_1_0,
857 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
858 else if (AR_SREV_9280_20(ah))
859 ath9k_hw_init_rxgain_ini(ah);
860
861 if (AR_SREV_9287_11_OR_LATER(ah)) {
862 INIT_INI_ARRAY(&ah->iniModesTxGain,
863 ar9287Modes_tx_gain_9287_1_1,
864 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
865 } else if (AR_SREV_9287_10(ah)) {
866 INIT_INI_ARRAY(&ah->iniModesTxGain,
867 ar9287Modes_tx_gain_9287_1_0,
868 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
869 } else if (AR_SREV_9280_20(ah)) {
870 ath9k_hw_init_txgain_ini(ah);
871 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
872 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
873
874 /* txgain table */
875 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
876 INIT_INI_ARRAY(&ah->iniModesTxGain,
877 ar9285Modes_high_power_tx_gain_9285_1_2,
878 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
879 } else {
880 INIT_INI_ARRAY(&ah->iniModesTxGain,
881 ar9285Modes_original_tx_gain_9285_1_2,
882 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
883 }
884
885 }
886 }
887
888 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
889 {
890 u32 i, j;
891
892 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
893
894 /* EEPROM Fixup */
895 for (i = 0; i < ah->iniModes.ia_rows; i++) {
896 u32 reg = INI_RA(&ah->iniModes, i, 0);
897
898 for (j = 1; j < ah->iniModes.ia_columns; j++) {
899 u32 val = INI_RA(&ah->iniModes, i, j);
900
901 INI_RA(&ah->iniModes, i, j) =
902 ath9k_hw_ini_fixup(ah,
903 &ah->eeprom.def,
904 reg, val);
905 }
906 }
907 }
908 }
909
910 int ath9k_hw_init(struct ath_hw *ah)
911 {
912 int r = 0;
913
914 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
915 return -EOPNOTSUPP;
916
917 ath9k_hw_init_defaults(ah);
918 ath9k_hw_init_config(ah);
919
920 ath9k_hw_read_revisions(ah);
921
922 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
923 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
924 return -EIO;
925 }
926
927 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
928 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
929 return -EIO;
930 }
931
932 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
933 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
934 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
935 !ah->is_pciexpress)) {
936 ah->config.serialize_regmode =
937 SER_REG_MODE_ON;
938 } else {
939 ah->config.serialize_regmode =
940 SER_REG_MODE_OFF;
941 }
942 }
943
944 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
945 ah->config.serialize_regmode);
946
947 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
948 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
949 else
950 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
951
952 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
953 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
954 "Mac Chip Rev 0x%02x.%x is not supported by "
955 "this driver\n", ah->hw_version.macVersion,
956 ah->hw_version.macRev);
957 return -EOPNOTSUPP;
958 }
959
960 if (AR_SREV_9100(ah)) {
961 ah->iq_caldata.calData = &iq_cal_multi_sample;
962 ah->supp_cals = IQ_MISMATCH_CAL;
963 ah->is_pciexpress = false;
964 }
965
966 if (AR_SREV_9271(ah))
967 ah->is_pciexpress = false;
968
969 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
970
971 ath9k_hw_init_cal_settings(ah);
972
973 ah->ani_function = ATH9K_ANI_ALL;
974 if (AR_SREV_9280_10_OR_LATER(ah))
975 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
976
977 ath9k_hw_init_mode_regs(ah);
978
979 if (ah->is_pciexpress)
980 ath9k_hw_configpcipowersave(ah, 0, 0);
981 else
982 ath9k_hw_disablepcie(ah);
983
984 r = ath9k_hw_post_init(ah);
985 if (r)
986 return r;
987
988 ath9k_hw_init_mode_gain_regs(ah);
989 ath9k_hw_fill_cap_info(ah);
990 ath9k_hw_init_eeprom_fix(ah);
991
992 r = ath9k_hw_init_macaddr(ah);
993 if (r) {
994 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
995 "Failed to initialize MAC address\n");
996 return r;
997 }
998
999 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1000 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
1001 else
1002 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
1003
1004 ath9k_init_nfcal_hist_buffer(ah);
1005
1006 return 0;
1007 }
1008
1009 static void ath9k_hw_init_bb(struct ath_hw *ah,
1010 struct ath9k_channel *chan)
1011 {
1012 u32 synthDelay;
1013
1014 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1015 if (IS_CHAN_B(chan))
1016 synthDelay = (4 * synthDelay) / 22;
1017 else
1018 synthDelay /= 10;
1019
1020 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1021
1022 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1023 }
1024
1025 static void ath9k_hw_init_qos(struct ath_hw *ah)
1026 {
1027 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1028 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1029
1030 REG_WRITE(ah, AR_QOS_NO_ACK,
1031 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1032 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1033 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1034
1035 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1036 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1037 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1038 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1039 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1040 }
1041
1042 static void ath9k_hw_init_pll(struct ath_hw *ah,
1043 struct ath9k_channel *chan)
1044 {
1045 u32 pll;
1046
1047 if (AR_SREV_9100(ah)) {
1048 if (chan && IS_CHAN_5GHZ(chan))
1049 pll = 0x1450;
1050 else
1051 pll = 0x1458;
1052 } else {
1053 if (AR_SREV_9280_10_OR_LATER(ah)) {
1054 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1055
1056 if (chan && IS_CHAN_HALF_RATE(chan))
1057 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1058 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1059 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1060
1061 if (chan && IS_CHAN_5GHZ(chan)) {
1062 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1063
1064
1065 if (AR_SREV_9280_20(ah)) {
1066 if (((chan->channel % 20) == 0)
1067 || ((chan->channel % 10) == 0))
1068 pll = 0x2850;
1069 else
1070 pll = 0x142c;
1071 }
1072 } else {
1073 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1074 }
1075
1076 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1077
1078 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1079
1080 if (chan && IS_CHAN_HALF_RATE(chan))
1081 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1082 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1083 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1084
1085 if (chan && IS_CHAN_5GHZ(chan))
1086 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1087 else
1088 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1089 } else {
1090 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1091
1092 if (chan && IS_CHAN_HALF_RATE(chan))
1093 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1094 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1095 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1096
1097 if (chan && IS_CHAN_5GHZ(chan))
1098 pll |= SM(0xa, AR_RTC_PLL_DIV);
1099 else
1100 pll |= SM(0xb, AR_RTC_PLL_DIV);
1101 }
1102 }
1103 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1104
1105 udelay(RTC_PLL_SETTLE_DELAY);
1106
1107 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1108 }
1109
1110 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1111 {
1112 int rx_chainmask, tx_chainmask;
1113
1114 rx_chainmask = ah->rxchainmask;
1115 tx_chainmask = ah->txchainmask;
1116
1117 switch (rx_chainmask) {
1118 case 0x5:
1119 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1120 AR_PHY_SWAP_ALT_CHAIN);
1121 case 0x3:
1122 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1123 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1124 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1125 break;
1126 }
1127 case 0x1:
1128 case 0x2:
1129 case 0x7:
1130 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1131 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1132 break;
1133 default:
1134 break;
1135 }
1136
1137 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1138 if (tx_chainmask == 0x5) {
1139 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1140 AR_PHY_SWAP_ALT_CHAIN);
1141 }
1142 if (AR_SREV_9100(ah))
1143 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1144 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1145 }
1146
1147 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1148 enum nl80211_iftype opmode)
1149 {
1150 ah->mask_reg = AR_IMR_TXERR |
1151 AR_IMR_TXURN |
1152 AR_IMR_RXERR |
1153 AR_IMR_RXORN |
1154 AR_IMR_BCNMISC;
1155
1156 if (ah->config.intr_mitigation)
1157 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1158 else
1159 ah->mask_reg |= AR_IMR_RXOK;
1160
1161 ah->mask_reg |= AR_IMR_TXOK;
1162
1163 if (opmode == NL80211_IFTYPE_AP)
1164 ah->mask_reg |= AR_IMR_MIB;
1165
1166 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1167 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1168
1169 if (!AR_SREV_9100(ah)) {
1170 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1171 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1172 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1173 }
1174 }
1175
1176 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1177 {
1178 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1179 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1180 ah->acktimeout = (u32) -1;
1181 return false;
1182 } else {
1183 REG_RMW_FIELD(ah, AR_TIME_OUT,
1184 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1185 ah->acktimeout = us;
1186 return true;
1187 }
1188 }
1189
1190 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1191 {
1192 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1193 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1194 ah->ctstimeout = (u32) -1;
1195 return false;
1196 } else {
1197 REG_RMW_FIELD(ah, AR_TIME_OUT,
1198 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1199 ah->ctstimeout = us;
1200 return true;
1201 }
1202 }
1203
1204 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1205 {
1206 if (tu > 0xFFFF) {
1207 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1208 "bad global tx timeout %u\n", tu);
1209 ah->globaltxtimeout = (u32) -1;
1210 return false;
1211 } else {
1212 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1213 ah->globaltxtimeout = tu;
1214 return true;
1215 }
1216 }
1217
1218 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1219 {
1220 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1221 ah->misc_mode);
1222
1223 if (ah->misc_mode != 0)
1224 REG_WRITE(ah, AR_PCU_MISC,
1225 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1226 if (ah->slottime != (u32) -1)
1227 ath9k_hw_setslottime(ah, ah->slottime);
1228 if (ah->acktimeout != (u32) -1)
1229 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1230 if (ah->ctstimeout != (u32) -1)
1231 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1232 if (ah->globaltxtimeout != (u32) -1)
1233 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1234 }
1235
1236 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1237 {
1238 return vendorid == ATHEROS_VENDOR_ID ?
1239 ath9k_hw_devname(devid) : NULL;
1240 }
1241
1242 void ath9k_hw_detach(struct ath_hw *ah)
1243 {
1244 if (!AR_SREV_9100(ah))
1245 ath9k_hw_ani_disable(ah);
1246
1247 ath9k_hw_rf_free(ah);
1248 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1249 kfree(ah);
1250 ah = NULL;
1251 }
1252
1253 /*******/
1254 /* INI */
1255 /*******/
1256
1257 static void ath9k_hw_override_ini(struct ath_hw *ah,
1258 struct ath9k_channel *chan)
1259 {
1260 u32 val;
1261
1262 if (AR_SREV_9271(ah)) {
1263 /*
1264 * Enable spectral scan to solution for issues with stuck
1265 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1266 * AR9271 1.1
1267 */
1268 if (AR_SREV_9271_10(ah)) {
1269 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1270 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1271 }
1272 else if (AR_SREV_9271_11(ah))
1273 /*
1274 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1275 * present on AR9271 1.1
1276 */
1277 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1278 return;
1279 }
1280
1281 /*
1282 * Set the RX_ABORT and RX_DIS and clear if off only after
1283 * RXE is set for MAC. This prevents frames with corrupted
1284 * descriptor status.
1285 */
1286 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1287
1288 if (AR_SREV_9280_10_OR_LATER(ah)) {
1289 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1290 (~AR_PCU_MISC_MODE2_HWWAR1);
1291
1292 if (AR_SREV_9287_10_OR_LATER(ah))
1293 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1294
1295 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1296 }
1297
1298 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1299 AR_SREV_9280_10_OR_LATER(ah))
1300 return;
1301 /*
1302 * Disable BB clock gating
1303 * Necessary to avoid issues on AR5416 2.0
1304 */
1305 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1306
1307 /*
1308 * Disable RIFS search on some chips to avoid baseband
1309 * hang issues.
1310 */
1311 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1312 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1313 val &= ~AR_PHY_RIFS_INIT_DELAY;
1314 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1315 }
1316 }
1317
1318 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1319 struct ar5416_eeprom_def *pEepData,
1320 u32 reg, u32 value)
1321 {
1322 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1323
1324 switch (ah->hw_version.devid) {
1325 case AR9280_DEVID_PCI:
1326 if (reg == 0x7894) {
1327 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1328 "ini VAL: %x EEPROM: %x\n", value,
1329 (pBase->version & 0xff));
1330
1331 if ((pBase->version & 0xff) > 0x0a) {
1332 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1333 "PWDCLKIND: %d\n",
1334 pBase->pwdclkind);
1335 value &= ~AR_AN_TOP2_PWDCLKIND;
1336 value |= AR_AN_TOP2_PWDCLKIND &
1337 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1338 } else {
1339 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1340 "PWDCLKIND Earlier Rev\n");
1341 }
1342
1343 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1344 "final ini VAL: %x\n", value);
1345 }
1346 break;
1347 }
1348
1349 return value;
1350 }
1351
1352 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1353 struct ar5416_eeprom_def *pEepData,
1354 u32 reg, u32 value)
1355 {
1356 if (ah->eep_map == EEP_MAP_4KBITS)
1357 return value;
1358 else
1359 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1360 }
1361
1362 static void ath9k_olc_init(struct ath_hw *ah)
1363 {
1364 u32 i;
1365
1366 if (OLC_FOR_AR9287_10_LATER) {
1367 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1368 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1369 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1370 AR9287_AN_TXPC0_TXPCMODE,
1371 AR9287_AN_TXPC0_TXPCMODE_S,
1372 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1373 udelay(100);
1374 } else {
1375 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1376 ah->originalGain[i] =
1377 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1378 AR_PHY_TX_GAIN);
1379 ah->PDADCdelta = 0;
1380 }
1381 }
1382
1383 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1384 struct ath9k_channel *chan)
1385 {
1386 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1387
1388 if (IS_CHAN_B(chan))
1389 ctl |= CTL_11B;
1390 else if (IS_CHAN_G(chan))
1391 ctl |= CTL_11G;
1392 else
1393 ctl |= CTL_11A;
1394
1395 return ctl;
1396 }
1397
1398 static int ath9k_hw_process_ini(struct ath_hw *ah,
1399 struct ath9k_channel *chan,
1400 enum ath9k_ht_macmode macmode)
1401 {
1402 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1403 int i, regWrites = 0;
1404 struct ieee80211_channel *channel = chan->chan;
1405 u32 modesIndex, freqIndex;
1406
1407 switch (chan->chanmode) {
1408 case CHANNEL_A:
1409 case CHANNEL_A_HT20:
1410 modesIndex = 1;
1411 freqIndex = 1;
1412 break;
1413 case CHANNEL_A_HT40PLUS:
1414 case CHANNEL_A_HT40MINUS:
1415 modesIndex = 2;
1416 freqIndex = 1;
1417 break;
1418 case CHANNEL_G:
1419 case CHANNEL_G_HT20:
1420 case CHANNEL_B:
1421 modesIndex = 4;
1422 freqIndex = 2;
1423 break;
1424 case CHANNEL_G_HT40PLUS:
1425 case CHANNEL_G_HT40MINUS:
1426 modesIndex = 3;
1427 freqIndex = 2;
1428 break;
1429
1430 default:
1431 return -EINVAL;
1432 }
1433
1434 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1435 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1436 ah->eep_ops->set_addac(ah, chan);
1437
1438 if (AR_SREV_5416_22_OR_LATER(ah)) {
1439 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1440 } else {
1441 struct ar5416IniArray temp;
1442 u32 addacSize =
1443 sizeof(u32) * ah->iniAddac.ia_rows *
1444 ah->iniAddac.ia_columns;
1445
1446 memcpy(ah->addac5416_21,
1447 ah->iniAddac.ia_array, addacSize);
1448
1449 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1450
1451 temp.ia_array = ah->addac5416_21;
1452 temp.ia_columns = ah->iniAddac.ia_columns;
1453 temp.ia_rows = ah->iniAddac.ia_rows;
1454 REG_WRITE_ARRAY(&temp, 1, regWrites);
1455 }
1456
1457 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1458
1459 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1460 u32 reg = INI_RA(&ah->iniModes, i, 0);
1461 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1462
1463 REG_WRITE(ah, reg, val);
1464
1465 if (reg >= 0x7800 && reg < 0x78a0
1466 && ah->config.analog_shiftreg) {
1467 udelay(100);
1468 }
1469
1470 DO_DELAY(regWrites);
1471 }
1472
1473 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1474 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1475
1476 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1477 AR_SREV_9287_10_OR_LATER(ah))
1478 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1479
1480 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1481 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1482 u32 val = INI_RA(&ah->iniCommon, i, 1);
1483
1484 REG_WRITE(ah, reg, val);
1485
1486 if (reg >= 0x7800 && reg < 0x78a0
1487 && ah->config.analog_shiftreg) {
1488 udelay(100);
1489 }
1490
1491 DO_DELAY(regWrites);
1492 }
1493
1494 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1495
1496 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1497 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1498 regWrites);
1499 }
1500
1501 ath9k_hw_override_ini(ah, chan);
1502 ath9k_hw_set_regs(ah, chan, macmode);
1503 ath9k_hw_init_chain_masks(ah);
1504
1505 if (OLC_FOR_AR9280_20_LATER)
1506 ath9k_olc_init(ah);
1507
1508 ah->eep_ops->set_txpower(ah, chan,
1509 ath9k_regd_get_ctl(regulatory, chan),
1510 channel->max_antenna_gain * 2,
1511 channel->max_power * 2,
1512 min((u32) MAX_RATE_POWER,
1513 (u32) regulatory->power_limit));
1514
1515 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1516 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1517 "ar5416SetRfRegs failed\n");
1518 return -EIO;
1519 }
1520
1521 return 0;
1522 }
1523
1524 /****************************************/
1525 /* Reset and Channel Switching Routines */
1526 /****************************************/
1527
1528 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1529 {
1530 u32 rfMode = 0;
1531
1532 if (chan == NULL)
1533 return;
1534
1535 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1536 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1537
1538 if (!AR_SREV_9280_10_OR_LATER(ah))
1539 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1540 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1541
1542 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1543 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1544
1545 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1546 }
1547
1548 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1549 {
1550 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1551 }
1552
1553 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1554 {
1555 u32 regval;
1556
1557 /*
1558 * set AHB_MODE not to do cacheline prefetches
1559 */
1560 regval = REG_READ(ah, AR_AHB_MODE);
1561 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1562
1563 /*
1564 * let mac dma reads be in 128 byte chunks
1565 */
1566 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1567 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1568
1569 /*
1570 * Restore TX Trigger Level to its pre-reset value.
1571 * The initial value depends on whether aggregation is enabled, and is
1572 * adjusted whenever underruns are detected.
1573 */
1574 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1575
1576 /*
1577 * let mac dma writes be in 128 byte chunks
1578 */
1579 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1580 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1581
1582 /*
1583 * Setup receive FIFO threshold to hold off TX activities
1584 */
1585 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1586
1587 /*
1588 * reduce the number of usable entries in PCU TXBUF to avoid
1589 * wrap around issues.
1590 */
1591 if (AR_SREV_9285(ah)) {
1592 /* For AR9285 the number of Fifos are reduced to half.
1593 * So set the usable tx buf size also to half to
1594 * avoid data/delimiter underruns
1595 */
1596 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1597 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1598 } else if (!AR_SREV_9271(ah)) {
1599 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1600 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1601 }
1602 }
1603
1604 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1605 {
1606 u32 val;
1607
1608 val = REG_READ(ah, AR_STA_ID1);
1609 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1610 switch (opmode) {
1611 case NL80211_IFTYPE_AP:
1612 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1613 | AR_STA_ID1_KSRCH_MODE);
1614 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1615 break;
1616 case NL80211_IFTYPE_ADHOC:
1617 case NL80211_IFTYPE_MESH_POINT:
1618 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1619 | AR_STA_ID1_KSRCH_MODE);
1620 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1621 break;
1622 case NL80211_IFTYPE_STATION:
1623 case NL80211_IFTYPE_MONITOR:
1624 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1625 break;
1626 }
1627 }
1628
1629 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1630 u32 coef_scaled,
1631 u32 *coef_mantissa,
1632 u32 *coef_exponent)
1633 {
1634 u32 coef_exp, coef_man;
1635
1636 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1637 if ((coef_scaled >> coef_exp) & 0x1)
1638 break;
1639
1640 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1641
1642 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1643
1644 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1645 *coef_exponent = coef_exp - 16;
1646 }
1647
1648 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1649 struct ath9k_channel *chan)
1650 {
1651 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1652 u32 clockMhzScaled = 0x64000000;
1653 struct chan_centers centers;
1654
1655 if (IS_CHAN_HALF_RATE(chan))
1656 clockMhzScaled = clockMhzScaled >> 1;
1657 else if (IS_CHAN_QUARTER_RATE(chan))
1658 clockMhzScaled = clockMhzScaled >> 2;
1659
1660 ath9k_hw_get_channel_centers(ah, chan, &centers);
1661 coef_scaled = clockMhzScaled / centers.synth_center;
1662
1663 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1664 &ds_coef_exp);
1665
1666 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1667 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1668 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1669 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1670
1671 coef_scaled = (9 * coef_scaled) / 10;
1672
1673 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1674 &ds_coef_exp);
1675
1676 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1677 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1678 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1679 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1680 }
1681
1682 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1683 {
1684 u32 rst_flags;
1685 u32 tmpReg;
1686
1687 if (AR_SREV_9100(ah)) {
1688 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1689 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1690 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1691 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1692 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1693 }
1694
1695 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1696 AR_RTC_FORCE_WAKE_ON_INT);
1697
1698 if (AR_SREV_9100(ah)) {
1699 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1700 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1701 } else {
1702 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1703 if (tmpReg &
1704 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1705 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1706 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1707 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1708 } else {
1709 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1710 }
1711
1712 rst_flags = AR_RTC_RC_MAC_WARM;
1713 if (type == ATH9K_RESET_COLD)
1714 rst_flags |= AR_RTC_RC_MAC_COLD;
1715 }
1716
1717 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1718 udelay(50);
1719
1720 REG_WRITE(ah, AR_RTC_RC, 0);
1721 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1722 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1723 "RTC stuck in MAC reset\n");
1724 return false;
1725 }
1726
1727 if (!AR_SREV_9100(ah))
1728 REG_WRITE(ah, AR_RC, 0);
1729
1730 ath9k_hw_init_pll(ah, NULL);
1731
1732 if (AR_SREV_9100(ah))
1733 udelay(50);
1734
1735 return true;
1736 }
1737
1738 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1739 {
1740 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1741 AR_RTC_FORCE_WAKE_ON_INT);
1742
1743 if (!AR_SREV_9100(ah))
1744 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1745
1746 REG_WRITE(ah, AR_RTC_RESET, 0);
1747 udelay(2);
1748
1749 if (!AR_SREV_9100(ah))
1750 REG_WRITE(ah, AR_RC, 0);
1751
1752 REG_WRITE(ah, AR_RTC_RESET, 1);
1753
1754 if (!ath9k_hw_wait(ah,
1755 AR_RTC_STATUS,
1756 AR_RTC_STATUS_M,
1757 AR_RTC_STATUS_ON,
1758 AH_WAIT_TIMEOUT)) {
1759 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1760 return false;
1761 }
1762
1763 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1764 }
1765
1766 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1767 {
1768 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1769 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1770
1771 switch (type) {
1772 case ATH9K_RESET_POWER_ON:
1773 return ath9k_hw_set_reset_power_on(ah);
1774 case ATH9K_RESET_WARM:
1775 case ATH9K_RESET_COLD:
1776 return ath9k_hw_set_reset(ah, type);
1777 default:
1778 return false;
1779 }
1780 }
1781
1782 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1783 enum ath9k_ht_macmode macmode)
1784 {
1785 u32 phymode;
1786 u32 enableDacFifo = 0;
1787
1788 if (AR_SREV_9285_10_OR_LATER(ah))
1789 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1790 AR_PHY_FC_ENABLE_DAC_FIFO);
1791
1792 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1793 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1794
1795 if (IS_CHAN_HT40(chan)) {
1796 phymode |= AR_PHY_FC_DYN2040_EN;
1797
1798 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1799 (chan->chanmode == CHANNEL_G_HT40PLUS))
1800 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1801
1802 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1803 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1804 }
1805 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1806
1807 ath9k_hw_set11nmac2040(ah, macmode);
1808
1809 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1810 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1811 }
1812
1813 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1814 struct ath9k_channel *chan)
1815 {
1816 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1817 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1818 return false;
1819 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1820 return false;
1821
1822 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1823 return false;
1824
1825 ah->chip_fullsleep = false;
1826 ath9k_hw_init_pll(ah, chan);
1827 ath9k_hw_set_rfmode(ah, chan);
1828
1829 return true;
1830 }
1831
1832 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1833 struct ath9k_channel *chan,
1834 enum ath9k_ht_macmode macmode)
1835 {
1836 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1837 struct ieee80211_channel *channel = chan->chan;
1838 u32 synthDelay, qnum;
1839
1840 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1841 if (ath9k_hw_numtxpending(ah, qnum)) {
1842 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1843 "Transmit frames pending on queue %d\n", qnum);
1844 return false;
1845 }
1846 }
1847
1848 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1849 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1850 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1851 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1852 "Could not kill baseband RX\n");
1853 return false;
1854 }
1855
1856 ath9k_hw_set_regs(ah, chan, macmode);
1857
1858 if (AR_SREV_9280_10_OR_LATER(ah)) {
1859 ath9k_hw_ar9280_set_channel(ah, chan);
1860 } else {
1861 if (!(ath9k_hw_set_channel(ah, chan))) {
1862 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1863 "Failed to set channel\n");
1864 return false;
1865 }
1866 }
1867
1868 ah->eep_ops->set_txpower(ah, chan,
1869 ath9k_regd_get_ctl(regulatory, chan),
1870 channel->max_antenna_gain * 2,
1871 channel->max_power * 2,
1872 min((u32) MAX_RATE_POWER,
1873 (u32) regulatory->power_limit));
1874
1875 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1876 if (IS_CHAN_B(chan))
1877 synthDelay = (4 * synthDelay) / 22;
1878 else
1879 synthDelay /= 10;
1880
1881 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1882
1883 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1884
1885 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1886 ath9k_hw_set_delta_slope(ah, chan);
1887
1888 if (AR_SREV_9280_10_OR_LATER(ah))
1889 ath9k_hw_9280_spur_mitigate(ah, chan);
1890 else
1891 ath9k_hw_spur_mitigate(ah, chan);
1892
1893 if (!chan->oneTimeCalsDone)
1894 chan->oneTimeCalsDone = true;
1895
1896 return true;
1897 }
1898
1899 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1900 {
1901 int bb_spur = AR_NO_SPUR;
1902 int freq;
1903 int bin, cur_bin;
1904 int bb_spur_off, spur_subchannel_sd;
1905 int spur_freq_sd;
1906 int spur_delta_phase;
1907 int denominator;
1908 int upper, lower, cur_vit_mask;
1909 int tmp, newVal;
1910 int i;
1911 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1912 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1913 };
1914 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1915 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1916 };
1917 int inc[4] = { 0, 100, 0, 0 };
1918 struct chan_centers centers;
1919
1920 int8_t mask_m[123];
1921 int8_t mask_p[123];
1922 int8_t mask_amt;
1923 int tmp_mask;
1924 int cur_bb_spur;
1925 bool is2GHz = IS_CHAN_2GHZ(chan);
1926
1927 memset(&mask_m, 0, sizeof(int8_t) * 123);
1928 memset(&mask_p, 0, sizeof(int8_t) * 123);
1929
1930 ath9k_hw_get_channel_centers(ah, chan, &centers);
1931 freq = centers.synth_center;
1932
1933 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1934 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1935 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1936
1937 if (is2GHz)
1938 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1939 else
1940 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1941
1942 if (AR_NO_SPUR == cur_bb_spur)
1943 break;
1944 cur_bb_spur = cur_bb_spur - freq;
1945
1946 if (IS_CHAN_HT40(chan)) {
1947 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1948 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1949 bb_spur = cur_bb_spur;
1950 break;
1951 }
1952 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1953 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1954 bb_spur = cur_bb_spur;
1955 break;
1956 }
1957 }
1958
1959 if (AR_NO_SPUR == bb_spur) {
1960 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1961 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1962 return;
1963 } else {
1964 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1965 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1966 }
1967
1968 bin = bb_spur * 320;
1969
1970 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1971
1972 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1973 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1974 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1975 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1976 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1977
1978 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1979 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1980 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1981 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1982 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1983 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1984
1985 if (IS_CHAN_HT40(chan)) {
1986 if (bb_spur < 0) {
1987 spur_subchannel_sd = 1;
1988 bb_spur_off = bb_spur + 10;
1989 } else {
1990 spur_subchannel_sd = 0;
1991 bb_spur_off = bb_spur - 10;
1992 }
1993 } else {
1994 spur_subchannel_sd = 0;
1995 bb_spur_off = bb_spur;
1996 }
1997
1998 if (IS_CHAN_HT40(chan))
1999 spur_delta_phase =
2000 ((bb_spur * 262144) /
2001 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2002 else
2003 spur_delta_phase =
2004 ((bb_spur * 524288) /
2005 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2006
2007 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
2008 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
2009
2010 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2011 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2012 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2013 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
2014
2015 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
2016 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2017
2018 cur_bin = -6000;
2019 upper = bin + 100;
2020 lower = bin - 100;
2021
2022 for (i = 0; i < 4; i++) {
2023 int pilot_mask = 0;
2024 int chan_mask = 0;
2025 int bp = 0;
2026 for (bp = 0; bp < 30; bp++) {
2027 if ((cur_bin > lower) && (cur_bin < upper)) {
2028 pilot_mask = pilot_mask | 0x1 << bp;
2029 chan_mask = chan_mask | 0x1 << bp;
2030 }
2031 cur_bin += 100;
2032 }
2033 cur_bin += inc[i];
2034 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2035 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2036 }
2037
2038 cur_vit_mask = 6100;
2039 upper = bin + 120;
2040 lower = bin - 120;
2041
2042 for (i = 0; i < 123; i++) {
2043 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2044
2045 /* workaround for gcc bug #37014 */
2046 volatile int tmp_v = abs(cur_vit_mask - bin);
2047
2048 if (tmp_v < 75)
2049 mask_amt = 1;
2050 else
2051 mask_amt = 0;
2052 if (cur_vit_mask < 0)
2053 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2054 else
2055 mask_p[cur_vit_mask / 100] = mask_amt;
2056 }
2057 cur_vit_mask -= 100;
2058 }
2059
2060 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2061 | (mask_m[48] << 26) | (mask_m[49] << 24)
2062 | (mask_m[50] << 22) | (mask_m[51] << 20)
2063 | (mask_m[52] << 18) | (mask_m[53] << 16)
2064 | (mask_m[54] << 14) | (mask_m[55] << 12)
2065 | (mask_m[56] << 10) | (mask_m[57] << 8)
2066 | (mask_m[58] << 6) | (mask_m[59] << 4)
2067 | (mask_m[60] << 2) | (mask_m[61] << 0);
2068 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2069 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2070
2071 tmp_mask = (mask_m[31] << 28)
2072 | (mask_m[32] << 26) | (mask_m[33] << 24)
2073 | (mask_m[34] << 22) | (mask_m[35] << 20)
2074 | (mask_m[36] << 18) | (mask_m[37] << 16)
2075 | (mask_m[48] << 14) | (mask_m[39] << 12)
2076 | (mask_m[40] << 10) | (mask_m[41] << 8)
2077 | (mask_m[42] << 6) | (mask_m[43] << 4)
2078 | (mask_m[44] << 2) | (mask_m[45] << 0);
2079 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2080 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2081
2082 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2083 | (mask_m[18] << 26) | (mask_m[18] << 24)
2084 | (mask_m[20] << 22) | (mask_m[20] << 20)
2085 | (mask_m[22] << 18) | (mask_m[22] << 16)
2086 | (mask_m[24] << 14) | (mask_m[24] << 12)
2087 | (mask_m[25] << 10) | (mask_m[26] << 8)
2088 | (mask_m[27] << 6) | (mask_m[28] << 4)
2089 | (mask_m[29] << 2) | (mask_m[30] << 0);
2090 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2091 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2092
2093 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2094 | (mask_m[2] << 26) | (mask_m[3] << 24)
2095 | (mask_m[4] << 22) | (mask_m[5] << 20)
2096 | (mask_m[6] << 18) | (mask_m[7] << 16)
2097 | (mask_m[8] << 14) | (mask_m[9] << 12)
2098 | (mask_m[10] << 10) | (mask_m[11] << 8)
2099 | (mask_m[12] << 6) | (mask_m[13] << 4)
2100 | (mask_m[14] << 2) | (mask_m[15] << 0);
2101 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2102 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2103
2104 tmp_mask = (mask_p[15] << 28)
2105 | (mask_p[14] << 26) | (mask_p[13] << 24)
2106 | (mask_p[12] << 22) | (mask_p[11] << 20)
2107 | (mask_p[10] << 18) | (mask_p[9] << 16)
2108 | (mask_p[8] << 14) | (mask_p[7] << 12)
2109 | (mask_p[6] << 10) | (mask_p[5] << 8)
2110 | (mask_p[4] << 6) | (mask_p[3] << 4)
2111 | (mask_p[2] << 2) | (mask_p[1] << 0);
2112 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2113 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2114
2115 tmp_mask = (mask_p[30] << 28)
2116 | (mask_p[29] << 26) | (mask_p[28] << 24)
2117 | (mask_p[27] << 22) | (mask_p[26] << 20)
2118 | (mask_p[25] << 18) | (mask_p[24] << 16)
2119 | (mask_p[23] << 14) | (mask_p[22] << 12)
2120 | (mask_p[21] << 10) | (mask_p[20] << 8)
2121 | (mask_p[19] << 6) | (mask_p[18] << 4)
2122 | (mask_p[17] << 2) | (mask_p[16] << 0);
2123 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2124 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2125
2126 tmp_mask = (mask_p[45] << 28)
2127 | (mask_p[44] << 26) | (mask_p[43] << 24)
2128 | (mask_p[42] << 22) | (mask_p[41] << 20)
2129 | (mask_p[40] << 18) | (mask_p[39] << 16)
2130 | (mask_p[38] << 14) | (mask_p[37] << 12)
2131 | (mask_p[36] << 10) | (mask_p[35] << 8)
2132 | (mask_p[34] << 6) | (mask_p[33] << 4)
2133 | (mask_p[32] << 2) | (mask_p[31] << 0);
2134 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2135 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2136
2137 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2138 | (mask_p[59] << 26) | (mask_p[58] << 24)
2139 | (mask_p[57] << 22) | (mask_p[56] << 20)
2140 | (mask_p[55] << 18) | (mask_p[54] << 16)
2141 | (mask_p[53] << 14) | (mask_p[52] << 12)
2142 | (mask_p[51] << 10) | (mask_p[50] << 8)
2143 | (mask_p[49] << 6) | (mask_p[48] << 4)
2144 | (mask_p[47] << 2) | (mask_p[46] << 0);
2145 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2146 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2147 }
2148
2149 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2150 {
2151 int bb_spur = AR_NO_SPUR;
2152 int bin, cur_bin;
2153 int spur_freq_sd;
2154 int spur_delta_phase;
2155 int denominator;
2156 int upper, lower, cur_vit_mask;
2157 int tmp, new;
2158 int i;
2159 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2160 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2161 };
2162 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2163 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2164 };
2165 int inc[4] = { 0, 100, 0, 0 };
2166
2167 int8_t mask_m[123];
2168 int8_t mask_p[123];
2169 int8_t mask_amt;
2170 int tmp_mask;
2171 int cur_bb_spur;
2172 bool is2GHz = IS_CHAN_2GHZ(chan);
2173
2174 memset(&mask_m, 0, sizeof(int8_t) * 123);
2175 memset(&mask_p, 0, sizeof(int8_t) * 123);
2176
2177 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2178 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2179 if (AR_NO_SPUR == cur_bb_spur)
2180 break;
2181 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2182 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2183 bb_spur = cur_bb_spur;
2184 break;
2185 }
2186 }
2187
2188 if (AR_NO_SPUR == bb_spur)
2189 return;
2190
2191 bin = bb_spur * 32;
2192
2193 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2194 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2195 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2196 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2197 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2198
2199 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2200
2201 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2202 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2203 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2204 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2205 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2206 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2207
2208 spur_delta_phase = ((bb_spur * 524288) / 100) &
2209 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2210
2211 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2212 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2213
2214 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2215 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2216 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2217 REG_WRITE(ah, AR_PHY_TIMING11, new);
2218
2219 cur_bin = -6000;
2220 upper = bin + 100;
2221 lower = bin - 100;
2222
2223 for (i = 0; i < 4; i++) {
2224 int pilot_mask = 0;
2225 int chan_mask = 0;
2226 int bp = 0;
2227 for (bp = 0; bp < 30; bp++) {
2228 if ((cur_bin > lower) && (cur_bin < upper)) {
2229 pilot_mask = pilot_mask | 0x1 << bp;
2230 chan_mask = chan_mask | 0x1 << bp;
2231 }
2232 cur_bin += 100;
2233 }
2234 cur_bin += inc[i];
2235 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2236 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2237 }
2238
2239 cur_vit_mask = 6100;
2240 upper = bin + 120;
2241 lower = bin - 120;
2242
2243 for (i = 0; i < 123; i++) {
2244 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2245
2246 /* workaround for gcc bug #37014 */
2247 volatile int tmp_v = abs(cur_vit_mask - bin);
2248
2249 if (tmp_v < 75)
2250 mask_amt = 1;
2251 else
2252 mask_amt = 0;
2253 if (cur_vit_mask < 0)
2254 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2255 else
2256 mask_p[cur_vit_mask / 100] = mask_amt;
2257 }
2258 cur_vit_mask -= 100;
2259 }
2260
2261 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2262 | (mask_m[48] << 26) | (mask_m[49] << 24)
2263 | (mask_m[50] << 22) | (mask_m[51] << 20)
2264 | (mask_m[52] << 18) | (mask_m[53] << 16)
2265 | (mask_m[54] << 14) | (mask_m[55] << 12)
2266 | (mask_m[56] << 10) | (mask_m[57] << 8)
2267 | (mask_m[58] << 6) | (mask_m[59] << 4)
2268 | (mask_m[60] << 2) | (mask_m[61] << 0);
2269 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2270 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2271
2272 tmp_mask = (mask_m[31] << 28)
2273 | (mask_m[32] << 26) | (mask_m[33] << 24)
2274 | (mask_m[34] << 22) | (mask_m[35] << 20)
2275 | (mask_m[36] << 18) | (mask_m[37] << 16)
2276 | (mask_m[48] << 14) | (mask_m[39] << 12)
2277 | (mask_m[40] << 10) | (mask_m[41] << 8)
2278 | (mask_m[42] << 6) | (mask_m[43] << 4)
2279 | (mask_m[44] << 2) | (mask_m[45] << 0);
2280 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2281 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2282
2283 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2284 | (mask_m[18] << 26) | (mask_m[18] << 24)
2285 | (mask_m[20] << 22) | (mask_m[20] << 20)
2286 | (mask_m[22] << 18) | (mask_m[22] << 16)
2287 | (mask_m[24] << 14) | (mask_m[24] << 12)
2288 | (mask_m[25] << 10) | (mask_m[26] << 8)
2289 | (mask_m[27] << 6) | (mask_m[28] << 4)
2290 | (mask_m[29] << 2) | (mask_m[30] << 0);
2291 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2292 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2293
2294 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2295 | (mask_m[2] << 26) | (mask_m[3] << 24)
2296 | (mask_m[4] << 22) | (mask_m[5] << 20)
2297 | (mask_m[6] << 18) | (mask_m[7] << 16)
2298 | (mask_m[8] << 14) | (mask_m[9] << 12)
2299 | (mask_m[10] << 10) | (mask_m[11] << 8)
2300 | (mask_m[12] << 6) | (mask_m[13] << 4)
2301 | (mask_m[14] << 2) | (mask_m[15] << 0);
2302 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2303 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2304
2305 tmp_mask = (mask_p[15] << 28)
2306 | (mask_p[14] << 26) | (mask_p[13] << 24)
2307 | (mask_p[12] << 22) | (mask_p[11] << 20)
2308 | (mask_p[10] << 18) | (mask_p[9] << 16)
2309 | (mask_p[8] << 14) | (mask_p[7] << 12)
2310 | (mask_p[6] << 10) | (mask_p[5] << 8)
2311 | (mask_p[4] << 6) | (mask_p[3] << 4)
2312 | (mask_p[2] << 2) | (mask_p[1] << 0);
2313 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2314 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2315
2316 tmp_mask = (mask_p[30] << 28)
2317 | (mask_p[29] << 26) | (mask_p[28] << 24)
2318 | (mask_p[27] << 22) | (mask_p[26] << 20)
2319 | (mask_p[25] << 18) | (mask_p[24] << 16)
2320 | (mask_p[23] << 14) | (mask_p[22] << 12)
2321 | (mask_p[21] << 10) | (mask_p[20] << 8)
2322 | (mask_p[19] << 6) | (mask_p[18] << 4)
2323 | (mask_p[17] << 2) | (mask_p[16] << 0);
2324 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2325 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2326
2327 tmp_mask = (mask_p[45] << 28)
2328 | (mask_p[44] << 26) | (mask_p[43] << 24)
2329 | (mask_p[42] << 22) | (mask_p[41] << 20)
2330 | (mask_p[40] << 18) | (mask_p[39] << 16)
2331 | (mask_p[38] << 14) | (mask_p[37] << 12)
2332 | (mask_p[36] << 10) | (mask_p[35] << 8)
2333 | (mask_p[34] << 6) | (mask_p[33] << 4)
2334 | (mask_p[32] << 2) | (mask_p[31] << 0);
2335 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2336 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2337
2338 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2339 | (mask_p[59] << 26) | (mask_p[58] << 24)
2340 | (mask_p[57] << 22) | (mask_p[56] << 20)
2341 | (mask_p[55] << 18) | (mask_p[54] << 16)
2342 | (mask_p[53] << 14) | (mask_p[52] << 12)
2343 | (mask_p[51] << 10) | (mask_p[50] << 8)
2344 | (mask_p[49] << 6) | (mask_p[48] << 4)
2345 | (mask_p[47] << 2) | (mask_p[46] << 0);
2346 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2347 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2348 }
2349
2350 static void ath9k_enable_rfkill(struct ath_hw *ah)
2351 {
2352 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2353 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2354
2355 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2356 AR_GPIO_INPUT_MUX2_RFSILENT);
2357
2358 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2359 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2360 }
2361
2362 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2363 bool bChannelChange)
2364 {
2365 u32 saveLedState;
2366 struct ath_softc *sc = ah->ah_sc;
2367 struct ath9k_channel *curchan = ah->curchan;
2368 u32 saveDefAntenna;
2369 u32 macStaId1;
2370 u64 tsf = 0;
2371 int i, rx_chainmask, r;
2372
2373 ah->extprotspacing = sc->ht_extprotspacing;
2374 ah->txchainmask = sc->tx_chainmask;
2375 ah->rxchainmask = sc->rx_chainmask;
2376
2377 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2378 return -EIO;
2379
2380 if (curchan && !ah->chip_fullsleep)
2381 ath9k_hw_getnf(ah, curchan);
2382
2383 if (bChannelChange &&
2384 (ah->chip_fullsleep != true) &&
2385 (ah->curchan != NULL) &&
2386 (chan->channel != ah->curchan->channel) &&
2387 ((chan->channelFlags & CHANNEL_ALL) ==
2388 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2389 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2390 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2391
2392 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2393 ath9k_hw_loadnf(ah, ah->curchan);
2394 ath9k_hw_start_nfcal(ah);
2395 return 0;
2396 }
2397 }
2398
2399 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2400 if (saveDefAntenna == 0)
2401 saveDefAntenna = 1;
2402
2403 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2404
2405 /* For chips on which RTC reset is done, save TSF before it gets cleared */
2406 if (AR_SREV_9100(ah) ||
2407 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
2408 tsf = ath9k_hw_gettsf64(ah);
2409
2410 saveLedState = REG_READ(ah, AR_CFG_LED) &
2411 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2412 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2413
2414 ath9k_hw_mark_phy_inactive(ah);
2415
2416 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2417 REG_WRITE(ah,
2418 AR9271_RESET_POWER_DOWN_CONTROL,
2419 AR9271_RADIO_RF_RST);
2420 udelay(50);
2421 }
2422
2423 if (!ath9k_hw_chip_reset(ah, chan)) {
2424 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2425 return -EINVAL;
2426 }
2427
2428 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2429 ah->htc_reset_init = false;
2430 REG_WRITE(ah,
2431 AR9271_RESET_POWER_DOWN_CONTROL,
2432 AR9271_GATE_MAC_CTL);
2433 udelay(50);
2434 }
2435
2436 /* Restore TSF */
2437 if (tsf)
2438 ath9k_hw_settsf64(ah, tsf);
2439
2440 if (AR_SREV_9280_10_OR_LATER(ah))
2441 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2442
2443 if (AR_SREV_9287_12_OR_LATER(ah)) {
2444 /* Enable ASYNC FIFO */
2445 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2446 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2447 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2448 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2449 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2450 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2451 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2452 }
2453 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2454 if (r)
2455 return r;
2456
2457 /*
2458 * Some AR91xx SoC devices frequently fail to accept TSF writes
2459 * right after the chip reset. When that happens, write a new
2460 * value after the initvals have been applied, with an offset
2461 * based on measured time difference
2462 */
2463 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
2464 tsf += 1500;
2465 ath9k_hw_settsf64(ah, tsf);
2466 }
2467
2468 /* Setup MFP options for CCMP */
2469 if (AR_SREV_9280_20_OR_LATER(ah)) {
2470 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2471 * frames when constructing CCMP AAD. */
2472 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2473 0xc7ff);
2474 ah->sw_mgmt_crypto = false;
2475 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2476 /* Disable hardware crypto for management frames */
2477 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2478 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2479 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2480 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2481 ah->sw_mgmt_crypto = true;
2482 } else
2483 ah->sw_mgmt_crypto = true;
2484
2485 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2486 ath9k_hw_set_delta_slope(ah, chan);
2487
2488 if (AR_SREV_9280_10_OR_LATER(ah))
2489 ath9k_hw_9280_spur_mitigate(ah, chan);
2490 else
2491 ath9k_hw_spur_mitigate(ah, chan);
2492
2493 ah->eep_ops->set_board_values(ah, chan);
2494
2495 ath9k_hw_decrease_chain_power(ah, chan);
2496
2497 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2498 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2499 | macStaId1
2500 | AR_STA_ID1_RTS_USE_DEF
2501 | (ah->config.
2502 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2503 | ah->sta_id1_defaults);
2504 ath9k_hw_set_operating_mode(ah, ah->opmode);
2505
2506 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2507 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2508
2509 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2510
2511 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2512 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2513 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2514
2515 REG_WRITE(ah, AR_ISR, ~0);
2516
2517 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2518
2519 if (AR_SREV_9280_10_OR_LATER(ah))
2520 ath9k_hw_ar9280_set_channel(ah, chan);
2521 else
2522 if (!(ath9k_hw_set_channel(ah, chan)))
2523 return -EIO;
2524
2525 for (i = 0; i < AR_NUM_DCU; i++)
2526 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2527
2528 ah->intr_txqs = 0;
2529 for (i = 0; i < ah->caps.total_queues; i++)
2530 ath9k_hw_resettxqueue(ah, i);
2531
2532 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2533 ath9k_hw_init_qos(ah);
2534
2535 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2536 ath9k_enable_rfkill(ah);
2537
2538 ath9k_hw_init_user_settings(ah);
2539
2540 if (AR_SREV_9287_12_OR_LATER(ah)) {
2541 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2542 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2543 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2544 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2545 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2546 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2547
2548 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2549 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2550
2551 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2552 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2553 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2554 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2555 }
2556 if (AR_SREV_9287_12_OR_LATER(ah)) {
2557 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2558 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2559 }
2560
2561 REG_WRITE(ah, AR_STA_ID1,
2562 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2563
2564 ath9k_hw_set_dma(ah);
2565
2566 REG_WRITE(ah, AR_OBS, 8);
2567
2568 if (ah->config.intr_mitigation) {
2569 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2570 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2571 }
2572
2573 ath9k_hw_init_bb(ah, chan);
2574
2575 if (!ath9k_hw_init_cal(ah, chan))
2576 return -EIO;
2577
2578 rx_chainmask = ah->rxchainmask;
2579 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2580 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2581 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2582 }
2583
2584 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2585
2586 /*
2587 * For big endian systems turn on swapping for descriptors
2588 */
2589 if (AR_SREV_9100(ah)) {
2590 u32 mask;
2591 mask = REG_READ(ah, AR_CFG);
2592 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2593 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2594 "CFG Byte Swap Set 0x%x\n", mask);
2595 } else {
2596 mask =
2597 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2598 REG_WRITE(ah, AR_CFG, mask);
2599 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2600 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2601 }
2602 } else {
2603 /* Configure AR9271 target WLAN */
2604 if (AR_SREV_9271(ah))
2605 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2606 #ifdef __BIG_ENDIAN
2607 else
2608 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2609 #endif
2610 }
2611
2612 if (ah->ah_sc->sc_flags & SC_OP_BTCOEX_ENABLED)
2613 ath9k_hw_btcoex_enable(ah);
2614
2615 return 0;
2616 }
2617
2618 /************************/
2619 /* Key Cache Management */
2620 /************************/
2621
2622 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2623 {
2624 u32 keyType;
2625
2626 if (entry >= ah->caps.keycache_size) {
2627 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2628 "keychache entry %u out of range\n", entry);
2629 return false;
2630 }
2631
2632 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2633
2634 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2635 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2636 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2637 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2638 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2639 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2640 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2641 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2642
2643 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2644 u16 micentry = entry + 64;
2645
2646 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2647 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2648 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2649 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2650
2651 }
2652
2653 return true;
2654 }
2655
2656 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2657 {
2658 u32 macHi, macLo;
2659
2660 if (entry >= ah->caps.keycache_size) {
2661 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2662 "keychache entry %u out of range\n", entry);
2663 return false;
2664 }
2665
2666 if (mac != NULL) {
2667 macHi = (mac[5] << 8) | mac[4];
2668 macLo = (mac[3] << 24) |
2669 (mac[2] << 16) |
2670 (mac[1] << 8) |
2671 mac[0];
2672 macLo >>= 1;
2673 macLo |= (macHi & 1) << 31;
2674 macHi >>= 1;
2675 } else {
2676 macLo = macHi = 0;
2677 }
2678 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2679 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2680
2681 return true;
2682 }
2683
2684 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2685 const struct ath9k_keyval *k,
2686 const u8 *mac)
2687 {
2688 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2689 u32 key0, key1, key2, key3, key4;
2690 u32 keyType;
2691
2692 if (entry >= pCap->keycache_size) {
2693 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2694 "keycache entry %u out of range\n", entry);
2695 return false;
2696 }
2697
2698 switch (k->kv_type) {
2699 case ATH9K_CIPHER_AES_OCB:
2700 keyType = AR_KEYTABLE_TYPE_AES;
2701 break;
2702 case ATH9K_CIPHER_AES_CCM:
2703 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2704 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2705 "AES-CCM not supported by mac rev 0x%x\n",
2706 ah->hw_version.macRev);
2707 return false;
2708 }
2709 keyType = AR_KEYTABLE_TYPE_CCM;
2710 break;
2711 case ATH9K_CIPHER_TKIP:
2712 keyType = AR_KEYTABLE_TYPE_TKIP;
2713 if (ATH9K_IS_MIC_ENABLED(ah)
2714 && entry + 64 >= pCap->keycache_size) {
2715 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2716 "entry %u inappropriate for TKIP\n", entry);
2717 return false;
2718 }
2719 break;
2720 case ATH9K_CIPHER_WEP:
2721 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2722 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2723 "WEP key length %u too small\n", k->kv_len);
2724 return false;
2725 }
2726 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2727 keyType = AR_KEYTABLE_TYPE_40;
2728 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2729 keyType = AR_KEYTABLE_TYPE_104;
2730 else
2731 keyType = AR_KEYTABLE_TYPE_128;
2732 break;
2733 case ATH9K_CIPHER_CLR:
2734 keyType = AR_KEYTABLE_TYPE_CLR;
2735 break;
2736 default:
2737 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2738 "cipher %u not supported\n", k->kv_type);
2739 return false;
2740 }
2741
2742 key0 = get_unaligned_le32(k->kv_val + 0);
2743 key1 = get_unaligned_le16(k->kv_val + 4);
2744 key2 = get_unaligned_le32(k->kv_val + 6);
2745 key3 = get_unaligned_le16(k->kv_val + 10);
2746 key4 = get_unaligned_le32(k->kv_val + 12);
2747 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2748 key4 &= 0xff;
2749
2750 /*
2751 * Note: Key cache registers access special memory area that requires
2752 * two 32-bit writes to actually update the values in the internal
2753 * memory. Consequently, the exact order and pairs used here must be
2754 * maintained.
2755 */
2756
2757 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2758 u16 micentry = entry + 64;
2759
2760 /*
2761 * Write inverted key[47:0] first to avoid Michael MIC errors
2762 * on frames that could be sent or received at the same time.
2763 * The correct key will be written in the end once everything
2764 * else is ready.
2765 */
2766 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2767 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2768
2769 /* Write key[95:48] */
2770 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2771 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2772
2773 /* Write key[127:96] and key type */
2774 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2775 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2776
2777 /* Write MAC address for the entry */
2778 (void) ath9k_hw_keysetmac(ah, entry, mac);
2779
2780 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2781 /*
2782 * TKIP uses two key cache entries:
2783 * Michael MIC TX/RX keys in the same key cache entry
2784 * (idx = main index + 64):
2785 * key0 [31:0] = RX key [31:0]
2786 * key1 [15:0] = TX key [31:16]
2787 * key1 [31:16] = reserved
2788 * key2 [31:0] = RX key [63:32]
2789 * key3 [15:0] = TX key [15:0]
2790 * key3 [31:16] = reserved
2791 * key4 [31:0] = TX key [63:32]
2792 */
2793 u32 mic0, mic1, mic2, mic3, mic4;
2794
2795 mic0 = get_unaligned_le32(k->kv_mic + 0);
2796 mic2 = get_unaligned_le32(k->kv_mic + 4);
2797 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2798 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2799 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2800
2801 /* Write RX[31:0] and TX[31:16] */
2802 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2803 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2804
2805 /* Write RX[63:32] and TX[15:0] */
2806 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2807 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2808
2809 /* Write TX[63:32] and keyType(reserved) */
2810 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2811 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2812 AR_KEYTABLE_TYPE_CLR);
2813
2814 } else {
2815 /*
2816 * TKIP uses four key cache entries (two for group
2817 * keys):
2818 * Michael MIC TX/RX keys are in different key cache
2819 * entries (idx = main index + 64 for TX and
2820 * main index + 32 + 96 for RX):
2821 * key0 [31:0] = TX/RX MIC key [31:0]
2822 * key1 [31:0] = reserved
2823 * key2 [31:0] = TX/RX MIC key [63:32]
2824 * key3 [31:0] = reserved
2825 * key4 [31:0] = reserved
2826 *
2827 * Upper layer code will call this function separately
2828 * for TX and RX keys when these registers offsets are
2829 * used.
2830 */
2831 u32 mic0, mic2;
2832
2833 mic0 = get_unaligned_le32(k->kv_mic + 0);
2834 mic2 = get_unaligned_le32(k->kv_mic + 4);
2835
2836 /* Write MIC key[31:0] */
2837 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2838 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2839
2840 /* Write MIC key[63:32] */
2841 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2842 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2843
2844 /* Write TX[63:32] and keyType(reserved) */
2845 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2846 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2847 AR_KEYTABLE_TYPE_CLR);
2848 }
2849
2850 /* MAC address registers are reserved for the MIC entry */
2851 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2852 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2853
2854 /*
2855 * Write the correct (un-inverted) key[47:0] last to enable
2856 * TKIP now that all other registers are set with correct
2857 * values.
2858 */
2859 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2860 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2861 } else {
2862 /* Write key[47:0] */
2863 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2864 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2865
2866 /* Write key[95:48] */
2867 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2868 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2869
2870 /* Write key[127:96] and key type */
2871 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2872 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2873
2874 /* Write MAC address for the entry */
2875 (void) ath9k_hw_keysetmac(ah, entry, mac);
2876 }
2877
2878 return true;
2879 }
2880
2881 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2882 {
2883 if (entry < ah->caps.keycache_size) {
2884 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2885 if (val & AR_KEYTABLE_VALID)
2886 return true;
2887 }
2888 return false;
2889 }
2890
2891 /******************************/
2892 /* Power Management (Chipset) */
2893 /******************************/
2894
2895 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2896 {
2897 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2898 if (setChip) {
2899 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2900 AR_RTC_FORCE_WAKE_EN);
2901 if (!AR_SREV_9100(ah))
2902 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2903
2904 REG_CLR_BIT(ah, (AR_RTC_RESET),
2905 AR_RTC_RESET_EN);
2906 }
2907 }
2908
2909 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2910 {
2911 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2912 if (setChip) {
2913 struct ath9k_hw_capabilities *pCap = &ah->caps;
2914
2915 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2916 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2917 AR_RTC_FORCE_WAKE_ON_INT);
2918 } else {
2919 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2920 AR_RTC_FORCE_WAKE_EN);
2921 }
2922 }
2923 }
2924
2925 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2926 {
2927 u32 val;
2928 int i;
2929
2930 if (setChip) {
2931 if ((REG_READ(ah, AR_RTC_STATUS) &
2932 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2933 if (ath9k_hw_set_reset_reg(ah,
2934 ATH9K_RESET_POWER_ON) != true) {
2935 return false;
2936 }
2937 }
2938 if (AR_SREV_9100(ah))
2939 REG_SET_BIT(ah, AR_RTC_RESET,
2940 AR_RTC_RESET_EN);
2941
2942 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2943 AR_RTC_FORCE_WAKE_EN);
2944 udelay(50);
2945
2946 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2947 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2948 if (val == AR_RTC_STATUS_ON)
2949 break;
2950 udelay(50);
2951 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2952 AR_RTC_FORCE_WAKE_EN);
2953 }
2954 if (i == 0) {
2955 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2956 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2957 return false;
2958 }
2959 }
2960
2961 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2962
2963 return true;
2964 }
2965
2966 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2967 enum ath9k_power_mode mode)
2968 {
2969 int status = true, setChip = true;
2970 static const char *modes[] = {
2971 "AWAKE",
2972 "FULL-SLEEP",
2973 "NETWORK SLEEP",
2974 "UNDEFINED"
2975 };
2976
2977 if (ah->power_mode == mode)
2978 return status;
2979
2980 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2981 modes[ah->power_mode], modes[mode]);
2982
2983 switch (mode) {
2984 case ATH9K_PM_AWAKE:
2985 status = ath9k_hw_set_power_awake(ah, setChip);
2986 break;
2987 case ATH9K_PM_FULL_SLEEP:
2988 ath9k_set_power_sleep(ah, setChip);
2989 ah->chip_fullsleep = true;
2990 break;
2991 case ATH9K_PM_NETWORK_SLEEP:
2992 ath9k_set_power_network_sleep(ah, setChip);
2993 break;
2994 default:
2995 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2996 "Unknown power mode %u\n", mode);
2997 return false;
2998 }
2999 ah->power_mode = mode;
3000
3001 return status;
3002 }
3003
3004 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
3005 {
3006 unsigned long flags;
3007 bool ret;
3008
3009 spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
3010 ret = ath9k_hw_setpower_nolock(ah, mode);
3011 spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
3012
3013 return ret;
3014 }
3015
3016 void ath9k_ps_wakeup(struct ath_softc *sc)
3017 {
3018 unsigned long flags;
3019
3020 spin_lock_irqsave(&sc->sc_pm_lock, flags);
3021 if (++sc->ps_usecount != 1)
3022 goto unlock;
3023
3024 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
3025
3026 unlock:
3027 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3028 }
3029
3030 void ath9k_ps_restore(struct ath_softc *sc)
3031 {
3032 unsigned long flags;
3033
3034 spin_lock_irqsave(&sc->sc_pm_lock, flags);
3035 if (--sc->ps_usecount != 0)
3036 goto unlock;
3037
3038 if (sc->ps_enabled &&
3039 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
3040 SC_OP_WAIT_FOR_CAB |
3041 SC_OP_WAIT_FOR_PSPOLL_DATA |
3042 SC_OP_WAIT_FOR_TX_ACK)))
3043 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
3044
3045 unlock:
3046 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3047 }
3048
3049 /*
3050 * Helper for ASPM support.
3051 *
3052 * Disable PLL when in L0s as well as receiver clock when in L1.
3053 * This power saving option must be enabled through the SerDes.
3054 *
3055 * Programming the SerDes must go through the same 288 bit serial shift
3056 * register as the other analog registers. Hence the 9 writes.
3057 */
3058 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
3059 {
3060 u8 i;
3061 u32 val;
3062
3063 if (ah->is_pciexpress != true)
3064 return;
3065
3066 /* Do not touch SerDes registers */
3067 if (ah->config.pcie_powersave_enable == 2)
3068 return;
3069
3070 /* Nothing to do on restore for 11N */
3071 if (!restore) {
3072 if (AR_SREV_9280_20_OR_LATER(ah)) {
3073 /*
3074 * AR9280 2.0 or later chips use SerDes values from the
3075 * initvals.h initialized depending on chipset during
3076 * ath9k_hw_init()
3077 */
3078 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3079 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3080 INI_RA(&ah->iniPcieSerdes, i, 1));
3081 }
3082 } else if (AR_SREV_9280(ah) &&
3083 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
3084 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3085 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3086
3087 /* RX shut off when elecidle is asserted */
3088 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3089 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3090 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3091
3092 /* Shut off CLKREQ active in L1 */
3093 if (ah->config.pcie_clock_req)
3094 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3095 else
3096 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3097
3098 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3099 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3100 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3101
3102 /* Load the new settings */
3103 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3104
3105 } else {
3106 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3107 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3108
3109 /* RX shut off when elecidle is asserted */
3110 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3111 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3112 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3113
3114 /*
3115 * Ignore ah->ah_config.pcie_clock_req setting for
3116 * pre-AR9280 11n
3117 */
3118 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3119
3120 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3121 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3122 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3123
3124 /* Load the new settings */
3125 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3126 }
3127
3128 udelay(1000);
3129
3130 /* set bit 19 to allow forcing of pcie core into L1 state */
3131 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3132
3133 /* Several PCIe massages to ensure proper behaviour */
3134 if (ah->config.pcie_waen) {
3135 val = ah->config.pcie_waen;
3136 if (!power_off)
3137 val &= (~AR_WA_D3_L1_DISABLE);
3138 } else {
3139 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3140 AR_SREV_9287(ah)) {
3141 val = AR9285_WA_DEFAULT;
3142 if (!power_off)
3143 val &= (~AR_WA_D3_L1_DISABLE);
3144 } else if (AR_SREV_9280(ah)) {
3145 /*
3146 * On AR9280 chips bit 22 of 0x4004 needs to be
3147 * set otherwise card may disappear.
3148 */
3149 val = AR9280_WA_DEFAULT;
3150 if (!power_off)
3151 val &= (~AR_WA_D3_L1_DISABLE);
3152 } else
3153 val = AR_WA_DEFAULT;
3154 }
3155
3156 REG_WRITE(ah, AR_WA, val);
3157 }
3158
3159 if (power_off) {
3160 /*
3161 * Set PCIe workaround bits
3162 * bit 14 in WA register (disable L1) should only
3163 * be set when device enters D3 and be cleared
3164 * when device comes back to D0.
3165 */
3166 if (ah->config.pcie_waen) {
3167 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3168 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3169 } else {
3170 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3171 AR_SREV_9287(ah)) &&
3172 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3173 (AR_SREV_9280(ah) &&
3174 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3175 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3176 }
3177 }
3178 }
3179 }
3180
3181 /**********************/
3182 /* Interrupt Handling */
3183 /**********************/
3184
3185 bool ath9k_hw_intrpend(struct ath_hw *ah)
3186 {
3187 u32 host_isr;
3188
3189 if (AR_SREV_9100(ah))
3190 return true;
3191
3192 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3193 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3194 return true;
3195
3196 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3197 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3198 && (host_isr != AR_INTR_SPURIOUS))
3199 return true;
3200
3201 return false;
3202 }
3203
3204 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3205 {
3206 u32 isr = 0;
3207 u32 mask2 = 0;
3208 struct ath9k_hw_capabilities *pCap = &ah->caps;
3209 u32 sync_cause = 0;
3210 bool fatal_int = false;
3211
3212 if (!AR_SREV_9100(ah)) {
3213 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3214 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3215 == AR_RTC_STATUS_ON) {
3216 isr = REG_READ(ah, AR_ISR);
3217 }
3218 }
3219
3220 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3221 AR_INTR_SYNC_DEFAULT;
3222
3223 *masked = 0;
3224
3225 if (!isr && !sync_cause)
3226 return false;
3227 } else {
3228 *masked = 0;
3229 isr = REG_READ(ah, AR_ISR);
3230 }
3231
3232 if (isr) {
3233 if (isr & AR_ISR_BCNMISC) {
3234 u32 isr2;
3235 isr2 = REG_READ(ah, AR_ISR_S2);
3236 if (isr2 & AR_ISR_S2_TIM)
3237 mask2 |= ATH9K_INT_TIM;
3238 if (isr2 & AR_ISR_S2_DTIM)
3239 mask2 |= ATH9K_INT_DTIM;
3240 if (isr2 & AR_ISR_S2_DTIMSYNC)
3241 mask2 |= ATH9K_INT_DTIMSYNC;
3242 if (isr2 & (AR_ISR_S2_CABEND))
3243 mask2 |= ATH9K_INT_CABEND;
3244 if (isr2 & AR_ISR_S2_GTT)
3245 mask2 |= ATH9K_INT_GTT;
3246 if (isr2 & AR_ISR_S2_CST)
3247 mask2 |= ATH9K_INT_CST;
3248 if (isr2 & AR_ISR_S2_TSFOOR)
3249 mask2 |= ATH9K_INT_TSFOOR;
3250 }
3251
3252 isr = REG_READ(ah, AR_ISR_RAC);
3253 if (isr == 0xffffffff) {
3254 *masked = 0;
3255 return false;
3256 }
3257
3258 *masked = isr & ATH9K_INT_COMMON;
3259
3260 if (ah->config.intr_mitigation) {
3261 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3262 *masked |= ATH9K_INT_RX;
3263 }
3264
3265 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3266 *masked |= ATH9K_INT_RX;
3267 if (isr &
3268 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3269 AR_ISR_TXEOL)) {
3270 u32 s0_s, s1_s;
3271
3272 *masked |= ATH9K_INT_TX;
3273
3274 s0_s = REG_READ(ah, AR_ISR_S0_S);
3275 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3276 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3277
3278 s1_s = REG_READ(ah, AR_ISR_S1_S);
3279 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3280 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3281 }
3282
3283 if (isr & AR_ISR_RXORN) {
3284 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3285 "receive FIFO overrun interrupt\n");
3286 }
3287
3288 if (!AR_SREV_9100(ah)) {
3289 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3290 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3291 if (isr5 & AR_ISR_S5_TIM_TIMER)
3292 *masked |= ATH9K_INT_TIM_TIMER;
3293 }
3294 }
3295
3296 *masked |= mask2;
3297 }
3298
3299 if (AR_SREV_9100(ah))
3300 return true;
3301
3302 if (isr & AR_ISR_GENTMR) {
3303 u32 s5_s;
3304
3305 s5_s = REG_READ(ah, AR_ISR_S5_S);
3306 if (isr & AR_ISR_GENTMR) {
3307 ah->intr_gen_timer_trigger =
3308 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3309
3310 ah->intr_gen_timer_thresh =
3311 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3312
3313 if (ah->intr_gen_timer_trigger)
3314 *masked |= ATH9K_INT_GENTIMER;
3315
3316 }
3317 }
3318
3319 if (sync_cause) {
3320 fatal_int =
3321 (sync_cause &
3322 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3323 ? true : false;
3324
3325 if (fatal_int) {
3326 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3327 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3328 "received PCI FATAL interrupt\n");
3329 }
3330 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3331 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3332 "received PCI PERR interrupt\n");
3333 }
3334 *masked |= ATH9K_INT_FATAL;
3335 }
3336 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3337 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3338 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3339 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3340 REG_WRITE(ah, AR_RC, 0);
3341 *masked |= ATH9K_INT_FATAL;
3342 }
3343 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3344 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3345 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3346 }
3347
3348 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3349 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3350 }
3351
3352 return true;
3353 }
3354
3355 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3356 {
3357 u32 omask = ah->mask_reg;
3358 u32 mask, mask2;
3359 struct ath9k_hw_capabilities *pCap = &ah->caps;
3360
3361 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3362
3363 if (omask & ATH9K_INT_GLOBAL) {
3364 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3365 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3366 (void) REG_READ(ah, AR_IER);
3367 if (!AR_SREV_9100(ah)) {
3368 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3369 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3370
3371 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3372 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3373 }
3374 }
3375
3376 mask = ints & ATH9K_INT_COMMON;
3377 mask2 = 0;
3378
3379 if (ints & ATH9K_INT_TX) {
3380 if (ah->txok_interrupt_mask)
3381 mask |= AR_IMR_TXOK;
3382 if (ah->txdesc_interrupt_mask)
3383 mask |= AR_IMR_TXDESC;
3384 if (ah->txerr_interrupt_mask)
3385 mask |= AR_IMR_TXERR;
3386 if (ah->txeol_interrupt_mask)
3387 mask |= AR_IMR_TXEOL;
3388 }
3389 if (ints & ATH9K_INT_RX) {
3390 mask |= AR_IMR_RXERR;
3391 if (ah->config.intr_mitigation)
3392 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3393 else
3394 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3395 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3396 mask |= AR_IMR_GENTMR;
3397 }
3398
3399 if (ints & (ATH9K_INT_BMISC)) {
3400 mask |= AR_IMR_BCNMISC;
3401 if (ints & ATH9K_INT_TIM)
3402 mask2 |= AR_IMR_S2_TIM;
3403 if (ints & ATH9K_INT_DTIM)
3404 mask2 |= AR_IMR_S2_DTIM;
3405 if (ints & ATH9K_INT_DTIMSYNC)
3406 mask2 |= AR_IMR_S2_DTIMSYNC;
3407 if (ints & ATH9K_INT_CABEND)
3408 mask2 |= AR_IMR_S2_CABEND;
3409 if (ints & ATH9K_INT_TSFOOR)
3410 mask2 |= AR_IMR_S2_TSFOOR;
3411 }
3412
3413 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3414 mask |= AR_IMR_BCNMISC;
3415 if (ints & ATH9K_INT_GTT)
3416 mask2 |= AR_IMR_S2_GTT;
3417 if (ints & ATH9K_INT_CST)
3418 mask2 |= AR_IMR_S2_CST;
3419 }
3420
3421 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3422 REG_WRITE(ah, AR_IMR, mask);
3423 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3424 AR_IMR_S2_DTIM |
3425 AR_IMR_S2_DTIMSYNC |
3426 AR_IMR_S2_CABEND |
3427 AR_IMR_S2_CABTO |
3428 AR_IMR_S2_TSFOOR |
3429 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3430 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3431 ah->mask_reg = ints;
3432
3433 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3434 if (ints & ATH9K_INT_TIM_TIMER)
3435 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3436 else
3437 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3438 }
3439
3440 if (ints & ATH9K_INT_GLOBAL) {
3441 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3442 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3443 if (!AR_SREV_9100(ah)) {
3444 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3445 AR_INTR_MAC_IRQ);
3446 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3447
3448
3449 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3450 AR_INTR_SYNC_DEFAULT);
3451 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3452 AR_INTR_SYNC_DEFAULT);
3453 }
3454 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3455 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3456 }
3457
3458 return omask;
3459 }
3460
3461 /*******************/
3462 /* Beacon Handling */
3463 /*******************/
3464
3465 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3466 {
3467 int flags = 0;
3468
3469 ah->beacon_interval = beacon_period;
3470
3471 switch (ah->opmode) {
3472 case NL80211_IFTYPE_STATION:
3473 case NL80211_IFTYPE_MONITOR:
3474 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3475 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3476 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3477 flags |= AR_TBTT_TIMER_EN;
3478 break;
3479 case NL80211_IFTYPE_ADHOC:
3480 case NL80211_IFTYPE_MESH_POINT:
3481 REG_SET_BIT(ah, AR_TXCFG,
3482 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3483 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3484 TU_TO_USEC(next_beacon +
3485 (ah->atim_window ? ah->
3486 atim_window : 1)));
3487 flags |= AR_NDP_TIMER_EN;
3488 case NL80211_IFTYPE_AP:
3489 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3490 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3491 TU_TO_USEC(next_beacon -
3492 ah->config.
3493 dma_beacon_response_time));
3494 REG_WRITE(ah, AR_NEXT_SWBA,
3495 TU_TO_USEC(next_beacon -
3496 ah->config.
3497 sw_beacon_response_time));
3498 flags |=
3499 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3500 break;
3501 default:
3502 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3503 "%s: unsupported opmode: %d\n",
3504 __func__, ah->opmode);
3505 return;
3506 break;
3507 }
3508
3509 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3510 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3511 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3512 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3513
3514 beacon_period &= ~ATH9K_BEACON_ENA;
3515 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3516 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3517 ath9k_hw_reset_tsf(ah);
3518 }
3519
3520 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3521 }
3522
3523 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3524 const struct ath9k_beacon_state *bs)
3525 {
3526 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3527 struct ath9k_hw_capabilities *pCap = &ah->caps;
3528
3529 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3530
3531 REG_WRITE(ah, AR_BEACON_PERIOD,
3532 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3533 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3534 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3535
3536 REG_RMW_FIELD(ah, AR_RSSI_THR,
3537 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3538
3539 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3540
3541 if (bs->bs_sleepduration > beaconintval)
3542 beaconintval = bs->bs_sleepduration;
3543
3544 dtimperiod = bs->bs_dtimperiod;
3545 if (bs->bs_sleepduration > dtimperiod)
3546 dtimperiod = bs->bs_sleepduration;
3547
3548 if (beaconintval == dtimperiod)
3549 nextTbtt = bs->bs_nextdtim;
3550 else
3551 nextTbtt = bs->bs_nexttbtt;
3552
3553 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3554 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3555 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3556 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3557
3558 REG_WRITE(ah, AR_NEXT_DTIM,
3559 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3560 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3561
3562 REG_WRITE(ah, AR_SLEEP1,
3563 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3564 | AR_SLEEP1_ASSUME_DTIM);
3565
3566 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3567 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3568 else
3569 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3570
3571 REG_WRITE(ah, AR_SLEEP2,
3572 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3573
3574 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3575 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3576
3577 REG_SET_BIT(ah, AR_TIMER_MODE,
3578 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3579 AR_DTIM_TIMER_EN);
3580
3581 /* TSF Out of Range Threshold */
3582 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3583 }
3584
3585 /*******************/
3586 /* HW Capabilities */
3587 /*******************/
3588
3589 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3590 {
3591 struct ath9k_hw_capabilities *pCap = &ah->caps;
3592 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3593 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
3594
3595 u16 capField = 0, eeval;
3596
3597 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3598 regulatory->current_rd = eeval;
3599
3600 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3601 if (AR_SREV_9285_10_OR_LATER(ah))
3602 eeval |= AR9285_RDEXT_DEFAULT;
3603 regulatory->current_rd_ext = eeval;
3604
3605 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3606
3607 if (ah->opmode != NL80211_IFTYPE_AP &&
3608 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3609 if (regulatory->current_rd == 0x64 ||
3610 regulatory->current_rd == 0x65)
3611 regulatory->current_rd += 5;
3612 else if (regulatory->current_rd == 0x41)
3613 regulatory->current_rd = 0x43;
3614 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3615 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3616 }
3617
3618 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3619 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3620
3621 if (eeval & AR5416_OPFLAGS_11A) {
3622 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3623 if (ah->config.ht_enable) {
3624 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3625 set_bit(ATH9K_MODE_11NA_HT20,
3626 pCap->wireless_modes);
3627 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3628 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3629 pCap->wireless_modes);
3630 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3631 pCap->wireless_modes);
3632 }
3633 }
3634 }
3635
3636 if (eeval & AR5416_OPFLAGS_11G) {
3637 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3638 if (ah->config.ht_enable) {
3639 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3640 set_bit(ATH9K_MODE_11NG_HT20,
3641 pCap->wireless_modes);
3642 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3643 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3644 pCap->wireless_modes);
3645 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3646 pCap->wireless_modes);
3647 }
3648 }
3649 }
3650
3651 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3652 /*
3653 * For AR9271 we will temporarilly uses the rx chainmax as read from
3654 * the EEPROM.
3655 */
3656 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3657 !(eeval & AR5416_OPFLAGS_11A) &&
3658 !(AR_SREV_9271(ah)))
3659 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3660 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3661 else
3662 /* Use rx_chainmask from EEPROM. */
3663 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3664
3665 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3666 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3667
3668 pCap->low_2ghz_chan = 2312;
3669 pCap->high_2ghz_chan = 2732;
3670
3671 pCap->low_5ghz_chan = 4920;
3672 pCap->high_5ghz_chan = 6100;
3673
3674 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3675 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3676 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3677
3678 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3679 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3680 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3681
3682 if (ah->config.ht_enable)
3683 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3684 else
3685 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3686
3687 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3688 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3689 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3690 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3691
3692 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3693 pCap->total_queues =
3694 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3695 else
3696 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3697
3698 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3699 pCap->keycache_size =
3700 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3701 else
3702 pCap->keycache_size = AR_KEYTABLE_SIZE;
3703
3704 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3705
3706 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3707 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3708 else
3709 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3710
3711 if (AR_SREV_9285_10_OR_LATER(ah))
3712 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3713 else if (AR_SREV_9280_10_OR_LATER(ah))
3714 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3715 else
3716 pCap->num_gpio_pins = AR_NUM_GPIO;
3717
3718 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3719 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3720 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3721 } else {
3722 pCap->rts_aggr_limit = (8 * 1024);
3723 }
3724
3725 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3726
3727 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3728 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3729 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3730 ah->rfkill_gpio =
3731 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3732 ah->rfkill_polarity =
3733 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3734
3735 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3736 }
3737 #endif
3738
3739 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3740
3741 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3742 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3743 else
3744 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3745
3746 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3747 pCap->reg_cap =
3748 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3749 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3750 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3751 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3752 } else {
3753 pCap->reg_cap =
3754 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3755 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3756 }
3757
3758 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3759
3760 pCap->num_antcfg_5ghz =
3761 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3762 pCap->num_antcfg_2ghz =
3763 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3764
3765 if (AR_SREV_9280_10_OR_LATER(ah) &&
3766 ath_btcoex_supported(ah->hw_version.subsysid)) {
3767 btcoex_info->btactive_gpio = ATH_BTACTIVE_GPIO;
3768 btcoex_info->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3769
3770 if (AR_SREV_9285(ah)) {
3771 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_3WIRE;
3772 btcoex_info->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3773 } else {
3774 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_2WIRE;
3775 }
3776 } else {
3777 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_NONE;
3778 }
3779 }
3780
3781 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3782 u32 capability, u32 *result)
3783 {
3784 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3785 switch (type) {
3786 case ATH9K_CAP_CIPHER:
3787 switch (capability) {
3788 case ATH9K_CIPHER_AES_CCM:
3789 case ATH9K_CIPHER_AES_OCB:
3790 case ATH9K_CIPHER_TKIP:
3791 case ATH9K_CIPHER_WEP:
3792 case ATH9K_CIPHER_MIC:
3793 case ATH9K_CIPHER_CLR:
3794 return true;
3795 default:
3796 return false;
3797 }
3798 case ATH9K_CAP_TKIP_MIC:
3799 switch (capability) {
3800 case 0:
3801 return true;
3802 case 1:
3803 return (ah->sta_id1_defaults &
3804 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3805 false;
3806 }
3807 case ATH9K_CAP_TKIP_SPLIT:
3808 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3809 false : true;
3810 case ATH9K_CAP_DIVERSITY:
3811 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3812 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3813 true : false;
3814 case ATH9K_CAP_MCAST_KEYSRCH:
3815 switch (capability) {
3816 case 0:
3817 return true;
3818 case 1:
3819 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3820 return false;
3821 } else {
3822 return (ah->sta_id1_defaults &
3823 AR_STA_ID1_MCAST_KSRCH) ? true :
3824 false;
3825 }
3826 }
3827 return false;
3828 case ATH9K_CAP_TXPOW:
3829 switch (capability) {
3830 case 0:
3831 return 0;
3832 case 1:
3833 *result = regulatory->power_limit;
3834 return 0;
3835 case 2:
3836 *result = regulatory->max_power_level;
3837 return 0;
3838 case 3:
3839 *result = regulatory->tp_scale;
3840 return 0;
3841 }
3842 return false;
3843 case ATH9K_CAP_DS:
3844 return (AR_SREV_9280_20_OR_LATER(ah) &&
3845 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3846 ? false : true;
3847 default:
3848 return false;
3849 }
3850 }
3851
3852 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3853 u32 capability, u32 setting, int *status)
3854 {
3855 u32 v;
3856
3857 switch (type) {
3858 case ATH9K_CAP_TKIP_MIC:
3859 if (setting)
3860 ah->sta_id1_defaults |=
3861 AR_STA_ID1_CRPT_MIC_ENABLE;
3862 else
3863 ah->sta_id1_defaults &=
3864 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3865 return true;
3866 case ATH9K_CAP_DIVERSITY:
3867 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3868 if (setting)
3869 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3870 else
3871 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3872 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3873 return true;
3874 case ATH9K_CAP_MCAST_KEYSRCH:
3875 if (setting)
3876 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3877 else
3878 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3879 return true;
3880 default:
3881 return false;
3882 }
3883 }
3884
3885 /****************************/
3886 /* GPIO / RFKILL / Antennae */
3887 /****************************/
3888
3889 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3890 u32 gpio, u32 type)
3891 {
3892 int addr;
3893 u32 gpio_shift, tmp;
3894
3895 if (gpio > 11)
3896 addr = AR_GPIO_OUTPUT_MUX3;
3897 else if (gpio > 5)
3898 addr = AR_GPIO_OUTPUT_MUX2;
3899 else
3900 addr = AR_GPIO_OUTPUT_MUX1;
3901
3902 gpio_shift = (gpio % 6) * 5;
3903
3904 if (AR_SREV_9280_20_OR_LATER(ah)
3905 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3906 REG_RMW(ah, addr, (type << gpio_shift),
3907 (0x1f << gpio_shift));
3908 } else {
3909 tmp = REG_READ(ah, addr);
3910 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3911 tmp &= ~(0x1f << gpio_shift);
3912 tmp |= (type << gpio_shift);
3913 REG_WRITE(ah, addr, tmp);
3914 }
3915 }
3916
3917 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3918 {
3919 u32 gpio_shift;
3920
3921 ASSERT(gpio < ah->caps.num_gpio_pins);
3922
3923 gpio_shift = gpio << 1;
3924
3925 REG_RMW(ah,
3926 AR_GPIO_OE_OUT,
3927 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3928 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3929 }
3930
3931 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3932 {
3933 #define MS_REG_READ(x, y) \
3934 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3935
3936 if (gpio >= ah->caps.num_gpio_pins)
3937 return 0xffffffff;
3938
3939 if (AR_SREV_9287_10_OR_LATER(ah))
3940 return MS_REG_READ(AR9287, gpio) != 0;
3941 else if (AR_SREV_9285_10_OR_LATER(ah))
3942 return MS_REG_READ(AR9285, gpio) != 0;
3943 else if (AR_SREV_9280_10_OR_LATER(ah))
3944 return MS_REG_READ(AR928X, gpio) != 0;
3945 else
3946 return MS_REG_READ(AR, gpio) != 0;
3947 }
3948
3949 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3950 u32 ah_signal_type)
3951 {
3952 u32 gpio_shift;
3953
3954 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3955
3956 gpio_shift = 2 * gpio;
3957
3958 REG_RMW(ah,
3959 AR_GPIO_OE_OUT,
3960 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3961 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3962 }
3963
3964 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3965 {
3966 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3967 AR_GPIO_BIT(gpio));
3968 }
3969
3970 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3971 {
3972 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3973 }
3974
3975 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3976 {
3977 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3978 }
3979
3980 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3981 enum ath9k_ant_setting settings,
3982 struct ath9k_channel *chan,
3983 u8 *tx_chainmask,
3984 u8 *rx_chainmask,
3985 u8 *antenna_cfgd)
3986 {
3987 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3988
3989 if (AR_SREV_9280(ah)) {
3990 if (!tx_chainmask_cfg) {
3991
3992 tx_chainmask_cfg = *tx_chainmask;
3993 rx_chainmask_cfg = *rx_chainmask;
3994 }
3995
3996 switch (settings) {
3997 case ATH9K_ANT_FIXED_A:
3998 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3999 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
4000 *antenna_cfgd = true;
4001 break;
4002 case ATH9K_ANT_FIXED_B:
4003 if (ah->caps.tx_chainmask >
4004 ATH9K_ANTENNA1_CHAINMASK) {
4005 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
4006 }
4007 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
4008 *antenna_cfgd = true;
4009 break;
4010 case ATH9K_ANT_VARIABLE:
4011 *tx_chainmask = tx_chainmask_cfg;
4012 *rx_chainmask = rx_chainmask_cfg;
4013 *antenna_cfgd = true;
4014 break;
4015 default:
4016 break;
4017 }
4018 } else {
4019 ah->config.diversity_control = settings;
4020 }
4021
4022 return true;
4023 }
4024
4025 /*********************/
4026 /* General Operation */
4027 /*********************/
4028
4029 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
4030 {
4031 u32 bits = REG_READ(ah, AR_RX_FILTER);
4032 u32 phybits = REG_READ(ah, AR_PHY_ERR);
4033
4034 if (phybits & AR_PHY_ERR_RADAR)
4035 bits |= ATH9K_RX_FILTER_PHYRADAR;
4036 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
4037 bits |= ATH9K_RX_FILTER_PHYERR;
4038
4039 return bits;
4040 }
4041
4042 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
4043 {
4044 u32 phybits;
4045
4046 REG_WRITE(ah, AR_RX_FILTER, bits);
4047
4048 phybits = 0;
4049 if (bits & ATH9K_RX_FILTER_PHYRADAR)
4050 phybits |= AR_PHY_ERR_RADAR;
4051 if (bits & ATH9K_RX_FILTER_PHYERR)
4052 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
4053 REG_WRITE(ah, AR_PHY_ERR, phybits);
4054
4055 if (phybits)
4056 REG_WRITE(ah, AR_RXCFG,
4057 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
4058 else
4059 REG_WRITE(ah, AR_RXCFG,
4060 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
4061 }
4062
4063 bool ath9k_hw_phy_disable(struct ath_hw *ah)
4064 {
4065 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
4066 }
4067
4068 bool ath9k_hw_disable(struct ath_hw *ah)
4069 {
4070 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
4071 return false;
4072
4073 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
4074 }
4075
4076 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
4077 {
4078 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4079 struct ath9k_channel *chan = ah->curchan;
4080 struct ieee80211_channel *channel = chan->chan;
4081
4082 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
4083
4084 ah->eep_ops->set_txpower(ah, chan,
4085 ath9k_regd_get_ctl(regulatory, chan),
4086 channel->max_antenna_gain * 2,
4087 channel->max_power * 2,
4088 min((u32) MAX_RATE_POWER,
4089 (u32) regulatory->power_limit));
4090 }
4091
4092 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
4093 {
4094 memcpy(ah->macaddr, mac, ETH_ALEN);
4095 }
4096
4097 void ath9k_hw_setopmode(struct ath_hw *ah)
4098 {
4099 ath9k_hw_set_operating_mode(ah, ah->opmode);
4100 }
4101
4102 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4103 {
4104 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4105 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4106 }
4107
4108 void ath9k_hw_setbssidmask(struct ath_softc *sc)
4109 {
4110 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
4111 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
4112 }
4113
4114 void ath9k_hw_write_associd(struct ath_softc *sc)
4115 {
4116 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
4117 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
4118 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4119 }
4120
4121 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4122 {
4123 u64 tsf;
4124
4125 tsf = REG_READ(ah, AR_TSF_U32);
4126 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4127
4128 return tsf;
4129 }
4130
4131 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4132 {
4133 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4134 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4135 }
4136
4137 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4138 {
4139 ath9k_ps_wakeup(ah->ah_sc);
4140 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4141 AH_TSF_WRITE_TIMEOUT))
4142 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
4143 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4144
4145 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4146 ath9k_ps_restore(ah->ah_sc);
4147 }
4148
4149 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4150 {
4151 if (setting)
4152 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4153 else
4154 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4155 }
4156
4157 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4158 {
4159 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4160 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
4161 ah->slottime = (u32) -1;
4162 return false;
4163 } else {
4164 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4165 ah->slottime = us;
4166 return true;
4167 }
4168 }
4169
4170 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
4171 {
4172 u32 macmode;
4173
4174 if (mode == ATH9K_HT_MACMODE_2040 &&
4175 !ah->config.cwm_ignore_extcca)
4176 macmode = AR_2040_JOINED_RX_CLEAR;
4177 else
4178 macmode = 0;
4179
4180 REG_WRITE(ah, AR_2040_MODE, macmode);
4181 }
4182
4183 /* HW Generic timers configuration */
4184
4185 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4186 {
4187 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4188 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4189 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4190 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4191 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4192 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4193 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4194 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4195 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4196 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4197 AR_NDP2_TIMER_MODE, 0x0002},
4198 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4199 AR_NDP2_TIMER_MODE, 0x0004},
4200 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4201 AR_NDP2_TIMER_MODE, 0x0008},
4202 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4203 AR_NDP2_TIMER_MODE, 0x0010},
4204 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4205 AR_NDP2_TIMER_MODE, 0x0020},
4206 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4207 AR_NDP2_TIMER_MODE, 0x0040},
4208 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4209 AR_NDP2_TIMER_MODE, 0x0080}
4210 };
4211
4212 /* HW generic timer primitives */
4213
4214 /* compute and clear index of rightmost 1 */
4215 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4216 {
4217 u32 b;
4218
4219 b = *mask;
4220 b &= (0-b);
4221 *mask &= ~b;
4222 b *= debruijn32;
4223 b >>= 27;
4224
4225 return timer_table->gen_timer_index[b];
4226 }
4227
4228 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4229 {
4230 return REG_READ(ah, AR_TSF_L32);
4231 }
4232
4233 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4234 void (*trigger)(void *),
4235 void (*overflow)(void *),
4236 void *arg,
4237 u8 timer_index)
4238 {
4239 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4240 struct ath_gen_timer *timer;
4241
4242 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4243
4244 if (timer == NULL) {
4245 printk(KERN_DEBUG "Failed to allocate memory"
4246 "for hw timer[%d]\n", timer_index);
4247 return NULL;
4248 }
4249
4250 /* allocate a hardware generic timer slot */
4251 timer_table->timers[timer_index] = timer;
4252 timer->index = timer_index;
4253 timer->trigger = trigger;
4254 timer->overflow = overflow;
4255 timer->arg = arg;
4256
4257 return timer;
4258 }
4259
4260 void ath_gen_timer_start(struct ath_hw *ah,
4261 struct ath_gen_timer *timer,
4262 u32 timer_next, u32 timer_period)
4263 {
4264 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4265 u32 tsf;
4266
4267 BUG_ON(!timer_period);
4268
4269 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4270
4271 tsf = ath9k_hw_gettsf32(ah);
4272
4273 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, "curent tsf %x period %x"
4274 "timer_next %x\n", tsf, timer_period, timer_next);
4275
4276 /*
4277 * Pull timer_next forward if the current TSF already passed it
4278 * because of software latency
4279 */
4280 if (timer_next < tsf)
4281 timer_next = tsf + timer_period;
4282
4283 /*
4284 * Program generic timer registers
4285 */
4286 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4287 timer_next);
4288 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4289 timer_period);
4290 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4291 gen_tmr_configuration[timer->index].mode_mask);
4292
4293 /* Enable both trigger and thresh interrupt masks */
4294 REG_SET_BIT(ah, AR_IMR_S5,
4295 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4296 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4297
4298 if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
4299 ath9k_hw_set_interrupts(ah, 0);
4300 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
4301 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4302 }
4303 }
4304
4305 void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4306 {
4307 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4308
4309 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4310 (timer->index >= ATH_MAX_GEN_TIMER)) {
4311 return;
4312 }
4313
4314 /* Clear generic timer enable bits. */
4315 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4316 gen_tmr_configuration[timer->index].mode_mask);
4317
4318 /* Disable both trigger and thresh interrupt masks */
4319 REG_CLR_BIT(ah, AR_IMR_S5,
4320 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4321 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4322
4323 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4324
4325 /* if no timer is enabled, turn off interrupt mask */
4326 if (timer_table->timer_mask.val == 0) {
4327 ath9k_hw_set_interrupts(ah, 0);
4328 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
4329 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4330 }
4331 }
4332
4333 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4334 {
4335 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4336
4337 /* free the hardware generic timer slot */
4338 timer_table->timers[timer->index] = NULL;
4339 kfree(timer);
4340 }
4341
4342 /*
4343 * Generic Timer Interrupts handling
4344 */
4345 void ath_gen_timer_isr(struct ath_hw *ah)
4346 {
4347 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4348 struct ath_gen_timer *timer;
4349 u32 trigger_mask, thresh_mask, index;
4350
4351 /* get hardware generic timer interrupt status */
4352 trigger_mask = ah->intr_gen_timer_trigger;
4353 thresh_mask = ah->intr_gen_timer_thresh;
4354 trigger_mask &= timer_table->timer_mask.val;
4355 thresh_mask &= timer_table->timer_mask.val;
4356
4357 trigger_mask &= ~thresh_mask;
4358
4359 while (thresh_mask) {
4360 index = rightmost_index(timer_table, &thresh_mask);
4361 timer = timer_table->timers[index];
4362 BUG_ON(!timer);
4363 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
4364 "TSF overflow for Gen timer %d\n", index);
4365 timer->overflow(timer->arg);
4366 }
4367
4368 while (trigger_mask) {
4369 index = rightmost_index(timer_table, &trigger_mask);
4370 timer = timer_table->timers[index];
4371 BUG_ON(!timer);
4372 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
4373 "Gen timer[%d] trigger\n", index);
4374 timer->trigger(timer->arg);
4375 }
4376 }
4377
4378 /*
4379 * Primitive to disable ASPM
4380 */
4381 void ath_pcie_aspm_disable(struct ath_softc *sc)
4382 {
4383 struct pci_dev *pdev = to_pci_dev(sc->dev);
4384 u8 aspm;
4385
4386 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
4387 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
4388 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
4389 }
Linux MOXA ART SoC ARM port