drivers/net/wireless/ath/ath9k/pci.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include <linux/pci.h>
  19 #include "ath9k.h"
  20
  21 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  22         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  23         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  24         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  25         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  26         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  27         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  28         { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
  29         { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
  30         { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
  31         { 0 }
  32 };
  33
  34 /* return bus cachesize in 4B word units */
  35 static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
  36 {
  37         u8 u8tmp;
  38
  39         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
  40         *csz = (int)u8tmp;
  41
  42         /*
  43          * This check was put in to avoid "unplesant" consequences if
  44          * the bootrom has not fully initialized all PCI devices.
  45          * Sometimes the cache line size register is not set
  46          */
  47
  48         if (*csz == 0)
  49                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  50 }
  51
  52 static void ath_pci_cleanup(struct ath_softc *sc)
  53 {
  54         struct pci_dev *pdev = to_pci_dev(sc->dev);
  55
  56         pci_iounmap(pdev, sc->mem);
  57         pci_disable_device(pdev);
  58         pci_release_region(pdev, 0);
  59 }
  60
  61 static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
  62 {
  63         (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  64
  65         if (!ath9k_hw_wait(ah,
  66                            AR_EEPROM_STATUS_DATA,
  67                            AR_EEPROM_STATUS_DATA_BUSY |
  68                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  69                            AH_WAIT_TIMEOUT)) {
  70                 return false;
  71         }
  72
  73         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  74                    AR_EEPROM_STATUS_DATA_VAL);
  75
  76         return true;
  77 }
  78
  79 static struct ath_bus_ops ath_pci_bus_ops = {
  80         .read_cachesize = ath_pci_read_cachesize,
  81         .cleanup = ath_pci_cleanup,
  82         .eeprom_read = ath_pci_eeprom_read,
  83 };
  84
  85 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  86 {
  87         void __iomem *mem;
  88         struct ath_wiphy *aphy;
  89         struct ath_softc *sc;
  90         struct ieee80211_hw *hw;
  91         u8 csz;
  92         u16 subsysid;
  93         u32 val;
  94         int ret = 0;
  95         struct ath_hw *ah;
  96
  97         if (pci_enable_device(pdev))
  98                 return -EIO;
  99
 100         ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 101
 102         if (ret) {
 103                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
 104                 goto bad;
 105         }
 106
 107         ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 108
 109         if (ret) {
 110                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
 111                         "DMA enable failed\n");
 112                 goto bad;
 113         }
 114
 115         /*
 116          * Cache line size is used to size and align various
 117          * structures used to communicate with the hardware.
 118          */
 119         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 120         if (csz == 0) {
 121                 /*
 122                  * Linux 2.4.18 (at least) writes the cache line size
 123                  * register as a 16-bit wide register which is wrong.
 124                  * We must have this setup properly for rx buffer
 125                  * DMA to work so force a reasonable value here if it
 126                  * comes up zero.
 127                  */
 128                 csz = L1_CACHE_BYTES / sizeof(u32);
 129                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 130         }
 131         /*
 132          * The default setting of latency timer yields poor results,
 133          * set it to the value used by other systems. It may be worth
 134          * tweaking this setting more.
 135          */
 136         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 137
 138         pci_set_master(pdev);
 139
 140         /*
 141          * Disable the RETRY_TIMEOUT register (0x41) to keep
 142          * PCI Tx retries from interfering with C3 CPU state.
 143          */
 144         pci_read_config_dword(pdev, 0x40, &val);
 145         if ((val & 0x0000ff00) != 0)
 146                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 147
 148         ret = pci_request_region(pdev, 0, "ath9k");
 149         if (ret) {
 150                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
 151                 ret = -ENODEV;
 152                 goto bad;
 153         }
 154
 155         mem = pci_iomap(pdev, 0, 0);
 156         if (!mem) {
 157                 printk(KERN_ERR "PCI memory map error\n") ;
 158                 ret = -EIO;
 159                 goto bad1;
 160         }
 161
 162         hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
 163                                 sizeof(struct ath_softc), &ath9k_ops);
 164         if (!hw) {
 165                 dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
 166                 ret = -ENOMEM;
 167                 goto bad2;
 168         }
 169
 170         SET_IEEE80211_DEV(hw, &pdev->dev);
 171         pci_set_drvdata(pdev, hw);
 172
 173         aphy = hw->priv;
 174         sc = (struct ath_softc *) (aphy + 1);
 175         aphy->sc = sc;
 176         aphy->hw = hw;
 177         sc->pri_wiphy = aphy;
 178         sc->hw = hw;
 179         sc->dev = &pdev->dev;
 180         sc->mem = mem;
 181         sc->bus_ops = &ath_pci_bus_ops;
 182
 183         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
 184         ret = ath_init_device(id->device, sc, subsysid);
 185         if (ret) {
 186                 dev_err(&pdev->dev, "failed to initialize device\n");
 187                 goto bad3;
 188         }
 189
 190         /* setup interrupt service routine */
 191
 192         ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
 193         if (ret) {
 194                 dev_err(&pdev->dev, "request_irq failed\n");
 195                 goto bad4;
 196         }
 197
 198         sc->irq = pdev->irq;
 199
 200         ah = sc->sc_ah;
 201         printk(KERN_INFO
 202                "%s: Atheros AR%s MAC/BB Rev:%x "
 203                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
 204                wiphy_name(hw->wiphy),
 205                ath_mac_bb_name(ah->hw_version.macVersion),
 206                ah->hw_version.macRev,
 207                ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
 208                ah->hw_version.phyRev,
 209                (unsigned long)mem, pdev->irq);
 210
 211         return 0;
 212 bad4:
 213         ath_detach(sc);
 214 bad3:
 215         ieee80211_free_hw(hw);
 216 bad2:
 217         pci_iounmap(pdev, mem);
 218 bad1:
 219         pci_release_region(pdev, 0);
 220 bad:
 221         pci_disable_device(pdev);
 222         return ret;
 223 }
 224
 225 static void ath_pci_remove(struct pci_dev *pdev)
 226 {
 227         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 228         struct ath_wiphy *aphy = hw->priv;
 229         struct ath_softc *sc = aphy->sc;
 230
 231         ath_cleanup(sc);
 232 }
 233
 234 #ifdef CONFIG_PM
 235
 236 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 237 {
 238         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 239         struct ath_wiphy *aphy = hw->priv;
 240         struct ath_softc *sc = aphy->sc;
 241
 242         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 243
 244         pci_save_state(pdev);
 245         pci_disable_device(pdev);
 246         pci_set_power_state(pdev, PCI_D3hot);
 247
 248         return 0;
 249 }
 250
 251 static int ath_pci_resume(struct pci_dev *pdev)
 252 {
 253         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 254         struct ath_wiphy *aphy = hw->priv;
 255         struct ath_softc *sc = aphy->sc;
 256         u32 val;
 257         int err;
 258
 259         pci_restore_state(pdev);
 260
 261         err = pci_enable_device(pdev);
 262         if (err)
 263                 return err;
 264
 265         /*
 266          * Suspend/Resume resets the PCI configuration space, so we have to
 267          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 268          * PCI Tx retries from interfering with C3 CPU state
 269          */
 270         pci_read_config_dword(pdev, 0x40, &val);
 271         if ((val & 0x0000ff00) != 0)
 272                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 273
 274         /* Enable LED */
 275         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
 276                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 277         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 278
 279         return 0;
 280 }
 281
 282 #endif /* CONFIG_PM */
 283
 284 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 285
 286 static struct pci_driver ath_pci_driver = {
 287         .name       = "ath9k",
 288         .id_table   = ath_pci_id_table,
 289         .probe      = ath_pci_probe,
 290         .remove     = ath_pci_remove,
 291 #ifdef CONFIG_PM
 292         .suspend    = ath_pci_suspend,
 293         .resume     = ath_pci_resume,
 294 #endif /* CONFIG_PM */
 295 };
 296
 297 int ath_pci_init(void)
 298 {
 299         return pci_register_driver(&ath_pci_driver);
 300 }
 301
 302 void ath_pci_exit(void)
 303 {
 304         pci_unregister_driver(&ath_pci_driver);
 305 }