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init from v2.6.32.60
[mach-moxart.git] / drivers / net / wireless / p54 / p54pci.c
blobd21fb27ca1f940fdeda83e03f33532829db5b79a
1
2 /*
3 * Linux device driver for PCI based Prism54
4 *
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
7 *
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <linux/init.h>
17 #include <linux/pci.h>
18 #include <linux/firmware.h>
19 #include <linux/etherdevice.h>
20 #include <linux/delay.h>
21 #include <linux/completion.h>
22 #include <net/mac80211.h>
23
24 #include "p54.h"
25 #include "lmac.h"
26 #include "p54pci.h"
27
28 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
30 MODULE_LICENSE("GPL");
31 MODULE_ALIAS("prism54pci");
32 MODULE_FIRMWARE("isl3886pci");
33
34 static struct pci_device_id p54p_table[] __devinitdata = {
35 /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
36 { PCI_DEVICE(0x1260, 0x3890) },
37 /* 3COM 3CRWE154G72 Wireless LAN adapter */
38 { PCI_DEVICE(0x10b7, 0x6001) },
39 /* Intersil PRISM Indigo Wireless LAN adapter */
40 { PCI_DEVICE(0x1260, 0x3877) },
41 /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
42 { PCI_DEVICE(0x1260, 0x3886) },
43 /* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
44 { PCI_DEVICE(0x1260, 0xffff) },
45 { },
46 };
47
48 MODULE_DEVICE_TABLE(pci, p54p_table);
49
50 static int p54p_upload_firmware(struct ieee80211_hw *dev)
51 {
52 struct p54p_priv *priv = dev->priv;
53 __le32 reg;
54 int err;
55 __le32 *data;
56 u32 remains, left, device_addr;
57
58 P54P_WRITE(int_enable, cpu_to_le32(0));
59 P54P_READ(int_enable);
60 udelay(10);
61
62 reg = P54P_READ(ctrl_stat);
63 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
64 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
65 P54P_WRITE(ctrl_stat, reg);
66 P54P_READ(ctrl_stat);
67 udelay(10);
68
69 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
70 P54P_WRITE(ctrl_stat, reg);
71 wmb();
72 udelay(10);
73
74 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
75 P54P_WRITE(ctrl_stat, reg);
76 wmb();
77
78 /* wait for the firmware to reset properly */
79 mdelay(10);
80
81 err = p54_parse_firmware(dev, priv->firmware);
82 if (err)
83 return err;
84
85 if (priv->common.fw_interface != FW_LM86) {
86 dev_err(&priv->pdev->dev, "wrong firmware, "
87 "please get a LM86(PCI) firmware a try again.\n");
88 return -EINVAL;
89 }
90
91 data = (__le32 *) priv->firmware->data;
92 remains = priv->firmware->size;
93 device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
94 while (remains) {
95 u32 i = 0;
96 left = min((u32)0x1000, remains);
97 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
98 P54P_READ(int_enable);
99
100 device_addr += 0x1000;
101 while (i < left) {
102 P54P_WRITE(direct_mem_win[i], *data++);
103 i += sizeof(u32);
104 }
105
106 remains -= left;
107 P54P_READ(int_enable);
108 }
109
110 reg = P54P_READ(ctrl_stat);
111 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
112 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
113 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
114 P54P_WRITE(ctrl_stat, reg);
115 P54P_READ(ctrl_stat);
116 udelay(10);
117
118 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
119 P54P_WRITE(ctrl_stat, reg);
120 wmb();
121 udelay(10);
122
123 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
124 P54P_WRITE(ctrl_stat, reg);
125 wmb();
126 udelay(10);
127
128 /* wait for the firmware to boot properly */
129 mdelay(100);
130
131 return 0;
132 }
133
134 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
135 int ring_index, struct p54p_desc *ring, u32 ring_limit,
136 struct sk_buff **rx_buf)
137 {
138 struct p54p_priv *priv = dev->priv;
139 struct p54p_ring_control *ring_control = priv->ring_control;
140 u32 limit, idx, i;
141
142 idx = le32_to_cpu(ring_control->host_idx[ring_index]);
143 limit = idx;
144 limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
145 limit = ring_limit - limit;
146
147 i = idx % ring_limit;
148 while (limit-- > 1) {
149 struct p54p_desc *desc = &ring[i];
150
151 if (!desc->host_addr) {
152 struct sk_buff *skb;
153 dma_addr_t mapping;
154 skb = dev_alloc_skb(priv->common.rx_mtu + 32);
155 if (!skb)
156 break;
157
158 mapping = pci_map_single(priv->pdev,
159 skb_tail_pointer(skb),
160 priv->common.rx_mtu + 32,
161 PCI_DMA_FROMDEVICE);
162
163 if (pci_dma_mapping_error(priv->pdev, mapping)) {
164 dev_kfree_skb_any(skb);
165 dev_err(&priv->pdev->dev,
166 "RX DMA Mapping error\n");
167 break;
168 }
169
170 desc->host_addr = cpu_to_le32(mapping);
171 desc->device_addr = 0; // FIXME: necessary?
172 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
173 desc->flags = 0;
174 rx_buf[i] = skb;
175 }
176
177 i++;
178 idx++;
179 i %= ring_limit;
180 }
181
182 wmb();
183 ring_control->host_idx[ring_index] = cpu_to_le32(idx);
184 }
185
186 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
187 int ring_index, struct p54p_desc *ring, u32 ring_limit,
188 struct sk_buff **rx_buf)
189 {
190 struct p54p_priv *priv = dev->priv;
191 struct p54p_ring_control *ring_control = priv->ring_control;
192 struct p54p_desc *desc;
193 u32 idx, i;
194
195 i = (*index) % ring_limit;
196 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
197 idx %= ring_limit;
198 while (i != idx) {
199 u16 len;
200 struct sk_buff *skb;
201 dma_addr_t dma_addr;
202 desc = &ring[i];
203 len = le16_to_cpu(desc->len);
204 skb = rx_buf[i];
205
206 if (!skb) {
207 i++;
208 i %= ring_limit;
209 continue;
210 }
211
212 if (unlikely(len > priv->common.rx_mtu)) {
213 if (net_ratelimit())
214 dev_err(&priv->pdev->dev, "rx'd frame size "
215 "exceeds length threshold.\n");
216
217 len = priv->common.rx_mtu;
218 }
219 dma_addr = le32_to_cpu(desc->host_addr);
220 pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
221 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
222 skb_put(skb, len);
223
224 if (p54_rx(dev, skb)) {
225 pci_unmap_single(priv->pdev, dma_addr,
226 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
227 rx_buf[i] = NULL;
228 desc->host_addr = cpu_to_le32(0);
229 } else {
230 skb_trim(skb, 0);
231 pci_dma_sync_single_for_device(priv->pdev, dma_addr,
232 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
233 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
234 }
235
236 i++;
237 i %= ring_limit;
238 }
239
240 p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
241 }
242
243 /* caller must hold priv->lock */
244 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
245 int ring_index, struct p54p_desc *ring, u32 ring_limit,
246 void **tx_buf)
247 {
248 struct p54p_priv *priv = dev->priv;
249 struct p54p_ring_control *ring_control = priv->ring_control;
250 struct p54p_desc *desc;
251 u32 idx, i;
252
253 i = (*index) % ring_limit;
254 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
255 idx %= ring_limit;
256
257 while (i != idx) {
258 desc = &ring[i];
259 if (tx_buf[i])
260 if (FREE_AFTER_TX((struct sk_buff *) tx_buf[i]))
261 p54_free_skb(dev, tx_buf[i]);
262 tx_buf[i] = NULL;
263
264 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
265 le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
266
267 desc->host_addr = 0;
268 desc->device_addr = 0;
269 desc->len = 0;
270 desc->flags = 0;
271
272 i++;
273 i %= ring_limit;
274 }
275 }
276
277 static void p54p_rx_tasklet(unsigned long dev_id)
278 {
279 struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
280 struct p54p_priv *priv = dev->priv;
281 struct p54p_ring_control *ring_control = priv->ring_control;
282
283 p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
284 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
285
286 p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
287 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
288
289 wmb();
290 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
291 }
292
293 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
294 {
295 struct ieee80211_hw *dev = dev_id;
296 struct p54p_priv *priv = dev->priv;
297 struct p54p_ring_control *ring_control = priv->ring_control;
298 __le32 reg;
299
300 spin_lock(&priv->lock);
301 reg = P54P_READ(int_ident);
302 if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
303 spin_unlock(&priv->lock);
304 return IRQ_HANDLED;
305 }
306
307 P54P_WRITE(int_ack, reg);
308
309 reg &= P54P_READ(int_enable);
310
311 if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
312 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
313 3, ring_control->tx_mgmt,
314 ARRAY_SIZE(ring_control->tx_mgmt),
315 priv->tx_buf_mgmt);
316
317 p54p_check_tx_ring(dev, &priv->tx_idx_data,
318 1, ring_control->tx_data,
319 ARRAY_SIZE(ring_control->tx_data),
320 priv->tx_buf_data);
321
322 tasklet_schedule(&priv->rx_tasklet);
323
324 } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
325 complete(&priv->boot_comp);
326
327 spin_unlock(&priv->lock);
328
329 return reg ? IRQ_HANDLED : IRQ_NONE;
330 }
331
332 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
333 {
334 struct p54p_priv *priv = dev->priv;
335 struct p54p_ring_control *ring_control = priv->ring_control;
336 unsigned long flags;
337 struct p54p_desc *desc;
338 dma_addr_t mapping;
339 u32 device_idx, idx, i;
340
341 spin_lock_irqsave(&priv->lock, flags);
342 device_idx = le32_to_cpu(ring_control->device_idx[1]);
343 idx = le32_to_cpu(ring_control->host_idx[1]);
344 i = idx % ARRAY_SIZE(ring_control->tx_data);
345
346 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
347 PCI_DMA_TODEVICE);
348 if (pci_dma_mapping_error(priv->pdev, mapping)) {
349 spin_unlock_irqrestore(&priv->lock, flags);
350 p54_free_skb(dev, skb);
351 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
352 return ;
353 }
354 priv->tx_buf_data[i] = skb;
355
356 desc = &ring_control->tx_data[i];
357 desc->host_addr = cpu_to_le32(mapping);
358 desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
359 desc->len = cpu_to_le16(skb->len);
360 desc->flags = 0;
361
362 wmb();
363 ring_control->host_idx[1] = cpu_to_le32(idx + 1);
364 spin_unlock_irqrestore(&priv->lock, flags);
365
366 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
367 P54P_READ(dev_int);
368 }
369
370 static void p54p_stop(struct ieee80211_hw *dev)
371 {
372 struct p54p_priv *priv = dev->priv;
373 struct p54p_ring_control *ring_control = priv->ring_control;
374 unsigned int i;
375 struct p54p_desc *desc;
376
377 tasklet_kill(&priv->rx_tasklet);
378
379 P54P_WRITE(int_enable, cpu_to_le32(0));
380 P54P_READ(int_enable);
381 udelay(10);
382
383 free_irq(priv->pdev->irq, dev);
384
385 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
386
387 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
388 desc = &ring_control->rx_data[i];
389 if (desc->host_addr)
390 pci_unmap_single(priv->pdev,
391 le32_to_cpu(desc->host_addr),
392 priv->common.rx_mtu + 32,
393 PCI_DMA_FROMDEVICE);
394 kfree_skb(priv->rx_buf_data[i]);
395 priv->rx_buf_data[i] = NULL;
396 }
397
398 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
399 desc = &ring_control->rx_mgmt[i];
400 if (desc->host_addr)
401 pci_unmap_single(priv->pdev,
402 le32_to_cpu(desc->host_addr),
403 priv->common.rx_mtu + 32,
404 PCI_DMA_FROMDEVICE);
405 kfree_skb(priv->rx_buf_mgmt[i]);
406 priv->rx_buf_mgmt[i] = NULL;
407 }
408
409 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
410 desc = &ring_control->tx_data[i];
411 if (desc->host_addr)
412 pci_unmap_single(priv->pdev,
413 le32_to_cpu(desc->host_addr),
414 le16_to_cpu(desc->len),
415 PCI_DMA_TODEVICE);
416
417 p54_free_skb(dev, priv->tx_buf_data[i]);
418 priv->tx_buf_data[i] = NULL;
419 }
420
421 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
422 desc = &ring_control->tx_mgmt[i];
423 if (desc->host_addr)
424 pci_unmap_single(priv->pdev,
425 le32_to_cpu(desc->host_addr),
426 le16_to_cpu(desc->len),
427 PCI_DMA_TODEVICE);
428
429 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
430 priv->tx_buf_mgmt[i] = NULL;
431 }
432
433 memset(ring_control, 0, sizeof(*ring_control));
434 }
435
436 static int p54p_open(struct ieee80211_hw *dev)
437 {
438 struct p54p_priv *priv = dev->priv;
439 int err;
440
441 init_completion(&priv->boot_comp);
442 err = request_irq(priv->pdev->irq, &p54p_interrupt,
443 IRQF_SHARED, "p54pci", dev);
444 if (err) {
445 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
446 return err;
447 }
448
449 memset(priv->ring_control, 0, sizeof(*priv->ring_control));
450 err = p54p_upload_firmware(dev);
451 if (err) {
452 free_irq(priv->pdev->irq, dev);
453 return err;
454 }
455 priv->rx_idx_data = priv->tx_idx_data = 0;
456 priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
457
458 p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
459 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
460
461 p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
462 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
463
464 P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
465 P54P_READ(ring_control_base);
466 wmb();
467 udelay(10);
468
469 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
470 P54P_READ(int_enable);
471 wmb();
472 udelay(10);
473
474 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
475 P54P_READ(dev_int);
476
477 if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
478 printk(KERN_ERR "%s: Cannot boot firmware!\n",
479 wiphy_name(dev->wiphy));
480 p54p_stop(dev);
481 return -ETIMEDOUT;
482 }
483
484 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
485 P54P_READ(int_enable);
486 wmb();
487 udelay(10);
488
489 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
490 P54P_READ(dev_int);
491 wmb();
492 udelay(10);
493
494 return 0;
495 }
496
497 static int __devinit p54p_probe(struct pci_dev *pdev,
498 const struct pci_device_id *id)
499 {
500 struct p54p_priv *priv;
501 struct ieee80211_hw *dev;
502 unsigned long mem_addr, mem_len;
503 int err;
504
505 err = pci_enable_device(pdev);
506 if (err) {
507 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
508 return err;
509 }
510
511 mem_addr = pci_resource_start(pdev, 0);
512 mem_len = pci_resource_len(pdev, 0);
513 if (mem_len < sizeof(struct p54p_csr)) {
514 dev_err(&pdev->dev, "Too short PCI resources\n");
515 goto err_disable_dev;
516 }
517
518 err = pci_request_regions(pdev, "p54pci");
519 if (err) {
520 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
521 goto err_disable_dev;
522 }
523
524 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
525 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
526 dev_err(&pdev->dev, "No suitable DMA available\n");
527 goto err_free_reg;
528 }
529
530 pci_set_master(pdev);
531 pci_try_set_mwi(pdev);
532
533 pci_write_config_byte(pdev, 0x40, 0);
534 pci_write_config_byte(pdev, 0x41, 0);
535
536 dev = p54_init_common(sizeof(*priv));
537 if (!dev) {
538 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
539 err = -ENOMEM;
540 goto err_free_reg;
541 }
542
543 priv = dev->priv;
544 priv->pdev = pdev;
545
546 SET_IEEE80211_DEV(dev, &pdev->dev);
547 pci_set_drvdata(pdev, dev);
548
549 priv->map = ioremap(mem_addr, mem_len);
550 if (!priv->map) {
551 dev_err(&pdev->dev, "Cannot map device memory\n");
552 err = -ENOMEM;
553 goto err_free_dev;
554 }
555
556 priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
557 &priv->ring_control_dma);
558 if (!priv->ring_control) {
559 dev_err(&pdev->dev, "Cannot allocate rings\n");
560 err = -ENOMEM;
561 goto err_iounmap;
562 }
563 priv->common.open = p54p_open;
564 priv->common.stop = p54p_stop;
565 priv->common.tx = p54p_tx;
566
567 spin_lock_init(&priv->lock);
568 tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
569
570 err = request_firmware(&priv->firmware, "isl3886pci",
571 &priv->pdev->dev);
572 if (err) {
573 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
574 err = request_firmware(&priv->firmware, "isl3886",
575 &priv->pdev->dev);
576 if (err)
577 goto err_free_common;
578 }
579
580 err = p54p_open(dev);
581 if (err)
582 goto err_free_common;
583 err = p54_read_eeprom(dev);
584 p54p_stop(dev);
585 if (err)
586 goto err_free_common;
587
588 err = p54_register_common(dev, &pdev->dev);
589 if (err)
590 goto err_free_common;
591
592 return 0;
593
594 err_free_common:
595 release_firmware(priv->firmware);
596 pci_free_consistent(pdev, sizeof(*priv->ring_control),
597 priv->ring_control, priv->ring_control_dma);
598
599 err_iounmap:
600 iounmap(priv->map);
601
602 err_free_dev:
603 pci_set_drvdata(pdev, NULL);
604 p54_free_common(dev);
605
606 err_free_reg:
607 pci_release_regions(pdev);
608 err_disable_dev:
609 pci_disable_device(pdev);
610 return err;
611 }
612
613 static void __devexit p54p_remove(struct pci_dev *pdev)
614 {
615 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
616 struct p54p_priv *priv;
617
618 if (!dev)
619 return;
620
621 p54_unregister_common(dev);
622 priv = dev->priv;
623 release_firmware(priv->firmware);
624 pci_free_consistent(pdev, sizeof(*priv->ring_control),
625 priv->ring_control, priv->ring_control_dma);
626 iounmap(priv->map);
627 pci_release_regions(pdev);
628 pci_disable_device(pdev);
629 p54_free_common(dev);
630 }
631
632 #ifdef CONFIG_PM
633 static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
634 {
635 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
636 struct p54p_priv *priv = dev->priv;
637
638 if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
639 ieee80211_stop_queues(dev);
640 p54p_stop(dev);
641 }
642
643 pci_save_state(pdev);
644 pci_set_power_state(pdev, pci_choose_state(pdev, state));
645 return 0;
646 }
647
648 static int p54p_resume(struct pci_dev *pdev)
649 {
650 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
651 struct p54p_priv *priv = dev->priv;
652
653 pci_set_power_state(pdev, PCI_D0);
654 pci_restore_state(pdev);
655
656 if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
657 p54p_open(dev);
658 ieee80211_wake_queues(dev);
659 }
660
661 return 0;
662 }
663 #endif /* CONFIG_PM */
664
665 static struct pci_driver p54p_driver = {
666 .name = "p54pci",
667 .id_table = p54p_table,
668 .probe = p54p_probe,
669 .remove = __devexit_p(p54p_remove),
670 #ifdef CONFIG_PM
671 .suspend = p54p_suspend,
672 .resume = p54p_resume,
673 #endif /* CONFIG_PM */
674 };
675
676 static int __init p54p_init(void)
677 {
678 return pci_register_driver(&p54p_driver);
679 }
680
681 static void __exit p54p_exit(void)
682 {
683 pci_unregister_driver(&p54p_driver);
684 }
685
686 module_init(p54p_init);
687 module_exit(p54p_exit);
Linux MOXA ART SoC ARM port