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init from v2.6.32.60
[mach-moxart.git] / drivers / staging / rtl8187se / r8185b_init.c
blobc30773b5c59e715c9f4714a88339c0fe4db5bc47
1 /*++
2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
3
4 Module Name:
5 r8185b_init.c
6
7 Abstract:
8 Hardware Initialization and Hardware IO for RTL8185B
9
10 Major Change History:
11 When Who What
12 ---------- --------------- -------------------------------
13 2006-11-15 Xiong Created
14
15 Notes:
16 This file is ported from RTL8185B Windows driver.
17
18
19 --*/
20
21 /*--------------------------Include File------------------------------------*/
22 #include <linux/spinlock.h>
23 #include "r8180_hw.h"
24 #include "r8180.h"
25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
26 #include "r8180_93cx6.h" /* Card EEPROM */
27 #include "r8180_wx.h"
28
29 #include "ieee80211/dot11d.h"
30
31
32 //#define CONFIG_RTL8180_IO_MAP
33
34 #define TC_3W_POLL_MAX_TRY_CNT 5
35 static u8 MAC_REG_TABLE[][2]={
36 //PAGA 0:
37 // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
38 // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
39 // 0x1F0~0x1F8 set in MacConfig_85BASIC()
40 {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
41 {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
42 {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
43 {0x94, 0x0F}, {0x95, 0x32},
44 {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
45 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
46 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
47 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
48 {0xff, 0x00},
49
50 //PAGE 1:
51 // For Flextronics system Logo PCIHCT failure:
52 // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
53 {0x5e, 0x01},
54 {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
55 {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
56 {0x82, 0xFF}, {0x83, 0x03},
57 {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
58 {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
59 {0xe2, 0x00},
60
61
62 //PAGE 2:
63 {0x5e, 0x02},
64 {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
65 {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
66 {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
67 {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
68 {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
69 {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
70 {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
71
72 //PAGA 0:
73 {0x5e, 0x00},{0x9f, 0x03}
74 };
75
76
77 static u8 ZEBRA_AGC[]={
78 0,
79 0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
80 0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
81 0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
82 0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
83 0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
84 0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
85 0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
86 0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
87 };
88
89 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
90 0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
91 0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
92 0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
93 0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
94 0x0183,0x0163,0x0143,0x0123,0x0103
95 };
96
97 static u8 OFDM_CONFIG[]={
98 // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
99 // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
100 // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
101
102 // 0x00
103 0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
104 0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
105 // 0x10
106 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
107 0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
108 // 0x20
109 0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
110 0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
111 // 0x30
112 0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
113 0xD8, 0x3C, 0x7B, 0x10, 0x10
114 };
115
116 /*---------------------------------------------------------------
117 * Hardware IO
118 * the code is ported from Windows source code
119 ----------------------------------------------------------------*/
120
121 void
122 PlatformIOWrite1Byte(
123 struct net_device *dev,
124 u32 offset,
125 u8 data
126 )
127 {
128 write_nic_byte(dev, offset, data);
129 read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
130
131 }
132
133 void
134 PlatformIOWrite2Byte(
135 struct net_device *dev,
136 u32 offset,
137 u16 data
138 )
139 {
140 write_nic_word(dev, offset, data);
141 read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
142
143
144 }
145 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
146
147 void
148 PlatformIOWrite4Byte(
149 struct net_device *dev,
150 u32 offset,
151 u32 data
152 )
153 {
154 //{by amy 080312
155 if (offset == PhyAddr)
156 {//For Base Band configuration.
157 unsigned char cmdByte;
158 unsigned long dataBytes;
159 unsigned char idx;
160 u8 u1bTmp;
161
162 cmdByte = (u8)(data & 0x000000ff);
163 dataBytes = data>>8;
164
165 //
166 // 071010, rcnjko:
167 // The critical section is only BB read/write race condition.
168 // Assumption:
169 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
170 // acquiring the spinlock in such context.
171 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
172 //
173 // NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
174
175 for(idx = 0; idx < 30; idx++)
176 { // Make sure command bit is clear before access it.
177 u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
178 if((u1bTmp & BIT7) == 0)
179 break;
180 else
181 mdelay(10);
182 }
183
184 for(idx=0; idx < 3; idx++)
185 {
186 PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
187 }
188 write_nic_byte(dev, offset, cmdByte);
189
190 // NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
191 }
192 //by amy 080312}
193 else{
194 write_nic_dword(dev, offset, data);
195 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
196 }
197 }
198
199 u8
200 PlatformIORead1Byte(
201 struct net_device *dev,
202 u32 offset
203 )
204 {
205 u8 data = 0;
206
207 data = read_nic_byte(dev, offset);
208
209
210 return data;
211 }
212
213 u16
214 PlatformIORead2Byte(
215 struct net_device *dev,
216 u32 offset
217 )
218 {
219 u16 data = 0;
220
221 data = read_nic_word(dev, offset);
222
223
224 return data;
225 }
226
227 u32
228 PlatformIORead4Byte(
229 struct net_device *dev,
230 u32 offset
231 )
232 {
233 u32 data = 0;
234
235 data = read_nic_dword(dev, offset);
236
237
238 return data;
239 }
240
241 void
242 SetOutputEnableOfRfPins(
243 struct net_device *dev
244 )
245 {
246 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
247
248 switch(priv->rf_chip)
249 {
250 case RFCHIPID_RTL8225:
251 case RF_ZEBRA2:
252 case RF_ZEBRA4:
253 write_nic_word(dev, RFPinsEnable, 0x1bff);
254 //write_nic_word(dev, RFPinsEnable, 0x1fff);
255 break;
256 }
257 }
258
259 void
260 ZEBRA_RFSerialWrite(
261 struct net_device *dev,
262 u32 data2Write,
263 u8 totalLength,
264 u8 low2high
265 )
266 {
267 ThreeWireReg twreg;
268 int i;
269 u16 oval,oval2,oval3;
270 u32 mask;
271 u16 UshortBuffer;
272
273 u8 u1bTmp;
274 // RTL8187S HSSI Read/Write Function
275 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
276 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
277 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
278 UshortBuffer = read_nic_word(dev, RFPinsOutput);
279 oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
280
281 oval2 = read_nic_word(dev, RFPinsEnable);
282 oval3 = read_nic_word(dev, RFPinsSelect);
283
284 // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
285 oval3 &= 0xfff8;
286
287 write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
288 write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
289 udelay(10);
290
291 // Add this to avoid hardware and software 3-wire conflict.
292 // 2005.03.01, by rcnjko.
293 twreg.longData = 0;
294 twreg.struc.enableB = 1;
295 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
296 udelay(2);
297 twreg.struc.enableB = 0;
298 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
299 udelay(10);
300
301 mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
302
303 for(i=0; i<totalLength/2; i++)
304 {
305 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
306 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
307 twreg.struc.clk = 1;
308 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
309 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
310
311 mask = (low2high)?(mask<<1):(mask>>1);
312 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
313 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
314 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
315 twreg.struc.clk = 0;
316 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
317 mask = (low2high)?(mask<<1):(mask>>1);
318 }
319
320 twreg.struc.enableB = 1;
321 twreg.struc.clk = 0;
322 twreg.struc.data = 0;
323 write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
324 udelay(10);
325
326 write_nic_word(dev, RFPinsOutput, oval|0x0004);
327 write_nic_word(dev, RFPinsSelect, oval3|0x0000);
328
329 SetOutputEnableOfRfPins(dev);
330 }
331 //by amy
332
333
334 int
335 HwHSSIThreeWire(
336 struct net_device *dev,
337 u8 *pDataBuf,
338 u8 nDataBufBitCnt,
339 int bSI,
340 int bWrite
341 )
342 {
343 int bResult = 1;
344 u8 TryCnt;
345 u8 u1bTmp;
346
347 do
348 {
349 // Check if WE and RE are cleared.
350 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
351 {
352 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
353 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
354 {
355 break;
356 }
357 udelay(10);
358 }
359 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT) {
360 printk(KERN_ERR "rtl8187se: HwThreeWire(): CmdReg:"
361 " %#X RE|WE bits are not clear!!\n", u1bTmp);
362 dump_stack();
363 return 0;
364 }
365
366 // RTL8187S HSSI Read/Write Function
367 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
368
369 if(bSI)
370 {
371 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
372 }else
373 {
374 u1bTmp &= ~RF_SW_CFG_SI; //reg08[1]=0 Parallel Interface(PI)
375 }
376
377 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
378
379 if(bSI)
380 {
381 // jong: HW SI read must set reg84[3]=0.
382 u1bTmp = read_nic_byte(dev, RFPinsSelect);
383 u1bTmp &= ~BIT3;
384 write_nic_byte(dev, RFPinsSelect, u1bTmp );
385 }
386 // Fill up data buffer for write operation.
387
388 if(bWrite)
389 {
390 if(nDataBufBitCnt == 16)
391 {
392 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
393 }
394 else if(nDataBufBitCnt == 64) // RTL8187S shouldn't enter this case
395 {
396 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
397 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
398 }
399 else
400 {
401 int idx;
402 int ByteCnt = nDataBufBitCnt / 8;
403 //printk("%d\n",nDataBufBitCnt);
404 if ((nDataBufBitCnt % 8) != 0) {
405 printk(KERN_ERR "rtl8187se: "
406 "HwThreeWire(): nDataBufBitCnt(%d)"
407 " should be multiple of 8!!!\n",
408 nDataBufBitCnt);
409 dump_stack();
410 nDataBufBitCnt += 8;
411 nDataBufBitCnt &= ~7;
412 }
413
414 if (nDataBufBitCnt > 64) {
415 printk(KERN_ERR "rtl8187se: HwThreeWire():"
416 " nDataBufBitCnt(%d) should <= 64!!!\n",
417 nDataBufBitCnt);
418 dump_stack();
419 nDataBufBitCnt = 64;
420 }
421
422 for(idx = 0; idx < ByteCnt; idx++)
423 {
424 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
425 }
426 }
427 }
428 else //read
429 {
430 if(bSI)
431 {
432 // SI - reg274[3:0] : RF register's Address
433 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
434 }
435 else
436 {
437 // PI - reg274[15:12] : RF register's Address
438 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
439 }
440 }
441
442 // Set up command: WE or RE.
443 if(bWrite)
444 {
445 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
446 }
447 else
448 {
449 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
450 }
451
452 // Check if DONE is set.
453 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
454 {
455 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
456 if( (u1bTmp & SW_3W_CMD1_DONE) != 0 )
457 {
458 break;
459 }
460 udelay(10);
461 }
462
463 write_nic_byte(dev, SW_3W_CMD1, 0);
464
465 // Read back data for read operation.
466 if(bWrite == 0)
467 {
468 if(bSI)
469 {
470 //Serial Interface : reg363_362[11:0]
471 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
472 }
473 else
474 {
475 //Parallel Interface : reg361_360[11:0]
476 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
477 }
478
479 *((u16*)pDataBuf) &= 0x0FFF;
480 }
481
482 }while(0);
483
484 return bResult;
485 }
486 //by amy
487
488 int
489 HwThreeWire(
490 struct net_device *dev,
491 u8 *pDataBuf,
492 u8 nDataBufBitCnt,
493 int bHold,
494 int bWrite
495 )
496 {
497 int bResult = 1;
498 u8 TryCnt;
499 u8 u1bTmp;
500
501 do
502 {
503 // Check if WE and RE are cleared.
504 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
505 {
506 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
507 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
508 {
509 break;
510 }
511 udelay(10);
512 }
513 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
514 panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
515
516 // Fill up data buffer for write operation.
517 if(nDataBufBitCnt == 16)
518 {
519 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
520 }
521 else if(nDataBufBitCnt == 64)
522 {
523 write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
524 write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
525 }
526 else
527 {
528 int idx;
529 int ByteCnt = nDataBufBitCnt / 8;
530
531 if ((nDataBufBitCnt % 8) != 0)
532 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
533 nDataBufBitCnt);
534
535 if (nDataBufBitCnt > 64)
536 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
537 nDataBufBitCnt);
538
539 for(idx = 0; idx < ByteCnt; idx++)
540 {
541 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
542 }
543 }
544
545 // Fill up length field.
546 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
547 if(bHold)
548 u1bTmp |= SW_3W_CMD0_HOLD;
549 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
550
551 // Set up command: WE or RE.
552 if(bWrite)
553 {
554 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
555 }
556 else
557 {
558 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
559 }
560
561 // Check if WE and RE are cleared and DONE is set.
562 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
563 {
564 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
565 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
566 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
567 {
568 break;
569 }
570 udelay(10);
571 }
572 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
573 {
574 //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
575 // ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
576 // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
577 write_nic_byte(dev, SW_3W_CMD1, 0);
578 }
579
580 // Read back data for read operation.
581 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
582 if(bWrite == 0)
583 {
584 if(nDataBufBitCnt == 16)
585 {
586 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
587 }
588 else if(nDataBufBitCnt == 64)
589 {
590 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
591 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
592 }
593 else
594 {
595 int idx;
596 int ByteCnt = nDataBufBitCnt / 8;
597
598 if ((nDataBufBitCnt % 8) != 0)
599 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
600 nDataBufBitCnt);
601
602 if (nDataBufBitCnt > 64)
603 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
604 nDataBufBitCnt);
605
606 for(idx = 0; idx < ByteCnt; idx++)
607 {
608 *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
609 }
610 }
611 }
612
613 }while(0);
614
615 return bResult;
616 }
617
618
619 void
620 RF_WriteReg(
621 struct net_device *dev,
622 u8 offset,
623 u32 data
624 )
625 {
626 //RFReg reg;
627 u32 data2Write;
628 u8 len;
629 u8 low2high;
630 //u32 RF_Read = 0;
631 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
632
633
634 switch(priv->rf_chip)
635 {
636 case RFCHIPID_RTL8225:
637 case RF_ZEBRA2: // Annie 2006-05-12.
638 case RF_ZEBRA4: //by amy
639 switch(priv->RegThreeWireMode)
640 {
641 case SW_THREE_WIRE:
642 { // Perform SW 3-wire programming by driver.
643 data2Write = (data << 4) | (u32)(offset & 0x0f);
644 len = 16;
645 low2high = 0;
646 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
647 }
648 break;
649
650 case HW_THREE_WIRE:
651 { // Pure HW 3-wire.
652 data2Write = (data << 4) | (u32)(offset & 0x0f);
653 len = 16;
654 HwThreeWire(
655 dev,
656 (u8 *)(&data2Write), // pDataBuf,
657 len, // nDataBufBitCnt,
658 0, // bHold,
659 1); // bWrite
660 }
661 break;
662 case HW_THREE_WIRE_PI: //Parallel Interface
663 { // Pure HW 3-wire.
664 data2Write = (data << 4) | (u32)(offset & 0x0f);
665 len = 16;
666 HwHSSIThreeWire(
667 dev,
668 (u8*)(&data2Write), // pDataBuf,
669 len, // nDataBufBitCnt,
670 0, // bSI
671 1); // bWrite
672
673 //printk("33333\n");
674 }
675 break;
676
677 case HW_THREE_WIRE_SI: //Serial Interface
678 { // Pure HW 3-wire.
679 data2Write = (data << 4) | (u32)(offset & 0x0f);
680 len = 16;
681 // printk(" enter ZEBRA_RFSerialWrite\n ");
682 // low2high = 0;
683 // ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
684
685 HwHSSIThreeWire(
686 dev,
687 (u8*)(&data2Write), // pDataBuf,
688 len, // nDataBufBitCnt,
689 1, // bSI
690 1); // bWrite
691
692 // printk(" exit ZEBRA_RFSerialWrite\n ");
693 }
694 break;
695
696
697 default:
698 DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
699 break;
700 }
701 break;
702
703 default:
704 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
705 break;
706 }
707 }
708
709
710 void
711 ZEBRA_RFSerialRead(
712 struct net_device *dev,
713 u32 data2Write,
714 u8 wLength,
715 u32 *data2Read,
716 u8 rLength,
717 u8 low2high
718 )
719 {
720 ThreeWireReg twreg;
721 int i;
722 u16 oval,oval2,oval3,tmp, wReg80;
723 u32 mask;
724 u8 u1bTmp;
725 ThreeWireReg tdata;
726 //PHAL_DATA_8187 pHalData = GetHalData8187(pAdapter);
727 { // RTL8187S HSSI Read/Write Function
728 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
729 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
730 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
731 }
732
733 wReg80 = oval = read_nic_word(dev, RFPinsOutput);
734 oval2 = read_nic_word(dev, RFPinsEnable);
735 oval3 = read_nic_word(dev, RFPinsSelect);
736
737 write_nic_word(dev, RFPinsEnable, oval2|0xf);
738 write_nic_word(dev, RFPinsSelect, oval3|0xf);
739
740 *data2Read = 0;
741
742 // We must clear BIT0-3 here, otherwise,
743 // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
744 // which will cause the value read become 0. 2005.04.11, by rcnjko.
745 oval &= ~0xf;
746
747 // Avoid collision with hardware three-wire.
748 twreg.longData = 0;
749 twreg.struc.enableB = 1;
750 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
751
752 twreg.longData = 0;
753 twreg.struc.enableB = 0;
754 twreg.struc.clk = 0;
755 twreg.struc.read_write = 0;
756 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
757
758 mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
759 for(i = 0; i < wLength/2; i++)
760 {
761 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
762 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
763 twreg.struc.clk = 1;
764 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
765 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
766
767 mask = (low2high) ? (mask<<1): (mask>>1);
768
769 if(i == 2)
770 {
771 // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
772 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe); // turn off data enable
773 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
774
775 twreg.struc.read_write=1;
776 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
777 twreg.struc.clk = 0;
778 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
779 break;
780 }
781 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
782 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
783 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
784
785 twreg.struc.clk = 0;
786 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
787
788 mask = (low2high) ? (mask<<1) : (mask>>1);
789 }
790
791 twreg.struc.clk = 0;
792 twreg.struc.data = 0;
793 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
794 mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
795
796 //
797 // 061016, by rcnjko:
798 // We must set data pin to HW controled, otherwise RF can't driver it and
799 // value RF register won't be able to read back properly.
800 //
801 write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
802
803 for(i = 0; i < rLength; i++)
804 {
805 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
806 twreg.struc.clk = 1;
807 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
808 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
809 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
810 tmp = read_nic_word(dev, RFPinsInput);
811 tdata.longData = tmp;
812 *data2Read |= tdata.struc.clk ? mask : 0;
813
814 twreg.struc.clk = 0;
815 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
816
817 mask = (low2high) ? (mask<<1) : (mask>>1);
818 }
819 twreg.struc.enableB = 1;
820 twreg.struc.clk = 0;
821 twreg.struc.data = 0;
822 twreg.struc.read_write = 1;
823 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
824
825 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8); // Set To Output Enable
826 write_nic_word(dev, RFPinsEnable, oval2); // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
827 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
828 write_nic_word(dev, RFPinsSelect, oval3); // Set To SW Switch
829 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
830 write_nic_word(dev, RFPinsOutput, 0x3a0);
831 //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
832 }
833
834
835 u32
836 RF_ReadReg(
837 struct net_device *dev,
838 u8 offset
839 )
840 {
841 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
842 u32 data2Write;
843 u8 wlen;
844 u8 rlen;
845 u8 low2high;
846 u32 dataRead;
847
848 switch(priv->rf_chip)
849 {
850 case RFCHIPID_RTL8225:
851 case RF_ZEBRA2:
852 case RF_ZEBRA4:
853 switch(priv->RegThreeWireMode)
854 {
855 case HW_THREE_WIRE_PI: // For 87S Parallel Interface.
856 {
857 data2Write = ((u32)(offset&0x0f));
858 wlen=16;
859 HwHSSIThreeWire(
860 dev,
861 (u8*)(&data2Write), // pDataBuf,
862 wlen, // nDataBufBitCnt,
863 0, // bSI
864 0); // bWrite
865 dataRead= data2Write;
866 }
867 break;
868
869 case HW_THREE_WIRE_SI: // For 87S Serial Interface.
870 {
871 data2Write = ((u32)(offset&0x0f)) ;
872 wlen=16;
873 HwHSSIThreeWire(
874 dev,
875 (u8*)(&data2Write), // pDataBuf,
876 wlen, // nDataBufBitCnt,
877 1, // bSI
878 0 // bWrite
879 );
880 dataRead= data2Write;
881 }
882 break;
883
884 // Perform SW 3-wire programming by driver.
885 default:
886 {
887 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
888 wlen = 6;
889 rlen = 12;
890 low2high = 0;
891 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
892 }
893 break;
894 }
895 break;
896 default:
897 dataRead = 0;
898 break;
899 }
900
901 return dataRead;
902 }
903
904
905 // by Owen on 04/07/14 for writing BB register successfully
906 void
907 WriteBBPortUchar(
908 struct net_device *dev,
909 u32 Data
910 )
911 {
912 //u8 TimeoutCounter;
913 u8 RegisterContent;
914 u8 UCharData;
915
916 UCharData = (u8)((Data & 0x0000ff00) >> 8);
917 PlatformIOWrite4Byte(dev, PhyAddr, Data);
918 //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
919 {
920 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
921 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
922 //if(UCharData == RegisterContent)
923 // break;
924 }
925 }
926
927 u8
928 ReadBBPortUchar(
929 struct net_device *dev,
930 u32 addr
931 )
932 {
933 //u8 TimeoutCounter;
934 u8 RegisterContent;
935
936 PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
937 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
938
939 return RegisterContent;
940 }
941 //{by amy 080312
942 //
943 // Description:
944 // Perform Antenna settings with antenna diversity on 87SE.
945 // Created by Roger, 2008.01.25.
946 //
947 bool
948 SetAntennaConfig87SE(
949 struct net_device *dev,
950 u8 DefaultAnt, // 0: Main, 1: Aux.
951 bool bAntDiversity // 1:Enable, 0: Disable.
952 )
953 {
954 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
955 bool bAntennaSwitched = true;
956
957 //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
958
959 // Threshold for antenna diversity.
960 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
961
962 if( bAntDiversity ) // Enable Antenna Diversity.
963 {
964 if( DefaultAnt == 1 ) // aux antenna
965 {
966 // Mac register, aux antenna
967 write_nic_byte(dev, ANTSEL, 0x00);
968
969 // Config CCK RX antenna.
970 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
971 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
972
973 // Config OFDM RX antenna.
974 write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54
975 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
976 }
977 else // use main antenna
978 {
979 // Mac register, main antenna
980 write_nic_byte(dev, ANTSEL, 0x03);
981 //base band
982 // Config CCK RX antenna.
983 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
984 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
985
986 // Config OFDM RX antenna.
987 write_phy_ofdm(dev, 0x0d, 0x5c); // Reg0d : 5c
988 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
989 }
990 }
991 else // Disable Antenna Diversity.
992 {
993 if( DefaultAnt == 1 ) // aux Antenna
994 {
995 // Mac register, aux antenna
996 write_nic_byte(dev, ANTSEL, 0x00);
997
998 // Config CCK RX antenna.
999 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1000 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1001
1002 // Config OFDM RX antenna.
1003 write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54
1004 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1005 }
1006 else // main Antenna
1007 {
1008 // Mac register, main antenna
1009 write_nic_byte(dev, ANTSEL, 0x03);
1010
1011 // Config CCK RX antenna.
1012 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1013 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1014
1015 // Config OFDM RX antenna.
1016 write_phy_ofdm(dev, 0x0D, 0x5c); // Reg0d : 5c
1017 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1018 }
1019 }
1020 priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1021 return bAntennaSwitched;
1022 }
1023 //by amy 080312
1024 /*---------------------------------------------------------------
1025 * Hardware Initialization.
1026 * the code is ported from Windows source code
1027 ----------------------------------------------------------------*/
1028
1029 void
1030 ZEBRA_Config_85BASIC_HardCode(
1031 struct net_device *dev
1032 )
1033 {
1034
1035 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1036 u32 i;
1037 u32 addr,data;
1038 u32 u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1039 u8 u1b24E;
1040
1041
1042 //=============================================================================
1043 // 87S_PCIE :: RADIOCFG.TXT
1044 //=============================================================================
1045
1046
1047 // Page1 : reg16-reg30
1048 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1); // switch to page1
1049 u4bRF23= RF_ReadReg(dev, 0x08); mdelay(1);
1050 u4bRF24= RF_ReadReg(dev, 0x09); mdelay(1);
1051
1052 if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1053 priv->card_8185 = VERSION_8187S_D;
1054
1055 // Page0 : reg0-reg15
1056
1057 // RF_WriteReg(dev, 0x00, 0x003f); mdelay(1);//1
1058 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);// 1
1059
1060 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1);
1061
1062 // RF_WriteReg(dev, 0x02, 0x004c); mdelay(1);//2
1063 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);// 2
1064
1065 // RF_WriteReg(dev, 0x03, 0x0000); mdelay(1);//3
1066 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);// 3
1067
1068 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1);
1069 RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1);
1070 RF_WriteReg(dev, 0x06, 0x0ae6); mdelay(1);
1071 RF_WriteReg(dev, 0x07, 0x00ca); mdelay(1);
1072 RF_WriteReg(dev, 0x08, 0x0e1c); mdelay(1);
1073 RF_WriteReg(dev, 0x09, 0x02f0); mdelay(1);
1074 RF_WriteReg(dev, 0x0a, 0x09d0); mdelay(1);
1075 RF_WriteReg(dev, 0x0b, 0x01ba); mdelay(1);
1076 RF_WriteReg(dev, 0x0c, 0x0640); mdelay(1);
1077 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
1078 RF_WriteReg(dev, 0x0e, 0x0020); mdelay(1);
1079 RF_WriteReg(dev, 0x0f, 0x0990); mdelay(1);
1080
1081
1082 // Page1 : reg16-reg30
1083 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1);
1084
1085 RF_WriteReg(dev, 0x03, 0x0806); mdelay(1);
1086
1087 if(priv->card_8185 < VERSION_8187S_C)
1088 {
1089 RF_WriteReg(dev, 0x04, 0x03f7); mdelay(1);
1090 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1);
1091 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
1092 }
1093 else
1094 {
1095 RF_WriteReg(dev, 0x04, 0x03a7); mdelay(1);
1096 RF_WriteReg(dev, 0x05, 0x059b); mdelay(1);
1097 RF_WriteReg(dev, 0x06, 0x0081); mdelay(1);
1098 }
1099
1100
1101 RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1);
1102 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1103 // RF_WriteReg(dev, 0x08, 0x0597); mdelay(1);
1104 // RF_WriteReg(dev, 0x09, 0x050a); mdelay(1);
1105 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
1106 RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1);
1107
1108 if(priv->card_8185 == VERSION_8187S_D)
1109 {
1110 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
1111 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
1112 RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1); // RX LO buffer
1113 }
1114 else
1115 {
1116 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
1117 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
1118 RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1); // RX LO buffer
1119 }
1120
1121 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
1122
1123 // RF_WriteReg(dev, 0x00, 0x017f); mdelay(1);//6
1124 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1);// 6
1125
1126 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1);
1127 RF_WriteReg(dev, 0x04, 0x0e50); mdelay(1);
1128 for(i=0;i<=36;i++)
1129 {
1130 RF_WriteReg(dev, 0x01, i); mdelay(1);
1131 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1132 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1133 }
1134
1135 RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /// 203, 343
1136 //RF_WriteReg(dev, 0x06, 0x0300); mdelay(1); // 400
1137 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); // 400
1138
1139 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30, and HSSI disable 137
1140 mdelay(10); // Deay 10 ms. //0xfd
1141
1142 // RF_WriteReg(dev, 0x0c, 0x09be); mdelay(1); // 7
1143 //RF_WriteReg(dev, 0x0c, 0x07be); mdelay(1);
1144 //mdelay(10); // Deay 10 ms. //0xfd
1145
1146 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); // Z4 synthesizer loop filter setting, 392
1147 mdelay(10); // Deay 10 ms. //0xfd
1148
1149 RF_WriteReg(dev, 0x00, 0x0037); mdelay(1); // switch to reg0-reg15, and HSSI disable
1150 mdelay(10); // Deay 10 ms. //0xfd
1151
1152 RF_WriteReg(dev, 0x04, 0x0160); mdelay(1); // CBC on, Tx Rx disable, High gain
1153 mdelay(10); // Deay 10 ms. //0xfd
1154
1155 RF_WriteReg(dev, 0x07, 0x0080); mdelay(1); // Z4 setted channel 1
1156 mdelay(10); // Deay 10 ms. //0xfd
1157
1158 RF_WriteReg(dev, 0x02, 0x088D); mdelay(1); // LC calibration
1159 mdelay(200); // Deay 200 ms. //0xfd
1160 mdelay(10); // Deay 10 ms. //0xfd
1161 mdelay(10); // Deay 10 ms. //0xfd
1162
1163 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30 137, and HSSI disable 137
1164 mdelay(10); // Deay 10 ms. //0xfd
1165
1166 RF_WriteReg(dev, 0x07, 0x0000); mdelay(1);
1167 RF_WriteReg(dev, 0x07, 0x0180); mdelay(1);
1168 RF_WriteReg(dev, 0x07, 0x0220); mdelay(1);
1169 RF_WriteReg(dev, 0x07, 0x03E0); mdelay(1);
1170
1171 // DAC calibration off 20070702
1172 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
1173 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
1174 //{by amy 080312
1175 // For crystal calibration, added by Roger, 2007.12.11.
1176 if( priv->bXtalCalibration ) // reg 30.
1177 { // enable crystal calibration.
1178 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5], addr[4:0].
1179 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1180 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1181 // So we should minus 4 BITs offset.
1182 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9); mdelay(1);
1183 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1184 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1185 }
1186 else
1187 { // using default value. Xin=6, Xout=6.
1188 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
1189 }
1190 //by amy 080312
1191 // RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); //-by amy 080312
1192
1193 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); // switch to reg0-reg15, and HSSI enable
1194 // RF_WriteReg(dev, 0x0d, 0x009f); mdelay(1); // Rx BB start calibration, 00c//-edward
1195 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); // Rx BB start calibration, 00c//+edward
1196 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); // temperature meter off
1197 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); // Rx mode
1198 mdelay(10); // Deay 10 ms. //0xfe
1199 mdelay(10); // Deay 10 ms. //0xfe
1200 mdelay(10); // Deay 10 ms. //0xfe
1201 RF_WriteReg(dev, 0x00, 0x0197); mdelay(1); // Rx mode//+edward
1202 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1); // Rx mode//+edward
1203 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1); // Rx mode//+edward
1204
1205 RF_WriteReg(dev, 0x01, 0x0000); mdelay(1); // Rx mode//+edward
1206 RF_WriteReg(dev, 0x02, 0x0000); mdelay(1); // Rx mode//+edward
1207 //power save parameters.
1208 u1b24E = read_nic_byte(dev, 0x24E);
1209 write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1210
1211 //=============================================================================
1212
1213 //=============================================================================
1214 // CCKCONF.TXT
1215 //=============================================================================
1216
1217 /* [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1218 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1219 CCK reg0x00[6]=1'b1: power saving for RX (default)
1220 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1221 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1222 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1223 */
1224
1225 write_phy_cck(dev,0x00,0xc8);
1226 write_phy_cck(dev,0x06,0x1c);
1227 write_phy_cck(dev,0x10,0x78);
1228 write_phy_cck(dev,0x2e,0xd0);
1229 write_phy_cck(dev,0x2f,0x06);
1230 write_phy_cck(dev,0x01,0x46);
1231
1232 // power control
1233 write_nic_byte(dev, CCK_TXAGC, 0x10);
1234 write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1235 write_nic_byte(dev, ANTSEL, 0x03);
1236
1237
1238
1239 //=============================================================================
1240 // AGC.txt
1241 //=============================================================================
1242
1243 // PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280); // Annie, 2006-05-05
1244 write_phy_ofdm(dev, 0x00, 0x12);
1245 //WriteBBPortUchar(dev, 0x00001280);
1246
1247 for (i=0; i<128; i++)
1248 {
1249 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1250
1251 data = ZEBRA_AGC[i+1];
1252 data = data << 8;
1253 data = data | 0x0000008F;
1254
1255 addr = i + 0x80; //enable writing AGC table
1256 addr = addr << 8;
1257 addr = addr | 0x0000008E;
1258
1259 WriteBBPortUchar(dev, data);
1260 WriteBBPortUchar(dev, addr);
1261 WriteBBPortUchar(dev, 0x0000008E);
1262 }
1263
1264 PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080); // Annie, 2006-05-05
1265 //WriteBBPortUchar(dev, 0x00001080);
1266
1267 //=============================================================================
1268
1269 //=============================================================================
1270 // OFDMCONF.TXT
1271 //=============================================================================
1272
1273 for(i=0; i<60; i++)
1274 {
1275 u4bRegOffset=i;
1276 u4bRegValue=OFDM_CONFIG[i];
1277
1278 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1279
1280 WriteBBPortUchar(dev,
1281 (0x00000080 |
1282 (u4bRegOffset & 0x7f) |
1283 ((u4bRegValue & 0xff) << 8)));
1284 }
1285
1286 //=============================================================================
1287 //by amy for antenna
1288 //=============================================================================
1289 //{by amy 080312
1290 // Config Sw/Hw Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1291 SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1292 //by amy 080312}
1293 //by amy for antenna
1294 }
1295
1296
1297 void
1298 UpdateInitialGain(
1299 struct net_device *dev
1300 )
1301 {
1302 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1303 //unsigned char* IGTable;
1304 //u8 DIG_CurrentInitialGain = 4;
1305 //unsigned char u1Tmp;
1306
1307 //lzm add 080826
1308 if(priv->eRFPowerState != eRfOn)
1309 {
1310 //Don't access BB/RF under disable PLL situation.
1311 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1312 // Back to the original state
1313 priv->InitialGain= priv->InitialGainBackUp;
1314 return;
1315 }
1316
1317 switch(priv->rf_chip)
1318 {
1319 case RF_ZEBRA4:
1320 // Dynamic set initial gain, follow 87B
1321 switch(priv->InitialGain)
1322 {
1323 case 1: //m861dBm
1324 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1325 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
1326 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1327 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1328 break;
1329
1330 case 2: //m862dBm
1331 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1332 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
1333 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1334 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1335 break;
1336
1337 case 3: //m863dBm
1338 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1339 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
1340 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1341 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1342 break;
1343
1344 case 4: //m864dBm
1345 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1346 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
1347 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1348 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1349 break;
1350
1351 case 5: //m82dBm
1352 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1353 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
1354 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
1355 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1356 break;
1357
1358 case 6: //m78dBm
1359 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1360 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
1361 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
1362 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1363 break;
1364
1365 case 7: //m74dBm
1366 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1367 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
1368 write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1);
1369 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1370 break;
1371
1372 case 8:
1373 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1374 write_phy_ofdm(dev, 0x17, 0x66); mdelay(1);
1375 write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1);
1376 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1377 break;
1378
1379
1380 default: //MP
1381 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1382 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
1383 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1384 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1385 break;
1386 }
1387 break;
1388
1389
1390 default:
1391 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1392 break;
1393 }
1394 }
1395 //
1396 // Description:
1397 // Tx Power tracking mechanism routine on 87SE.
1398 // Created by Roger, 2007.12.11.
1399 //
1400 void
1401 InitTxPwrTracking87SE(
1402 struct net_device *dev
1403 )
1404 {
1405 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1406 u32 u4bRfReg;
1407
1408 u4bRfReg = RF_ReadReg(dev, 0x02);
1409
1410 // Enable Thermal meter indication.
1411 //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1412 RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
1413 }
1414
1415 void
1416 PhyConfig8185(
1417 struct net_device *dev
1418 )
1419 {
1420 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1421 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1422 priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1423 // RF config
1424 switch(priv->rf_chip)
1425 {
1426 case RF_ZEBRA2:
1427 case RF_ZEBRA4:
1428 ZEBRA_Config_85BASIC_HardCode( dev);
1429 break;
1430 }
1431 //{by amy 080312
1432 // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1433 if(priv->bDigMechanism)
1434 {
1435 if(priv->InitialGain == 0)
1436 priv->InitialGain = 4;
1437 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1438 }
1439
1440 //
1441 // Enable thermal meter indication to implement TxPower tracking on 87SE.
1442 // We initialize thermal meter here to avoid unsuccessful configuration.
1443 // Added by Roger, 2007.12.11.
1444 //
1445 if(priv->bTxPowerTrack)
1446 InitTxPwrTracking87SE(dev);
1447
1448 //by amy 080312}
1449 priv->InitialGainBackUp= priv->InitialGain;
1450 UpdateInitialGain(dev);
1451
1452 return;
1453 }
1454
1455
1456
1457
1458 void
1459 HwConfigureRTL8185(
1460 struct net_device *dev
1461 )
1462 {
1463 //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1464 // u8 bUNIVERSAL_CONTROL_RL = 1;
1465 u8 bUNIVERSAL_CONTROL_RL = 0;
1466
1467 u8 bUNIVERSAL_CONTROL_AGC = 1;
1468 u8 bUNIVERSAL_CONTROL_ANT = 1;
1469 u8 bAUTO_RATE_FALLBACK_CTL = 1;
1470 u8 val8;
1471 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1472 //struct ieee80211_device *ieee = priv->ieee80211;
1473 //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1474 //{by amy 080312 if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1475 // {
1476 // write_nic_word(dev, BRSR, 0xffff);
1477 // }
1478 // else
1479 // {
1480 // write_nic_word(dev, BRSR, 0x000f);
1481 // }
1482 //by amy 080312}
1483 write_nic_word(dev, BRSR, 0x0fff);
1484 // Retry limit
1485 val8 = read_nic_byte(dev, CW_CONF);
1486
1487 if(bUNIVERSAL_CONTROL_RL)
1488 val8 = val8 & 0xfd;
1489 else
1490 val8 = val8 | 0x02;
1491
1492 write_nic_byte(dev, CW_CONF, val8);
1493
1494 // Tx AGC
1495 val8 = read_nic_byte(dev, TXAGC_CTL);
1496 if(bUNIVERSAL_CONTROL_AGC)
1497 {
1498 write_nic_byte(dev, CCK_TXAGC, 128);
1499 write_nic_byte(dev, OFDM_TXAGC, 128);
1500 val8 = val8 & 0xfe;
1501 }
1502 else
1503 {
1504 val8 = val8 | 0x01 ;
1505 }
1506
1507
1508 write_nic_byte(dev, TXAGC_CTL, val8);
1509
1510 // Tx Antenna including Feedback control
1511 val8 = read_nic_byte(dev, TXAGC_CTL );
1512
1513 if(bUNIVERSAL_CONTROL_ANT)
1514 {
1515 write_nic_byte(dev, ANTSEL, 0x00);
1516 val8 = val8 & 0xfd;
1517 }
1518 else
1519 {
1520 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1521 }
1522
1523 write_nic_byte(dev, TXAGC_CTL, val8);
1524
1525 // Auto Rate fallback control
1526 val8 = read_nic_byte(dev, RATE_FALLBACK);
1527 val8 &= 0x7c;
1528 if( bAUTO_RATE_FALLBACK_CTL )
1529 {
1530 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
1531
1532 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
1533 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
1534 //by amy
1535 // Aadded by Roger, 2007.11.15.
1536 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
1537 //by amy
1538 }
1539 else
1540 {
1541 }
1542 write_nic_byte(dev, RATE_FALLBACK, val8);
1543 }
1544
1545
1546
1547 static void
1548 MacConfig_85BASIC_HardCode(
1549 struct net_device *dev)
1550 {
1551 //============================================================================
1552 // MACREG.TXT
1553 //============================================================================
1554 int nLinesRead = 0;
1555
1556 u32 u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
1557 int i;
1558
1559 nLinesRead=sizeof(MAC_REG_TABLE)/2;
1560
1561 for(i = 0; i < nLinesRead; i++) //nLinesRead=101
1562 {
1563 u4bRegOffset=MAC_REG_TABLE[i][0];
1564 u4bRegValue=MAC_REG_TABLE[i][1];
1565
1566 if(u4bRegOffset == 0x5e)
1567 {
1568 u4bPageIndex = u4bRegValue;
1569 }
1570 else
1571 {
1572 u4bRegOffset |= (u4bPageIndex << 8);
1573 }
1574 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1575 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1576 }
1577 //============================================================================
1578 }
1579
1580
1581
1582 static void
1583 MacConfig_85BASIC(
1584 struct net_device *dev)
1585 {
1586
1587 u8 u1DA;
1588 MacConfig_85BASIC_HardCode(dev);
1589
1590 //============================================================================
1591
1592 // Follow TID_AC_MAP of WMac.
1593 write_nic_word(dev, TID_AC_MAP, 0xfa50);
1594
1595 // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
1596 write_nic_word(dev, IntMig, 0x0000);
1597
1598 // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
1599 PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
1600 PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
1601 PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1602
1603 // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1604 //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
1605 //by amy
1606 // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1607
1608 //Enable DA10 TX power saving
1609 u1DA = read_nic_byte(dev, PHYPR);
1610 write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
1611
1612 //POWER:
1613 write_nic_word(dev, 0x360, 0x1000);
1614 write_nic_word(dev, 0x362, 0x1000);
1615
1616 // AFE.
1617 write_nic_word(dev, 0x370, 0x0560);
1618 write_nic_word(dev, 0x372, 0x0560);
1619 write_nic_word(dev, 0x374, 0x0DA4);
1620 write_nic_word(dev, 0x376, 0x0DA4);
1621 write_nic_word(dev, 0x378, 0x0560);
1622 write_nic_word(dev, 0x37A, 0x0560);
1623 write_nic_word(dev, 0x37C, 0x00EC);
1624 // write_nic_word(dev, 0x37E, 0x00FE);//-edward
1625 write_nic_word(dev, 0x37E, 0x00EC);//+edward
1626 write_nic_byte(dev, 0x24E,0x01);
1627 //by amy
1628
1629 }
1630
1631
1632
1633
1634 u8
1635 GetSupportedWirelessMode8185(
1636 struct net_device *dev
1637 )
1638 {
1639 u8 btSupportedWirelessMode = 0;
1640 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1641
1642 switch(priv->rf_chip)
1643 {
1644 case RF_ZEBRA2:
1645 case RF_ZEBRA4:
1646 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1647 break;
1648 default:
1649 btSupportedWirelessMode = WIRELESS_MODE_B;
1650 break;
1651 }
1652
1653 return btSupportedWirelessMode;
1654 }
1655
1656 void
1657 ActUpdateChannelAccessSetting(
1658 struct net_device *dev,
1659 WIRELESS_MODE WirelessMode,
1660 PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1661 )
1662 {
1663 struct r8180_priv *priv = ieee80211_priv(dev);
1664 struct ieee80211_device *ieee = priv->ieee80211;
1665 AC_CODING eACI;
1666 AC_PARAM AcParam;
1667 //PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos;
1668 u8 bFollowLegacySetting = 0;
1669 u8 u1bAIFS;
1670
1671 //
1672 // <RJ_TODO_8185B>
1673 // TODO: We still don't know how to set up these registers, just follow WMAC to
1674 // verify 8185B FPAG.
1675 //
1676 // <RJ_TODO_8185B>
1677 // Jong said CWmin/CWmax register are not functional in 8185B,
1678 // so we shall fill channel access realted register into AC parameter registers,
1679 // even in nQBss.
1680 //
1681 ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
1682 ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
1683 ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
1684 ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1685 ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
1686 ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1687
1688 write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1689 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer ); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1690 write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1691
1692 u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1693
1694 //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
1695 //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
1696 //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
1697 //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
1698
1699 write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1700
1701 write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1702
1703 #ifdef TODO
1704 // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
1705 if( pStaQos->CurrentQosMode > QOS_DISABLE )
1706 { // QoS mode.
1707 if(pStaQos->QBssWirelessMode == WirelessMode)
1708 {
1709 // Follow AC Parameters of the QBSS.
1710 for(eACI = 0; eACI < AC_MAX; eACI++)
1711 {
1712 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
1713 }
1714 }
1715 else
1716 {
1717 // Follow Default WMM AC Parameters.
1718 bFollowLegacySetting = 1;
1719 }
1720 }
1721 else
1722 #endif
1723 { // Legacy 802.11.
1724 bFollowLegacySetting = 1;
1725
1726 }
1727
1728 // this setting is copied from rtl8187B. xiong-2006-11-13
1729 if(bFollowLegacySetting)
1730 {
1731
1732
1733 //
1734 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
1735 // 2005.12.01, by rcnjko.
1736 //
1737 AcParam.longData = 0;
1738 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
1739 AcParam.f.AciAifsn.f.ACM = 0;
1740 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
1741 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
1742 AcParam.f.TXOPLimit = 0;
1743
1744 //lzm reserved 080826
1745 #if 1
1746 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
1747 if( ieee->current_network.Turbo_Enable == 1 )
1748 AcParam.f.TXOPLimit = 0x01FF;
1749 // For 87SE with Intel 4965 Ad-Hoc mode have poor throughput (19MB)
1750 if (ieee->iw_mode == IW_MODE_ADHOC)
1751 AcParam.f.TXOPLimit = 0x0020;
1752 #endif
1753
1754 for(eACI = 0; eACI < AC_MAX; eACI++)
1755 {
1756 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
1757 {
1758 PAC_PARAM pAcParam = (PAC_PARAM)(&AcParam);
1759 AC_CODING eACI;
1760 u8 u1bAIFS;
1761 u32 u4bAcParam;
1762
1763 // Retrive paramters to udpate.
1764 eACI = pAcParam->f.AciAifsn.f.ACI;
1765 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
1766 u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
1767 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
1768 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
1769 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
1770
1771 switch(eACI)
1772 {
1773 case AC1_BK:
1774 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
1775 break;
1776
1777 case AC0_BE:
1778 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
1779 break;
1780
1781 case AC2_VI:
1782 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
1783 break;
1784
1785 case AC3_VO:
1786 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
1787 break;
1788
1789 default:
1790 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
1791 break;
1792 }
1793
1794 // Cehck ACM bit.
1795 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
1796 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
1797 {
1798 PACI_AIFSN pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
1799 AC_CODING eACI = pAciAifsn->f.ACI;
1800
1801 //modified Joseph
1802 //for 8187B AsynIORead issue
1803 #ifdef TODO
1804 u8 AcmCtrl = pHalData->AcmControl;
1805 #else
1806 u8 AcmCtrl = 0;
1807 #endif
1808 if( pAciAifsn->f.ACM )
1809 { // ACM bit is 1.
1810 switch(eACI)
1811 {
1812 case AC0_BE:
1813 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN); // or 0x21
1814 break;
1815
1816 case AC2_VI:
1817 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN); // or 0x42
1818 break;
1819
1820 case AC3_VO:
1821 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN); // or 0x84
1822 break;
1823
1824 default:
1825 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
1826 break;
1827 }
1828 }
1829 else
1830 { // ACM bit is 0.
1831 switch(eACI)
1832 {
1833 case AC0_BE:
1834 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xDE
1835 break;
1836
1837 case AC2_VI:
1838 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xBD
1839 break;
1840
1841 case AC3_VO:
1842 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0x7B
1843 break;
1844
1845 default:
1846 break;
1847 }
1848 }
1849
1850 //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1851
1852 #ifdef TO_DO
1853 pHalData->AcmControl = AcmCtrl;
1854 #endif
1855 //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
1856 write_nic_byte(dev, ACM_CONTROL, 0);
1857 }
1858 }
1859 }
1860
1861
1862 }
1863 }
1864
1865 void
1866 ActSetWirelessMode8185(
1867 struct net_device *dev,
1868 u8 btWirelessMode
1869 )
1870 {
1871 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1872 struct ieee80211_device *ieee = priv->ieee80211;
1873 //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
1874 u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1875
1876 if( (btWirelessMode & btSupportedWirelessMode) == 0 )
1877 { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
1878 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
1879 btWirelessMode, btSupportedWirelessMode);
1880 return;
1881 }
1882
1883 // 1. Assign wireless mode to swtich if necessary.
1884 if (btWirelessMode == WIRELESS_MODE_AUTO)
1885 {
1886 if((btSupportedWirelessMode & WIRELESS_MODE_A))
1887 {
1888 btWirelessMode = WIRELESS_MODE_A;
1889 }
1890 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
1891 {
1892 btWirelessMode = WIRELESS_MODE_G;
1893 }
1894 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
1895 {
1896 btWirelessMode = WIRELESS_MODE_B;
1897 }
1898 else
1899 {
1900 DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
1901 btSupportedWirelessMode);
1902 btWirelessMode = WIRELESS_MODE_B;
1903 }
1904 }
1905
1906
1907 // 2. Swtich band: RF or BB specific actions,
1908 // for example, refresh tables in omc8255, or change initial gain if necessary.
1909 switch(priv->rf_chip)
1910 {
1911 case RF_ZEBRA2:
1912 case RF_ZEBRA4:
1913 {
1914 // Nothing to do for Zebra to switch band.
1915 // Update current wireless mode if we swtich to specified band successfully.
1916 ieee->mode = (WIRELESS_MODE)btWirelessMode;
1917 }
1918 break;
1919
1920 default:
1921 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
1922 break;
1923 }
1924
1925 // 3. Change related setting.
1926 if( ieee->mode == WIRELESS_MODE_A ){
1927 DMESG("WIRELESS_MODE_A\n");
1928 }
1929 else if( ieee->mode == WIRELESS_MODE_B ){
1930 DMESG("WIRELESS_MODE_B\n");
1931 }
1932 else if( ieee->mode == WIRELESS_MODE_G ){
1933 DMESG("WIRELESS_MODE_G\n");
1934 }
1935
1936 ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
1937 }
1938
1939 void rtl8185b_irq_enable(struct net_device *dev)
1940 {
1941 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1942
1943 priv->irq_enabled = 1;
1944 write_nic_dword(dev, IMR, priv->IntrMask);
1945 }
1946 //by amy for power save
1947 void
1948 DrvIFIndicateDisassociation(
1949 struct net_device *dev,
1950 u16 reason
1951 )
1952 {
1953 //printk("==> DrvIFIndicateDisassociation()\n");
1954
1955 // nothing is needed after disassociation request.
1956
1957 //printk("<== DrvIFIndicateDisassociation()\n");
1958 }
1959 void
1960 MgntDisconnectIBSS(
1961 struct net_device *dev
1962 )
1963 {
1964 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1965 u8 i;
1966
1967 //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
1968
1969 DrvIFIndicateDisassociation(dev, unspec_reason);
1970
1971 // PlatformZeroMemory( pMgntInfo->Bssid, 6 );
1972 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x55;
1973
1974 priv->ieee80211->state = IEEE80211_NOLINK;
1975
1976 //Stop Beacon.
1977
1978 // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
1979 // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
1980 // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
1981
1982 // Disable Beacon Queue Own bit, suggested by jong
1983 // Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
1984 ieee80211_stop_send_beacons(priv->ieee80211);
1985
1986 priv->ieee80211->link_change(dev);
1987 notify_wx_assoc_event(priv->ieee80211);
1988
1989 // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
1990
1991 // MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
1992
1993 }
1994 void
1995 MlmeDisassociateRequest(
1996 struct net_device *dev,
1997 u8* asSta,
1998 u8 asRsn
1999 )
2000 {
2001 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2002 u8 i;
2003
2004 SendDisassociation(priv->ieee80211, asSta, asRsn );
2005
2006 if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
2007 //ShuChen TODO: change media status.
2008 //ShuChen TODO: What to do when disassociate.
2009 DrvIFIndicateDisassociation(dev, unspec_reason);
2010
2011
2012 // pMgntInfo->AsocTimestamp = 0;
2013 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22;
2014 // pMgntInfo->mBrates.Length = 0;
2015 // Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2016
2017 ieee80211_disassociate(priv->ieee80211);
2018
2019
2020 }
2021
2022 }
2023
2024 void
2025 MgntDisconnectAP(
2026 struct net_device *dev,
2027 u8 asRsn
2028 )
2029 {
2030 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2031
2032 //
2033 // Commented out by rcnjko, 2005.01.27:
2034 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2035 //
2036 // //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2037 // SecClearAllKeys(Adapter);
2038
2039 // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2040 #ifdef TODO
2041 if( pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2042 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) ) // In CCKM mode will Clear key
2043 {
2044 SecClearAllKeys(Adapter);
2045 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2046 }
2047 #endif
2048 // 2004.10.11, by rcnjko.
2049 //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2050 MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2051
2052 priv->ieee80211->state = IEEE80211_NOLINK;
2053 // pMgntInfo->AsocTimestamp = 0;
2054 }
2055 bool
2056 MgntDisconnect(
2057 struct net_device *dev,
2058 u8 asRsn
2059 )
2060 {
2061 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2062 //
2063 // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2064 //
2065 #ifdef TODO
2066 if(pMgntInfo->mPss != eAwake)
2067 {
2068 //
2069 // Using AwkaeTimer to prevent mismatch ps state.
2070 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2071 //
2072 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2073 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2074 }
2075 #endif
2076
2077 // Indication of disassociation event.
2078 //DrvIFIndicateDisassociation(Adapter, asRsn);
2079 if(IS_DOT11D_ENABLE(priv->ieee80211))
2080 Dot11d_Reset(priv->ieee80211);
2081 // In adhoc mode, update beacon frame.
2082 if( priv->ieee80211->state == IEEE80211_LINKED )
2083 {
2084 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2085 {
2086 // RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2087 //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2088 MgntDisconnectIBSS(dev);
2089 }
2090 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2091 {
2092 // We clear key here instead of MgntDisconnectAP() because that
2093 // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2094 // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2095 // used to handle disassociation related things to AP, e.g. send Disassoc
2096 // frame to AP. 2005.01.27, by rcnjko.
2097 // SecClearAllKeys(Adapter);
2098
2099 // RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2100 //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2101 MgntDisconnectAP(dev, asRsn);
2102 }
2103
2104 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2105 // MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2106 }
2107
2108 return true;
2109 }
2110 //
2111 // Description:
2112 // Chang RF Power State.
2113 // Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2114 //
2115 // Assumption:
2116 // PASSIVE LEVEL.
2117 //
2118 bool
2119 SetRFPowerState(
2120 struct net_device *dev,
2121 RT_RF_POWER_STATE eRFPowerState
2122 )
2123 {
2124 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2125 bool bResult = false;
2126
2127 // printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2128 if(eRFPowerState == priv->eRFPowerState)
2129 {
2130 // printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2131 return bResult;
2132 }
2133
2134 switch(priv->rf_chip)
2135 {
2136 case RF_ZEBRA2:
2137 case RF_ZEBRA4:
2138 bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2139 break;
2140
2141 default:
2142 printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2143 break;;
2144 }
2145 // printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2146
2147 return bResult;
2148 }
2149 void
2150 HalEnableRx8185Dummy(
2151 struct net_device *dev
2152 )
2153 {
2154 }
2155 void
2156 HalDisableRx8185Dummy(
2157 struct net_device *dev
2158 )
2159 {
2160 }
2161
2162 bool
2163 MgntActSet_RF_State(
2164 struct net_device *dev,
2165 RT_RF_POWER_STATE StateToSet,
2166 u32 ChangeSource
2167 )
2168 {
2169 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2170 bool bActionAllowed = false;
2171 bool bConnectBySSID = false;
2172 RT_RF_POWER_STATE rtState;
2173 u16 RFWaitCounter = 0;
2174 unsigned long flag;
2175 // printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2176 //
2177 // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2178 // Only one thread can change the RF state at one time, and others should wait to be executed.
2179 //
2180 #if 1
2181 while(true)
2182 {
2183 // down(&priv->rf_state);
2184 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2185 if(priv->RFChangeInProgress)
2186 {
2187 // printk("====================>haha111111111\n");
2188 // up(&priv->rf_state);
2189 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2190 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2191 // Set RF after the previous action is done.
2192 while(priv->RFChangeInProgress)
2193 {
2194 RFWaitCounter ++;
2195 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2196 udelay(1000); // 1 ms
2197
2198 // Wait too long, return FALSE to avoid to be stuck here.
2199 if(RFWaitCounter > 1000) // 1sec
2200 {
2201 // RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2202 printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2203 // TODO: Reset RF state?
2204 return false;
2205 }
2206 }
2207 }
2208 else
2209 {
2210 // printk("========================>haha2\n");
2211 priv->RFChangeInProgress = true;
2212 // up(&priv->rf_state);
2213 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2214 break;
2215 }
2216 }
2217 #endif
2218 rtState = priv->eRFPowerState;
2219
2220
2221 switch(StateToSet)
2222 {
2223 case eRfOn:
2224 //
2225 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2226 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2227 //
2228 priv->RfOffReason &= (~ChangeSource);
2229
2230 if(! priv->RfOffReason)
2231 {
2232 priv->RfOffReason = 0;
2233 bActionAllowed = true;
2234
2235 if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2236 {
2237 bConnectBySSID = true;
2238 }
2239 }
2240 else
2241 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2242 ;
2243 break;
2244
2245 case eRfOff:
2246 // 070125, rcnjko: we always keep connected in AP mode.
2247
2248 if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2249 {
2250 //
2251 // 060808, Annie:
2252 // Disconnect to current BSS when radio off. Asked by QuanTa.
2253 //
2254
2255 //
2256 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2257 // because we do NOT need to set ssid to dummy ones.
2258 // Revised by Roger, 2007.12.04.
2259 //
2260 MgntDisconnect( dev, disas_lv_ss );
2261
2262 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2263 // 2007.05.28, by shien chang.
2264 // PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2265 // pMgntInfo->NumBssDesc = 0;
2266 // PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2267 // pMgntInfo->NumBssDesc4Query = 0;
2268 }
2269
2270
2271
2272 priv->RfOffReason |= ChangeSource;
2273 bActionAllowed = true;
2274 break;
2275
2276 case eRfSleep:
2277 priv->RfOffReason |= ChangeSource;
2278 bActionAllowed = true;
2279 break;
2280
2281 default:
2282 break;
2283 }
2284
2285 if(bActionAllowed)
2286 {
2287 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2288 // Config HW to the specified mode.
2289 // printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2290 SetRFPowerState(dev, StateToSet);
2291
2292 // Turn on RF.
2293 if(StateToSet == eRfOn)
2294 {
2295 HalEnableRx8185Dummy(dev);
2296 if(bConnectBySSID)
2297 {
2298 // by amy not supported
2299 // MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2300 }
2301 }
2302 // Turn off RF.
2303 else if(StateToSet == eRfOff)
2304 {
2305 HalDisableRx8185Dummy(dev);
2306 }
2307 }
2308 else
2309 {
2310 // printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2311 }
2312
2313 // Release RF spinlock
2314 // down(&priv->rf_state);
2315 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2316 priv->RFChangeInProgress = false;
2317 // up(&priv->rf_state);
2318 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2319 // printk("<===MgntActSet_RF_State()\n");
2320 return bActionAllowed;
2321 }
2322 void
2323 InactivePowerSave(
2324 struct net_device *dev
2325 )
2326 {
2327 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2328 //u8 index = 0;
2329
2330 //
2331 // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2332 // is really scheduled.
2333 // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2334 // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2335 // blocks the IPS procedure of switching RF.
2336 // By Bruce, 2007-12-25.
2337 //
2338 priv->bSwRfProcessing = true;
2339
2340 MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2341
2342 //
2343 // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2344 //
2345
2346 priv->bSwRfProcessing = false;
2347 }
2348
2349 //
2350 // Description:
2351 // Enter the inactive power save mode. RF will be off
2352 // 2007.08.17, by shien chang.
2353 //
2354 void
2355 IPSEnter(
2356 struct net_device *dev
2357 )
2358 {
2359 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2360 RT_RF_POWER_STATE rtState;
2361 //printk("==============================>enter IPS\n");
2362 if (priv->bInactivePs)
2363 {
2364 rtState = priv->eRFPowerState;
2365
2366 //
2367 // Added by Bruce, 2007-12-25.
2368 // Do not enter IPS in the following conditions:
2369 // (1) RF is already OFF or Sleep
2370 // (2) bSwRfProcessing (indicates the IPS is still under going)
2371 // (3) Connectted (only disconnected can trigger IPS)
2372 // (4) IBSS (send Beacon)
2373 // (5) AP mode (send Beacon)
2374 //
2375 if (rtState == eRfOn && !priv->bSwRfProcessing
2376 && (priv->ieee80211->state != IEEE80211_LINKED ))
2377 {
2378 // printk("IPSEnter(): Turn off RF.\n");
2379 priv->eInactivePowerState = eRfOff;
2380 InactivePowerSave(dev);
2381 }
2382 }
2383 // printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2384 }
2385 void
2386 IPSLeave(
2387 struct net_device *dev
2388 )
2389 {
2390 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2391 RT_RF_POWER_STATE rtState;
2392 //printk("===================================>leave IPS\n");
2393 if (priv->bInactivePs)
2394 {
2395 rtState = priv->eRFPowerState;
2396 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2397 {
2398 // printk("IPSLeave(): Turn on RF.\n");
2399 priv->eInactivePowerState = eRfOn;
2400 InactivePowerSave(dev);
2401 }
2402 }
2403 // printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2404 }
2405 //by amy for power save
2406 void rtl8185b_adapter_start(struct net_device *dev)
2407 {
2408 struct r8180_priv *priv = ieee80211_priv(dev);
2409 struct ieee80211_device *ieee = priv->ieee80211;
2410
2411 u8 SupportedWirelessMode;
2412 u8 InitWirelessMode;
2413 u8 bInvalidWirelessMode = 0;
2414 //int i;
2415 u8 tmpu8;
2416 //u8 u1tmp,u2tmp;
2417 u8 btCR9346;
2418 u8 TmpU1b;
2419 u8 btPSR;
2420
2421 //rtl8180_rtx_disable(dev);
2422 //{by amy 080312
2423 write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2424 //by amy 080312}
2425 rtl8180_reset(dev);
2426
2427 priv->dma_poll_mask = 0;
2428 priv->dma_poll_stop_mask = 0;
2429
2430 //rtl8180_beacon_tx_disable(dev);
2431
2432 HwConfigureRTL8185(dev);
2433
2434 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2435 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2436
2437 write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); // default network type to 'No Link'
2438
2439 //write_nic_byte(dev, BRSR, 0x0); // Set BRSR= 1M
2440
2441 write_nic_word(dev, BcnItv, 100);
2442 write_nic_word(dev, AtimWnd, 2);
2443
2444 //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2445 PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2446
2447 write_nic_byte(dev, WPA_CONFIG, 0);
2448
2449 MacConfig_85BASIC(dev);
2450
2451 // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2452 // BT_DEMO_BOARD type
2453 PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2454 //by amy
2455 //#ifdef CONFIG_RTL818X_S
2456 // for jong required
2457 // PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2458 //#endif
2459 //by amy
2460 //BT_QA_BOARD
2461 //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2462
2463 //-----------------------------------------------------------------------------
2464 // Set up PHY related.
2465 //-----------------------------------------------------------------------------
2466 // Enable Config3.PARAM_En to revise AnaaParm.
2467 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
2468 //by amy
2469 tmpu8 = read_nic_byte(dev, CONFIG3);
2470 write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2471 //by amy
2472 // Turn on Analog power.
2473 // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2474 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2475 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2476 //by amy
2477 write_nic_word(dev, ANAPARAM3, 0x0010);
2478 //by amy
2479
2480 write_nic_byte(dev, CONFIG3, tmpu8);
2481 write_nic_byte(dev, CR9346, 0x00);
2482 //{by amy 080312 for led
2483 // enable EEM0 and EEM1 in 9346CR
2484 btCR9346 = read_nic_byte(dev, CR9346);
2485 write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
2486
2487 // B cut use LED1 to control HW RF on/off
2488 TmpU1b = read_nic_byte(dev, CONFIG5);
2489 TmpU1b = TmpU1b & ~BIT3;
2490 write_nic_byte(dev,CONFIG5, TmpU1b);
2491
2492 // disable EEM0 and EEM1 in 9346CR
2493 btCR9346 &= ~(0xC0);
2494 write_nic_byte(dev, CR9346, btCR9346);
2495
2496 //Enable Led (suggested by Jong)
2497 // B-cut RF Radio on/off 5e[3]=0
2498 btPSR = read_nic_byte(dev, PSR);
2499 write_nic_byte(dev, PSR, (btPSR | BIT3));
2500 //by amy 080312 for led}
2501 // setup initial timing for RFE.
2502 write_nic_word(dev, RFPinsOutput, 0x0480);
2503 SetOutputEnableOfRfPins(dev);
2504 write_nic_word(dev, RFPinsSelect, 0x2488);
2505
2506 // PHY config.
2507 PhyConfig8185(dev);
2508
2509 // We assume RegWirelessMode has already been initialized before,
2510 // however, we has to validate the wireless mode here and provide a reasonble
2511 // initialized value if necessary. 2005.01.13, by rcnjko.
2512 SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2513 if( (ieee->mode != WIRELESS_MODE_B) &&
2514 (ieee->mode != WIRELESS_MODE_G) &&
2515 (ieee->mode != WIRELESS_MODE_A) &&
2516 (ieee->mode != WIRELESS_MODE_AUTO))
2517 { // It should be one of B, G, A, or AUTO.
2518 bInvalidWirelessMode = 1;
2519 }
2520 else
2521 { // One of B, G, A, or AUTO.
2522 // Check if the wireless mode is supported by RF.
2523 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
2524 (ieee->mode & SupportedWirelessMode) == 0 )
2525 {
2526 bInvalidWirelessMode = 1;
2527 }
2528 }
2529
2530 if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
2531 { // Auto or other invalid value.
2532 // Assigne a wireless mode to initialize.
2533 if((SupportedWirelessMode & WIRELESS_MODE_A))
2534 {
2535 InitWirelessMode = WIRELESS_MODE_A;
2536 }
2537 else if((SupportedWirelessMode & WIRELESS_MODE_G))
2538 {
2539 InitWirelessMode = WIRELESS_MODE_G;
2540 }
2541 else if((SupportedWirelessMode & WIRELESS_MODE_B))
2542 {
2543 InitWirelessMode = WIRELESS_MODE_B;
2544 }
2545 else
2546 {
2547 DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
2548 SupportedWirelessMode);
2549 InitWirelessMode = WIRELESS_MODE_B;
2550 }
2551
2552 // Initialize RegWirelessMode if it is not a valid one.
2553 if(bInvalidWirelessMode)
2554 {
2555 ieee->mode = (WIRELESS_MODE)InitWirelessMode;
2556 }
2557 }
2558 else
2559 { // One of B, G, A.
2560 InitWirelessMode = ieee->mode;
2561 }
2562 //by amy for power save
2563 // printk("initialize ENABLE_IPS\n");
2564 priv->eRFPowerState = eRfOff;
2565 priv->RfOffReason = 0;
2566 {
2567 // u32 tmp2;
2568 // u32 tmp = jiffies;
2569 MgntActSet_RF_State(dev, eRfOn, 0);
2570 // tmp2 = jiffies;
2571 // printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2572 }
2573 // DrvIFIndicateCurrentPhyStatus(priv);
2574 //
2575 // If inactive power mode is enabled, disable rf while in disconnected state.
2576 // 2007.07.16, by shien chang.
2577 //
2578 if (priv->bInactivePs)
2579 {
2580 // u32 tmp2;
2581 // u32 tmp = jiffies;
2582 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
2583 // tmp2 = jiffies;
2584 // printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2585
2586 }
2587 // IPSEnter(dev);
2588 //by amy for power save
2589 #ifdef TODO
2590 // Turn off RF if necessary. 2005.08.23, by rcnjko.
2591 // We shall turn off RF after setting CMDR, otherwise,
2592 // RF will be turnned on after we enable MAC Tx/Rx.
2593 if(Adapter->MgntInfo.RegRfOff == TRUE)
2594 {
2595 SetRFPowerState8185(Adapter, RF_OFF);
2596 }
2597 else
2598 {
2599 SetRFPowerState8185(Adapter, RF_ON);
2600 }
2601 #endif
2602
2603 /* //these is equal with above TODO.
2604 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
2605 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
2606 RF_WriteReg(dev, 0x4, 0x9FF);
2607 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2608 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2609 write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
2610 write_nic_byte(dev, CR9346, 0x00);
2611 */
2612
2613 ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
2614
2615 //-----------------------------------------------------------------------------
2616
2617 rtl8185b_irq_enable(dev);
2618
2619 netif_start_queue(dev);
2620
2621 }
2622
2623
2624 void rtl8185b_rx_enable(struct net_device *dev)
2625 {
2626 u8 cmd;
2627 //u32 rxconf;
2628 /* for now we accept data, management & ctl frame*/
2629 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2630
2631 if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
2632
2633 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
2634 dev->flags & IFF_PROMISC){
2635 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
2636 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
2637 }
2638
2639 /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2640 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2641 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2642 }*/
2643
2644 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2645 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
2646 }
2647
2648 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
2649 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
2650
2651 write_nic_dword(dev, RCR, priv->ReceiveConfig);
2652
2653 fix_rx_fifo(dev);
2654
2655 #ifdef DEBUG_RX
2656 DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
2657 #endif
2658 cmd=read_nic_byte(dev,CMD);
2659 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
2660
2661 }
2662
2663 void rtl8185b_tx_enable(struct net_device *dev)
2664 {
2665 u8 cmd;
2666 //u8 tx_agc_ctl;
2667 u8 byte;
2668 //u32 txconf;
2669 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2670
2671 write_nic_dword(dev, TCR, priv->TransmitConfig);
2672 byte = read_nic_byte(dev, MSR);
2673 byte |= MSR_LINK_ENEDCA;
2674 write_nic_byte(dev, MSR, byte);
2675
2676 fix_tx_fifo(dev);
2677
2678 #ifdef DEBUG_TX
2679 DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
2680 #endif
2681
2682 cmd=read_nic_byte(dev,CMD);
2683 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
2684
2685 //write_nic_dword(dev,TX_CONF,txconf);
2686
2687
2688 /*
2689 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2690 write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
2691 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
2692 */
2693 }
2694
2695
Linux MOXA ART SoC ARM port