drivers/usb/host/pci-quirks.c

   1 /*
   2  * This file contains code to reset and initialize USB host controllers.
   3  * Some of it includes work-arounds for PCI hardware and BIOS quirks.
   4  * It may need to run early during booting -- before USB would normally
   5  * initialize -- to ensure that Linux doesn't use any legacy modes.
   6  *
   7  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
   8  *  (and others)
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/acpi.h>
  17 #include "pci-quirks.h"
  18 #include "xhci-ext-caps.h"
  19
  20
  21 #define UHCI_USBLEGSUP          0xc0            /* legacy support */
  22 #define UHCI_USBCMD             0               /* command register */
  23 #define UHCI_USBINTR            4               /* interrupt register */
  24 #define UHCI_USBLEGSUP_RWC      0x8f00          /* the R/WC bits */
  25 #define UHCI_USBLEGSUP_RO       0x5040          /* R/O and reserved bits */
  26 #define UHCI_USBCMD_RUN         0x0001          /* RUN/STOP bit */
  27 #define UHCI_USBCMD_HCRESET     0x0002          /* Host Controller reset */
  28 #define UHCI_USBCMD_EGSM        0x0008          /* Global Suspend Mode */
  29 #define UHCI_USBCMD_CONFIGURE   0x0040          /* Config Flag */
  30 #define UHCI_USBINTR_RESUME     0x0002          /* Resume interrupt enable */
  31
  32 #define OHCI_CONTROL            0x04
  33 #define OHCI_CMDSTATUS          0x08
  34 #define OHCI_INTRSTATUS         0x0c
  35 #define OHCI_INTRENABLE         0x10
  36 #define OHCI_INTRDISABLE        0x14
  37 #define OHCI_FMINTERVAL         0x34
  38 #define OHCI_HCR                (1 << 0)        /* host controller reset */
  39 #define OHCI_OCR                (1 << 3)        /* ownership change request */
  40 #define OHCI_CTRL_RWC           (1 << 9)        /* remote wakeup connected */
  41 #define OHCI_CTRL_IR            (1 << 8)        /* interrupt routing */
  42 #define OHCI_INTR_OC            (1 << 30)       /* ownership change */
  43
  44 #define EHCI_HCC_PARAMS         0x08            /* extended capabilities */
  45 #define EHCI_USBCMD             0               /* command register */
  46 #define EHCI_USBCMD_RUN         (1 << 0)        /* RUN/STOP bit */
  47 #define EHCI_USBSTS             4               /* status register */
  48 #define EHCI_USBSTS_HALTED      (1 << 12)       /* HCHalted bit */
  49 #define EHCI_USBINTR            8               /* interrupt register */
  50 #define EHCI_CONFIGFLAG         0x40            /* configured flag register */
  51 #define EHCI_USBLEGSUP          0               /* legacy support register */
  52 #define EHCI_USBLEGSUP_BIOS     (1 << 16)       /* BIOS semaphore */
  53 #define EHCI_USBLEGSUP_OS       (1 << 24)       /* OS semaphore */
  54 #define EHCI_USBLEGCTLSTS       4               /* legacy control/status */
  55 #define EHCI_USBLEGCTLSTS_SOOE  (1 << 13)       /* SMI on ownership change */
  56
  57
  58 /*
  59  * Make sure the controller is completely inactive, unable to
  60  * generate interrupts or do DMA.
  61  */
  62 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
  63 {
  64         /* Turn off PIRQ enable and SMI enable.  (This also turns off the
  65          * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
  66          */
  67         pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
  68
  69         /* Reset the HC - this will force us to get a
  70          * new notification of any already connected
  71          * ports due to the virtual disconnect that it
  72          * implies.
  73          */
  74         outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
  75         mb();
  76         udelay(5);
  77         if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
  78                 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
  79
  80         /* Just to be safe, disable interrupt requests and
  81          * make sure the controller is stopped.
  82          */
  83         outw(0, base + UHCI_USBINTR);
  84         outw(0, base + UHCI_USBCMD);
  85 }
  86 EXPORT_SYMBOL_GPL(uhci_reset_hc);
  87
  88 /*
  89  * Initialize a controller that was newly discovered or has just been
  90  * resumed.  In either case we can't be sure of its previous state.
  91  *
  92  * Returns: 1 if the controller was reset, 0 otherwise.
  93  */
  94 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
  95 {
  96         u16 legsup;
  97         unsigned int cmd, intr;
  98
  99         /*
 100          * When restarting a suspended controller, we expect all the
 101          * settings to be the same as we left them:
 102          *
 103          *      PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
 104          *      Controller is stopped and configured with EGSM set;
 105          *      No interrupts enabled except possibly Resume Detect.
 106          *
 107          * If any of these conditions are violated we do a complete reset.
 108          */
 109         pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
 110         if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
 111                 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
 112                                 __func__, legsup);
 113                 goto reset_needed;
 114         }
 115
 116         cmd = inw(base + UHCI_USBCMD);
 117         if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
 118                         !(cmd & UHCI_USBCMD_EGSM)) {
 119                 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
 120                                 __func__, cmd);
 121                 goto reset_needed;
 122         }
 123
 124         intr = inw(base + UHCI_USBINTR);
 125         if (intr & (~UHCI_USBINTR_RESUME)) {
 126                 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
 127                                 __func__, intr);
 128                 goto reset_needed;
 129         }
 130         return 0;
 131
 132 reset_needed:
 133         dev_dbg(&pdev->dev, "Performing full reset\n");
 134         uhci_reset_hc(pdev, base);
 135         return 1;
 136 }
 137 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
 138
 139 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
 140 {
 141         u16 cmd;
 142         return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
 143 }
 144
 145 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
 146 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
 147
 148 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
 149 {
 150         unsigned long base = 0;
 151         int i;
 152
 153         if (!pio_enabled(pdev))
 154                 return;
 155
 156         for (i = 0; i < PCI_ROM_RESOURCE; i++)
 157                 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
 158                         base = pci_resource_start(pdev, i);
 159                         break;
 160                 }
 161
 162         if (base)
 163                 uhci_check_and_reset_hc(pdev, base);
 164 }
 165
 166 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
 167 {
 168         return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
 169 }
 170
 171 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
 172 {
 173         void __iomem *base;
 174         u32 control;
 175
 176         if (!mmio_resource_enabled(pdev, 0))
 177                 return;
 178
 179         base = pci_ioremap_bar(pdev, 0);
 180         if (base == NULL)
 181                 return;
 182
 183         control = readl(base + OHCI_CONTROL);
 184
 185 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
 186 #ifdef __hppa__
 187 #define OHCI_CTRL_MASK          (OHCI_CTRL_RWC | OHCI_CTRL_IR)
 188 #else
 189 #define OHCI_CTRL_MASK          OHCI_CTRL_RWC
 190
 191         if (control & OHCI_CTRL_IR) {
 192                 int wait_time = 500; /* arbitrary; 5 seconds */
 193                 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
 194                 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
 195                 while (wait_time > 0 &&
 196                                 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
 197                         wait_time -= 10;
 198                         msleep(10);
 199                 }
 200                 if (wait_time <= 0)
 201                         dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
 202                                         " (BIOS bug?) %08x\n",
 203                                         readl(base + OHCI_CONTROL));
 204         }
 205 #endif
 206
 207         /* reset controller, preserving RWC (and possibly IR) */
 208         writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
 209         readl(base + OHCI_CONTROL);
 210
 211         /* Some NVIDIA controllers stop working if kept in RESET for too long */
 212         if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
 213                 u32 fminterval;
 214                 int cnt;
 215
 216                 /* drive reset for at least 50 ms (7.1.7.5) */
 217                 msleep(50);
 218
 219                 /* software reset of the controller, preserving HcFmInterval */
 220                 fminterval = readl(base + OHCI_FMINTERVAL);
 221                 writel(OHCI_HCR, base + OHCI_CMDSTATUS);
 222
 223                 /* reset requires max 10 us delay */
 224                 for (cnt = 30; cnt > 0; --cnt) {        /* ... allow extra time */
 225                         if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
 226                                 break;
 227                         udelay(1);
 228                 }
 229                 writel(fminterval, base + OHCI_FMINTERVAL);
 230
 231                 /* Now we're in the SUSPEND state with all devices reset
 232                  * and wakeups and interrupts disabled
 233                  */
 234         }
 235
 236         /*
 237          * disable interrupts
 238          */
 239         writel(~(u32)0, base + OHCI_INTRDISABLE);
 240         writel(~(u32)0, base + OHCI_INTRSTATUS);
 241
 242         iounmap(base);
 243 }
 244
 245 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
 246 {
 247         int wait_time, delta;
 248         void __iomem *base, *op_reg_base;
 249         u32     hcc_params, val;
 250         u8      offset, cap_length;
 251         int     count = 256/4;
 252         int     tried_handoff = 0;
 253
 254         if (!mmio_resource_enabled(pdev, 0))
 255                 return;
 256
 257         base = pci_ioremap_bar(pdev, 0);
 258         if (base == NULL)
 259                 return;
 260
 261         cap_length = readb(base);
 262         op_reg_base = base + cap_length;
 263
 264         /* EHCI 0.96 and later may have "extended capabilities"
 265          * spec section 5.1 explains the bios handoff, e.g. for
 266          * booting from USB disk or using a usb keyboard
 267          */
 268         hcc_params = readl(base + EHCI_HCC_PARAMS);
 269         offset = (hcc_params >> 8) & 0xff;
 270         while (offset && --count) {
 271                 u32             cap;
 272                 int             msec;
 273
 274                 pci_read_config_dword(pdev, offset, &cap);
 275                 switch (cap & 0xff) {
 276                 case 1:                 /* BIOS/SMM/... handoff support */
 277                         if ((cap & EHCI_USBLEGSUP_BIOS)) {
 278                                 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
 279
 280 #if 0
 281 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
 282  * but that seems dubious in general (the BIOS left it off intentionally)
 283  * and is known to prevent some systems from booting.  so we won't do this
 284  * unless maybe we can determine when we're on a system that needs SMI forced.
 285  */
 286                                 /* BIOS workaround (?): be sure the
 287                                  * pre-Linux code receives the SMI
 288                                  */
 289                                 pci_read_config_dword(pdev,
 290                                                 offset + EHCI_USBLEGCTLSTS,
 291                                                 &val);
 292                                 pci_write_config_dword(pdev,
 293                                                 offset + EHCI_USBLEGCTLSTS,
 294                                                 val | EHCI_USBLEGCTLSTS_SOOE);
 295 #endif
 296
 297                                 /* some systems get upset if this semaphore is
 298                                  * set for any other reason than forcing a BIOS
 299                                  * handoff..
 300                                  */
 301                                 pci_write_config_byte(pdev, offset + 3, 1);
 302                         }
 303
 304                         /* if boot firmware now owns EHCI, spin till
 305                          * it hands it over.
 306                          */
 307                         msec = 1000;
 308                         while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
 309                                 tried_handoff = 1;
 310                                 msleep(10);
 311                                 msec -= 10;
 312                                 pci_read_config_dword(pdev, offset, &cap);
 313                         }
 314
 315                         if (cap & EHCI_USBLEGSUP_BIOS) {
 316                                 /* well, possibly buggy BIOS... try to shut
 317                                  * it down, and hope nothing goes too wrong
 318                                  */
 319                                 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
 320                                                 " (BIOS bug?) %08x\n", cap);
 321                                 pci_write_config_byte(pdev, offset + 2, 0);
 322                         }
 323
 324                         /* just in case, always disable EHCI SMIs */
 325                         pci_write_config_dword(pdev,
 326                                         offset + EHCI_USBLEGCTLSTS,
 327                                         0);
 328
 329                         /* If the BIOS ever owned the controller then we
 330                          * can't expect any power sessions to remain intact.
 331                          */
 332                         if (tried_handoff)
 333                                 writel(0, op_reg_base + EHCI_CONFIGFLAG);
 334                         break;
 335                 case 0:                 /* illegal reserved capability */
 336                         cap = 0;
 337                         /* FALLTHROUGH */
 338                 default:
 339                         dev_warn(&pdev->dev, "EHCI: unrecognized capability "
 340                                         "%02x\n", cap & 0xff);
 341                         break;
 342                 }
 343                 offset = (cap >> 8) & 0xff;
 344         }
 345         if (!count)
 346                 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
 347
 348         /*
 349          * halt EHCI & disable its interrupts in any case
 350          */
 351         val = readl(op_reg_base + EHCI_USBSTS);
 352         if ((val & EHCI_USBSTS_HALTED) == 0) {
 353                 val = readl(op_reg_base + EHCI_USBCMD);
 354                 val &= ~EHCI_USBCMD_RUN;
 355                 writel(val, op_reg_base + EHCI_USBCMD);
 356
 357                 wait_time = 2000;
 358                 delta = 100;
 359                 do {
 360                         writel(0x3f, op_reg_base + EHCI_USBSTS);
 361                         udelay(delta);
 362                         wait_time -= delta;
 363                         val = readl(op_reg_base + EHCI_USBSTS);
 364                         if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
 365                                 break;
 366                         }
 367                 } while (wait_time > 0);
 368         }
 369         writel(0, op_reg_base + EHCI_USBINTR);
 370         writel(0x3f, op_reg_base + EHCI_USBSTS);
 371
 372         iounmap(base);
 373
 374         return;
 375 }
 376
 377 /*
 378  * handshake - spin reading a register until handshake completes
 379  * @ptr: address of hc register to be read
 380  * @mask: bits to look at in result of read
 381  * @done: value of those bits when handshake succeeds
 382  * @wait_usec: timeout in microseconds
 383  * @delay_usec: delay in microseconds to wait between polling
 384  *
 385  * Polls a register every delay_usec microseconds.
 386  * Returns 0 when the mask bits have the value done.
 387  * Returns -ETIMEDOUT if this condition is not true after
 388  * wait_usec microseconds have passed.
 389  */
 390 static int handshake(void __iomem *ptr, u32 mask, u32 done,
 391                 int wait_usec, int delay_usec)
 392 {
 393         u32     result;
 394
 395         do {
 396                 result = readl(ptr);
 397                 result &= mask;
 398                 if (result == done)
 399                         return 0;
 400                 udelay(delay_usec);
 401                 wait_usec -= delay_usec;
 402         } while (wait_usec > 0);
 403         return -ETIMEDOUT;
 404 }
 405
 406 /**
 407  * PCI Quirks for xHCI.
 408  *
 409  * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
 410  * It signals to the BIOS that the OS wants control of the host controller,
 411  * and then waits 5 seconds for the BIOS to hand over control.
 412  * If we timeout, assume the BIOS is broken and take control anyway.
 413  */
 414 static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
 415 {
 416         void __iomem *base;
 417         int ext_cap_offset;
 418         void __iomem *op_reg_base;
 419         u32 val;
 420         int timeout;
 421
 422         if (!mmio_resource_enabled(pdev, 0))
 423                 return;
 424
 425         base = ioremap_nocache(pci_resource_start(pdev, 0),
 426                                 pci_resource_len(pdev, 0));
 427         if (base == NULL)
 428                 return;
 429
 430         /*
 431          * Find the Legacy Support Capability register -
 432          * this is optional for xHCI host controllers.
 433          */
 434         ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
 435         do {
 436                 if (!ext_cap_offset)
 437                         /* We've reached the end of the extended capabilities */
 438                         goto hc_init;
 439                 val = readl(base + ext_cap_offset);
 440                 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
 441                         break;
 442                 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
 443         } while (1);
 444
 445         /* If the BIOS owns the HC, signal that the OS wants it, and wait */
 446         if (val & XHCI_HC_BIOS_OWNED) {
 447                 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
 448
 449                 /* Wait for 5 seconds with 10 microsecond polling interval */
 450                 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
 451                                 0, 5000, 10);
 452
 453                 /* Assume a buggy BIOS and take HC ownership anyway */
 454                 if (timeout) {
 455                         dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
 456                                         " (BIOS bug ?) %08x\n", val);
 457                         writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
 458                 }
 459         }
 460
 461         val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
 462         /* Mask off (turn off) any enabled SMIs */
 463         val &= XHCI_LEGACY_DISABLE_SMI;
 464         /* Mask all SMI events bits, RW1C */
 465         val |= XHCI_LEGACY_SMI_EVENTS;
 466         /* Disable any BIOS SMIs and clear all SMI events*/
 467         writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
 468
 469 hc_init:
 470         op_reg_base = base + XHCI_HC_LENGTH(readl(base));
 471
 472         /* Wait for the host controller to be ready before writing any
 473          * operational or runtime registers.  Wait 5 seconds and no more.
 474          */
 475         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
 476                         5000, 10);
 477         /* Assume a buggy HC and start HC initialization anyway */
 478         if (timeout) {
 479                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 480                 dev_warn(&pdev->dev,
 481                                 "xHCI HW not ready after 5 sec (HC bug?) "
 482                                 "status = 0x%x\n", val);
 483         }
 484
 485         /* Send the halt and disable interrupts command */
 486         val = readl(op_reg_base + XHCI_CMD_OFFSET);
 487         val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
 488         writel(val, op_reg_base + XHCI_CMD_OFFSET);
 489
 490         /* Wait for the HC to halt - poll every 125 usec (one microframe). */
 491         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
 492                         XHCI_MAX_HALT_USEC, 125);
 493         if (timeout) {
 494                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 495                 dev_warn(&pdev->dev,
 496                                 "xHCI HW did not halt within %d usec "
 497                                 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
 498         }
 499
 500         iounmap(base);
 501 }
 502
 503 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
 504 {
 505         /* Skip Netlogic mips SoC's internal PCI USB controller.
 506          * This device does not need/support EHCI/OHCI handoff
 507          */
 508         if (pdev->vendor == 0x184e)     /* vendor Netlogic */
 509                 return;
 510         if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
 511                         pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
 512                         pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
 513                         pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
 514                 return;
 515
 516         if (pci_enable_device(pdev) < 0) {
 517                 dev_warn(&pdev->dev, "Can't enable PCI device, "
 518                                 "BIOS handoff failed.\n");
 519                 return;
 520         }
 521         if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
 522                 quirk_usb_handoff_uhci(pdev);
 523         else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
 524                 quirk_usb_handoff_ohci(pdev);
 525         else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
 526                 quirk_usb_disable_ehci(pdev);
 527         else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
 528                 quirk_usb_handoff_xhci(pdev);
 529         pci_disable_device(pdev);
 530 }
 531 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);