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init from v2.6.32.60
[mach-moxart.git] / sound / pci / lx6464es / lx_core.c
blob2313a516fb62b6ac5a0f825e5c570ae37e427d2f
1 /* -*- linux-c -*- *
2 *
3 * ALSA driver for the digigram lx6464es interface
4 * low-level interface
5 *
6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
22 *
23 */
24
25 /* #define RMH_DEBUG 1 */
26
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30
31 #include "lx6464es.h"
32 #include "lx_core.h"
33
34 /* low-level register access */
35
36 static const unsigned long dsp_port_offsets[] = {
37 0,
38 0x400,
39 0x401,
40 0x402,
41 0x403,
42 0x404,
43 0x405,
44 0x406,
45 0x407,
46 0x408,
47 0x409,
48 0x40a,
49 0x40b,
50 0x40c,
51
52 0x410,
53 0x411,
54 0x412,
55 0x413,
56 0x414,
57 0x415,
58 0x416,
59
60 0x420,
61 0x430,
62 0x431,
63 0x432,
64 0x433,
65 0x434,
66 0x440
67 };
68
69 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port)
70 {
71 void __iomem *base_address = chip->port_dsp_bar;
72 return base_address + dsp_port_offsets[port]*4;
73 }
74
75 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port)
76 {
77 void __iomem *address = lx_dsp_register(chip, port);
78 return ioread32(address);
79 }
80
81 void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, u32 len)
82 {
83 u32 __iomem *address = lx_dsp_register(chip, port);
84 int i;
85
86 /* we cannot use memcpy_fromio */
87 for (i = 0; i != len; ++i)
88 data[i] = ioread32(address + i);
89 }
90
91
92 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data)
93 {
94 void __iomem *address = lx_dsp_register(chip, port);
95 iowrite32(data, address);
96 }
97
98 void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, const u32 *data,
99 u32 len)
100 {
101 u32 __iomem *address = lx_dsp_register(chip, port);
102 int i;
103
104 /* we cannot use memcpy_to */
105 for (i = 0; i != len; ++i)
106 iowrite32(data[i], address + i);
107 }
108
109
110 static const unsigned long plx_port_offsets[] = {
111 0x04,
112 0x40,
113 0x44,
114 0x48,
115 0x4c,
116 0x50,
117 0x54,
118 0x58,
119 0x5c,
120 0x64,
121 0x68,
122 0x6C
123 };
124
125 static void __iomem *lx_plx_register(struct lx6464es *chip, int port)
126 {
127 void __iomem *base_address = chip->port_plx_remapped;
128 return base_address + plx_port_offsets[port];
129 }
130
131 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port)
132 {
133 void __iomem *address = lx_plx_register(chip, port);
134 return ioread32(address);
135 }
136
137 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data)
138 {
139 void __iomem *address = lx_plx_register(chip, port);
140 iowrite32(data, address);
141 }
142
143 u32 lx_plx_mbox_read(struct lx6464es *chip, int mbox_nr)
144 {
145 int index;
146
147 switch (mbox_nr) {
148 case 1:
149 index = ePLX_MBOX1; break;
150 case 2:
151 index = ePLX_MBOX2; break;
152 case 3:
153 index = ePLX_MBOX3; break;
154 case 4:
155 index = ePLX_MBOX4; break;
156 case 5:
157 index = ePLX_MBOX5; break;
158 case 6:
159 index = ePLX_MBOX6; break;
160 case 7:
161 index = ePLX_MBOX7; break;
162 case 0: /* reserved for HF flags */
163 snd_BUG();
164 default:
165 return 0xdeadbeef;
166 }
167
168 return lx_plx_reg_read(chip, index);
169 }
170
171 int lx_plx_mbox_write(struct lx6464es *chip, int mbox_nr, u32 value)
172 {
173 int index = -1;
174
175 switch (mbox_nr) {
176 case 1:
177 index = ePLX_MBOX1; break;
178 case 3:
179 index = ePLX_MBOX3; break;
180 case 4:
181 index = ePLX_MBOX4; break;
182 case 5:
183 index = ePLX_MBOX5; break;
184 case 6:
185 index = ePLX_MBOX6; break;
186 case 7:
187 index = ePLX_MBOX7; break;
188 case 0: /* reserved for HF flags */
189 case 2: /* reserved for Pipe States
190 * the DSP keeps an image of it */
191 snd_BUG();
192 return -EBADRQC;
193 }
194
195 lx_plx_reg_write(chip, index, value);
196 return 0;
197 }
198
199
200 /* rmh */
201
202 #ifdef CONFIG_SND_DEBUG
203 #define CMD_NAME(a) a
204 #else
205 #define CMD_NAME(a) NULL
206 #endif
207
208 #define Reg_CSM_MR 0x00000002
209 #define Reg_CSM_MC 0x00000001
210
211 struct dsp_cmd_info {
212 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits
213 * word).*/
214 u16 dcCmdLength; /* Command length in words of 24 bits.*/
215 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for
216 * random. */
217 u16 dcStatusLength; /* Status length (if fixed).*/
218 char *dcOpName;
219 };
220
221 /*
222 Initialization and control data for the Microblaze interface
223 - OpCode:
224 the opcode field of the command set at the proper offset
225 - CmdLength
226 the number of command words
227 - StatusType
228 offset in the status registers: 0 means that the return value may be
229 different from 0, and must be read
230 - StatusLength
231 the number of status words (in addition to the return value)
232 */
233
234 static struct dsp_cmd_info dsp_commands[] =
235 {
236 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/
237 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") },
238 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/
239 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") },
240 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/
241 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") },
242 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/
243 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") },
244 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/
245 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") },
246 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/
247 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") },
248 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/
249 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") },
250 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/
251 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") },
252 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/
253 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") },
254 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/
255 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") },
256 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/
257 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") },
258 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/
259 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") },
260 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/
261 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") },
262 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/
263 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") },
264 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/
265 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") },
266 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/
267 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") },
268 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/
269 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") },
270 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/
271 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") },
272 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/
273 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") },
274 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/
275 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") },
276 };
277
278 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd)
279 {
280 snd_BUG_ON(cmd >= CMD_14_INVALID);
281
282 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp;
283 rmh->cmd_len = dsp_commands[cmd].dcCmdLength;
284 rmh->stat_len = dsp_commands[cmd].dcStatusLength;
285 rmh->dsp_stat = dsp_commands[cmd].dcStatusType;
286 rmh->cmd_idx = cmd;
287 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32));
288
289 #ifdef CONFIG_SND_DEBUG
290 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32));
291 #endif
292 #ifdef RMH_DEBUG
293 rmh->cmd_idx = cmd;
294 #endif
295 }
296
297 #ifdef RMH_DEBUG
298 #define LXRMH "lx6464es rmh: "
299 static void lx_message_dump(struct lx_rmh *rmh)
300 {
301 u8 idx = rmh->cmd_idx;
302 int i;
303
304 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName);
305
306 for (i = 0; i != rmh->cmd_len; ++i)
307 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]);
308
309 for (i = 0; i != rmh->stat_len; ++i)
310 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]);
311 snd_printk("\n");
312 }
313 #else
314 static inline void lx_message_dump(struct lx_rmh *rmh)
315 {}
316 #endif
317
318
319
320 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */
321 #define XILINX_TIMEOUT_MS 40
322 #define XILINX_POLL_NO_SLEEP 100
323 #define XILINX_POLL_ITERATIONS 150
324
325
326 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh)
327 {
328 u32 reg = ED_DSP_TIMED_OUT;
329 int dwloop;
330
331 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
332 snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg);
333 return -EBUSY;
334 }
335
336 /* write command */
337 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
338
339 /* MicoBlaze gogogo */
340 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
341
342 /* wait for device to answer */
343 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) {
344 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) {
345 if (rmh->dsp_stat == 0)
346 reg = lx_dsp_reg_read(chip, eReg_CRM1);
347 else
348 reg = 0;
349 goto polling_successful;
350 } else
351 udelay(1);
352 }
353 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send_atomic! "
354 "polling failed\n");
355
356 polling_successful:
357 if ((reg & ERROR_VALUE) == 0) {
358 /* read response */
359 if (rmh->stat_len) {
360 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
361 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
362 rmh->stat_len);
363 }
364 } else
365 snd_printk(LXP "rmh error: %08x\n", reg);
366
367 /* clear Reg_CSM_MR */
368 lx_dsp_reg_write(chip, eReg_CSM, 0);
369
370 switch (reg) {
371 case ED_DSP_TIMED_OUT:
372 snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n");
373 return -ETIMEDOUT;
374
375 case ED_DSP_CRASHED:
376 snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n");
377 return -EAGAIN;
378 }
379
380 lx_message_dump(rmh);
381
382 return reg;
383 }
384
385
386 /* low-level dsp access */
387 int __devinit lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version)
388 {
389 u16 ret;
390 unsigned long flags;
391
392 spin_lock_irqsave(&chip->msg_lock, flags);
393
394 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
395 ret = lx_message_send_atomic(chip, &chip->rmh);
396
397 *rdsp_version = chip->rmh.stat[1];
398 spin_unlock_irqrestore(&chip->msg_lock, flags);
399 return ret;
400 }
401
402 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq)
403 {
404 u16 ret = 0;
405 unsigned long flags;
406 u32 freq_raw = 0;
407 u32 freq = 0;
408 u32 frequency = 0;
409
410 spin_lock_irqsave(&chip->msg_lock, flags);
411
412 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
413 ret = lx_message_send_atomic(chip, &chip->rmh);
414
415 if (ret == 0) {
416 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET;
417 freq = freq_raw & XES_FREQ_COUNT8_MASK;
418
419 if ((freq < XES_FREQ_COUNT8_48_MAX) ||
420 (freq > XES_FREQ_COUNT8_44_MIN))
421 frequency = 0; /* unknown */
422 else if (freq >= XES_FREQ_COUNT8_44_MAX)
423 frequency = 44100;
424 else
425 frequency = 48000;
426 }
427
428 spin_unlock_irqrestore(&chip->msg_lock, flags);
429
430 *rfreq = frequency * chip->freq_ratio;
431
432 return ret;
433 }
434
435 int lx_dsp_get_mac(struct lx6464es *chip, u8 *mac_address)
436 {
437 u32 macmsb, maclsb;
438
439 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF;
440 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF;
441
442 /* todo: endianess handling */
443 mac_address[5] = ((u8 *)(&maclsb))[0];
444 mac_address[4] = ((u8 *)(&maclsb))[1];
445 mac_address[3] = ((u8 *)(&maclsb))[2];
446 mac_address[2] = ((u8 *)(&macmsb))[0];
447 mac_address[1] = ((u8 *)(&macmsb))[1];
448 mac_address[0] = ((u8 *)(&macmsb))[2];
449
450 return 0;
451 }
452
453
454 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran)
455 {
456 unsigned long flags;
457 int ret;
458
459 spin_lock_irqsave(&chip->msg_lock, flags);
460
461 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY);
462 chip->rmh.cmd[0] |= gran;
463
464 ret = lx_message_send_atomic(chip, &chip->rmh);
465 spin_unlock_irqrestore(&chip->msg_lock, flags);
466 return ret;
467 }
468
469 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data)
470 {
471 unsigned long flags;
472 int ret;
473
474 spin_lock_irqsave(&chip->msg_lock, flags);
475
476 lx_message_init(&chip->rmh, CMD_04_GET_EVENT);
477 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */
478
479 ret = lx_message_send_atomic(chip, &chip->rmh);
480
481 if (!ret)
482 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32));
483
484 spin_unlock_irqrestore(&chip->msg_lock, flags);
485 return ret;
486 }
487
488 #define CSES_TIMEOUT 100 /* microseconds */
489 #define CSES_CE 0x0001
490 #define CSES_BROADCAST 0x0002
491 #define CSES_UPDATE_LDSV 0x0004
492
493 int lx_dsp_es_check_pipeline(struct lx6464es *chip)
494 {
495 int i;
496
497 for (i = 0; i != CSES_TIMEOUT; ++i) {
498 /*
499 * le bit CSES_UPDATE_LDSV est à 1 dés que le macprog
500 * est pret. il re-passe à 0 lorsque le premier read a
501 * été fait. pour l'instant on retire le test car ce bit
502 * passe a 1 environ 200 à 400 ms aprés que le registre
503 * confES à été écrit (kick du xilinx ES).
504 *
505 * On ne teste que le bit CE.
506 * */
507
508 u32 cses = lx_dsp_reg_read(chip, eReg_CSES);
509
510 if ((cses & CSES_CE) == 0)
511 return 0;
512
513 udelay(1);
514 }
515
516 return -ETIMEDOUT;
517 }
518
519
520 #define PIPE_INFO_TO_CMD(capture, pipe) \
521 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
522
523
524
525 /* low-level pipe handling */
526 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
527 int channels)
528 {
529 int err;
530 unsigned long flags;
531
532 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
533
534 spin_lock_irqsave(&chip->msg_lock, flags);
535 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE);
536
537 chip->rmh.cmd[0] |= pipe_cmd;
538 chip->rmh.cmd[0] |= channels;
539
540 err = lx_message_send_atomic(chip, &chip->rmh);
541 spin_unlock_irqrestore(&chip->msg_lock, flags);
542
543 if (err != 0)
544 snd_printk(KERN_ERR "lx6464es: could not allocate pipe\n");
545
546 return err;
547 }
548
549 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture)
550 {
551 int err;
552 unsigned long flags;
553
554 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
555
556 spin_lock_irqsave(&chip->msg_lock, flags);
557 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE);
558
559 chip->rmh.cmd[0] |= pipe_cmd;
560
561 err = lx_message_send_atomic(chip, &chip->rmh);
562 spin_unlock_irqrestore(&chip->msg_lock, flags);
563
564 return err;
565 }
566
567 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
568 u32 *r_needed, u32 *r_freed, u32 *size_array)
569 {
570 int err;
571 unsigned long flags;
572
573 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
574
575 #ifdef CONFIG_SND_DEBUG
576 if (size_array)
577 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER);
578 #endif
579
580 *r_needed = 0;
581 *r_freed = 0;
582
583 spin_lock_irqsave(&chip->msg_lock, flags);
584 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS);
585
586 chip->rmh.cmd[0] |= pipe_cmd;
587
588 err = lx_message_send_atomic(chip, &chip->rmh);
589
590 if (!err) {
591 int i;
592 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
593 u32 stat = chip->rmh.stat[i];
594 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) {
595 /* finished */
596 *r_freed += 1;
597 if (size_array)
598 size_array[i] = stat & MASK_DATA_SIZE;
599 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET))
600 == 0)
601 /* free */
602 *r_needed += 1;
603 }
604
605 #if 0
606 snd_printdd(LXP "CMD_08_ASK_BUFFERS: needed %d, freed %d\n",
607 *r_needed, *r_freed);
608 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
609 for (i = 0; i != chip->rmh.stat_len; ++i)
610 snd_printdd(" stat[%d]: %x, %x\n", i,
611 chip->rmh.stat[i],
612 chip->rmh.stat[i] & MASK_DATA_SIZE);
613 }
614 #endif
615 }
616
617 spin_unlock_irqrestore(&chip->msg_lock, flags);
618 return err;
619 }
620
621
622 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture)
623 {
624 int err;
625 unsigned long flags;
626
627 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
628
629 spin_lock_irqsave(&chip->msg_lock, flags);
630 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE);
631
632 chip->rmh.cmd[0] |= pipe_cmd;
633
634 err = lx_message_send_atomic(chip, &chip->rmh);
635
636 spin_unlock_irqrestore(&chip->msg_lock, flags);
637 return err;
638 }
639
640 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture)
641 {
642 int err;
643 unsigned long flags;
644
645 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
646
647 spin_lock_irqsave(&chip->msg_lock, flags);
648 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE);
649
650 chip->rmh.cmd[0] |= pipe_cmd;
651
652 err = lx_message_send_atomic(chip, &chip->rmh);
653
654 spin_unlock_irqrestore(&chip->msg_lock, flags);
655 return err;
656 }
657
658
659 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture)
660 {
661 int err;
662
663 err = lx_pipe_wait_for_idle(chip, pipe, is_capture);
664 if (err < 0)
665 return err;
666
667 err = lx_pipe_toggle_state(chip, pipe, is_capture);
668
669 return err;
670 }
671
672 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture)
673 {
674 int err = 0;
675
676 err = lx_pipe_wait_for_start(chip, pipe, is_capture);
677 if (err < 0)
678 return err;
679
680 err = lx_pipe_toggle_state(chip, pipe, is_capture);
681
682 return err;
683 }
684
685
686 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
687 u64 *rsample_count)
688 {
689 int err;
690 unsigned long flags;
691
692 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
693
694 spin_lock_irqsave(&chip->msg_lock, flags);
695 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
696
697 chip->rmh.cmd[0] |= pipe_cmd;
698 chip->rmh.stat_len = 2; /* need all words here! */
699
700 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */
701
702 if (err != 0)
703 snd_printk(KERN_ERR
704 "lx6464es: could not query pipe's sample count\n");
705 else {
706 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
707 << 24) /* hi part */
708 + chip->rmh.stat[1]; /* lo part */
709 }
710
711 spin_unlock_irqrestore(&chip->msg_lock, flags);
712 return err;
713 }
714
715 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate)
716 {
717 int err;
718 unsigned long flags;
719
720 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
721
722 spin_lock_irqsave(&chip->msg_lock, flags);
723 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
724
725 chip->rmh.cmd[0] |= pipe_cmd;
726
727 err = lx_message_send_atomic(chip, &chip->rmh);
728
729 if (err != 0)
730 snd_printk(KERN_ERR "lx6464es: could not query pipe's state\n");
731 else
732 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F;
733
734 spin_unlock_irqrestore(&chip->msg_lock, flags);
735 return err;
736 }
737
738 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe,
739 int is_capture, u16 state)
740 {
741 int i;
742
743 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms:
744 * timeout 50 ms */
745 for (i = 0; i != 50; ++i) {
746 u16 current_state;
747 int err = lx_pipe_state(chip, pipe, is_capture, &current_state);
748
749 if (err < 0)
750 return err;
751
752 if (current_state == state)
753 return 0;
754
755 mdelay(1);
756 }
757
758 return -ETIMEDOUT;
759 }
760
761 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture)
762 {
763 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN);
764 }
765
766 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture)
767 {
768 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE);
769 }
770
771 /* low-level stream handling */
772 int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
773 int is_capture, enum stream_state_t state)
774 {
775 int err;
776 unsigned long flags;
777
778 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
779
780 spin_lock_irqsave(&chip->msg_lock, flags);
781 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE);
782
783 chip->rmh.cmd[0] |= pipe_cmd;
784 chip->rmh.cmd[0] |= state;
785
786 err = lx_message_send_atomic(chip, &chip->rmh);
787 spin_unlock_irqrestore(&chip->msg_lock, flags);
788
789 return err;
790 }
791
792 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
793 u32 pipe, int is_capture)
794 {
795 int err;
796 unsigned long flags;
797
798 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
799
800 u32 channels = runtime->channels;
801
802 if (runtime->channels != channels)
803 snd_printk(KERN_ERR LXP "channel count mismatch: %d vs %d",
804 runtime->channels, channels);
805
806 spin_lock_irqsave(&chip->msg_lock, flags);
807 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM);
808
809 chip->rmh.cmd[0] |= pipe_cmd;
810
811 if (runtime->sample_bits == 16)
812 /* 16 bit format */
813 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET);
814
815 if (snd_pcm_format_little_endian(runtime->format))
816 /* little endian/intel format */
817 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET);
818
819 chip->rmh.cmd[0] |= channels-1;
820
821 err = lx_message_send_atomic(chip, &chip->rmh);
822 spin_unlock_irqrestore(&chip->msg_lock, flags);
823
824 return err;
825 }
826
827 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
828 int *rstate)
829 {
830 int err;
831 unsigned long flags;
832
833 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
834
835 spin_lock_irqsave(&chip->msg_lock, flags);
836 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
837
838 chip->rmh.cmd[0] |= pipe_cmd;
839
840 err = lx_message_send_atomic(chip, &chip->rmh);
841
842 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE;
843
844 spin_unlock_irqrestore(&chip->msg_lock, flags);
845 return err;
846 }
847
848 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
849 u64 *r_bytepos)
850 {
851 int err;
852 unsigned long flags;
853
854 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
855
856 spin_lock_irqsave(&chip->msg_lock, flags);
857 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
858
859 chip->rmh.cmd[0] |= pipe_cmd;
860
861 err = lx_message_send_atomic(chip, &chip->rmh);
862
863 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
864 << 32) /* hi part */
865 + chip->rmh.stat[1]; /* lo part */
866
867 spin_unlock_irqrestore(&chip->msg_lock, flags);
868 return err;
869 }
870
871 /* low-level buffer handling */
872 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
873 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
874 u32 *r_buffer_index)
875 {
876 int err;
877 unsigned long flags;
878
879 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
880
881 spin_lock_irqsave(&chip->msg_lock, flags);
882 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER);
883
884 chip->rmh.cmd[0] |= pipe_cmd;
885 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */
886
887 /* todo: pause request, circular buffer */
888
889 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE;
890 chip->rmh.cmd[2] = buf_address_lo;
891
892 if (buf_address_hi) {
893 chip->rmh.cmd_len = 4;
894 chip->rmh.cmd[3] = buf_address_hi;
895 chip->rmh.cmd[0] |= BF_64BITS_ADR;
896 }
897
898 err = lx_message_send_atomic(chip, &chip->rmh);
899
900 if (err == 0) {
901 *r_buffer_index = chip->rmh.stat[0];
902 goto done;
903 }
904
905 if (err == EB_RBUFFERS_TABLE_OVERFLOW)
906 snd_printk(LXP "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n");
907
908 if (err == EB_INVALID_STREAM)
909 snd_printk(LXP "lx_buffer_give EB_INVALID_STREAM\n");
910
911 if (err == EB_CMD_REFUSED)
912 snd_printk(LXP "lx_buffer_give EB_CMD_REFUSED\n");
913
914 done:
915 spin_unlock_irqrestore(&chip->msg_lock, flags);
916 return err;
917 }
918
919 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
920 u32 *r_buffer_size)
921 {
922 int err;
923 unsigned long flags;
924
925 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
926
927 spin_lock_irqsave(&chip->msg_lock, flags);
928 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
929
930 chip->rmh.cmd[0] |= pipe_cmd;
931 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the
932 * microblaze will seek for it */
933
934 err = lx_message_send_atomic(chip, &chip->rmh);
935
936 if (err == 0)
937 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE;
938
939 spin_unlock_irqrestore(&chip->msg_lock, flags);
940 return err;
941 }
942
943 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
944 u32 buffer_index)
945 {
946 int err;
947 unsigned long flags;
948
949 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
950
951 spin_lock_irqsave(&chip->msg_lock, flags);
952 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
953
954 chip->rmh.cmd[0] |= pipe_cmd;
955 chip->rmh.cmd[0] |= buffer_index;
956
957 err = lx_message_send_atomic(chip, &chip->rmh);
958
959 spin_unlock_irqrestore(&chip->msg_lock, flags);
960 return err;
961 }
962
963
964 /* low-level gain/peak handling
965 *
966 * \todo: can we unmute capture/playback channels independently?
967 *
968 * */
969 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute)
970 {
971 int err;
972 unsigned long flags;
973
974 /* bit set to 1: channel muted */
975 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU;
976
977 spin_lock_irqsave(&chip->msg_lock, flags);
978 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE);
979
980 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0);
981
982 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */
983 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */
984
985 snd_printk("mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1],
986 chip->rmh.cmd[2]);
987
988 err = lx_message_send_atomic(chip, &chip->rmh);
989
990 spin_unlock_irqrestore(&chip->msg_lock, flags);
991 return err;
992 }
993
994 static u32 peak_map[] = {
995 0x00000109, /* -90.308dB */
996 0x0000083B, /* -72.247dB */
997 0x000020C4, /* -60.205dB */
998 0x00008273, /* -48.030dB */
999 0x00020756, /* -36.005dB */
1000 0x00040C37, /* -30.001dB */
1001 0x00081385, /* -24.002dB */
1002 0x00101D3F, /* -18.000dB */
1003 0x0016C310, /* -15.000dB */
1004 0x002026F2, /* -12.001dB */
1005 0x002D6A86, /* -9.000dB */
1006 0x004026E6, /* -6.004dB */
1007 0x005A9DF6, /* -3.000dB */
1008 0x0065AC8B, /* -2.000dB */
1009 0x00721481, /* -1.000dB */
1010 0x007FFFFF, /* FS */
1011 };
1012
1013 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
1014 u32 *r_levels)
1015 {
1016 int err = 0;
1017 unsigned long flags;
1018 int i;
1019 spin_lock_irqsave(&chip->msg_lock, flags);
1020
1021 for (i = 0; i < channels; i += 4) {
1022 u32 s0, s1, s2, s3;
1023
1024 lx_message_init(&chip->rmh, CMD_12_GET_PEAK);
1025 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i);
1026
1027 err = lx_message_send_atomic(chip, &chip->rmh);
1028
1029 if (err == 0) {
1030 s0 = peak_map[chip->rmh.stat[0] & 0x0F];
1031 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf];
1032 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf];
1033 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf];
1034 } else
1035 s0 = s1 = s2 = s3 = 0;
1036
1037 r_levels[0] = s0;
1038 r_levels[1] = s1;
1039 r_levels[2] = s2;
1040 r_levels[3] = s3;
1041
1042 r_levels += 4;
1043 }
1044
1045 spin_unlock_irqrestore(&chip->msg_lock, flags);
1046 return err;
1047 }
1048
1049 /* interrupt handling */
1050 #define PCX_IRQ_NONE 0
1051 #define IRQCS_ACTIVE_PCIDB 0x00002000L /* Bit nø 13 */
1052 #define IRQCS_ENABLE_PCIIRQ 0x00000100L /* Bit nø 08 */
1053 #define IRQCS_ENABLE_PCIDB 0x00000200L /* Bit nø 09 */
1054
1055 static u32 lx_interrupt_test_ack(struct lx6464es *chip)
1056 {
1057 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS);
1058
1059 /* Test if PCI Doorbell interrupt is active */
1060 if (irqcs & IRQCS_ACTIVE_PCIDB) {
1061 u32 temp;
1062 irqcs = PCX_IRQ_NONE;
1063
1064 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) {
1065 /* RAZ interrupt */
1066 irqcs |= temp;
1067 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp);
1068 }
1069
1070 return irqcs;
1071 }
1072 return PCX_IRQ_NONE;
1073 }
1074
1075 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc,
1076 int *r_async_pending, int *r_async_escmd)
1077 {
1078 u32 irq_async;
1079 u32 irqsrc = lx_interrupt_test_ack(chip);
1080
1081 if (irqsrc == PCX_IRQ_NONE)
1082 return 0;
1083
1084 *r_irqsrc = irqsrc;
1085
1086 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response
1087 * (set by xilinx) + EOB */
1088
1089 if (irq_async & MASK_SYS_STATUS_ESA) {
1090 irq_async &= ~MASK_SYS_STATUS_ESA;
1091 *r_async_escmd = 1;
1092 }
1093
1094 if (irq_async) {
1095 /* snd_printd("interrupt: async event pending\n"); */
1096 *r_async_pending = 1;
1097 }
1098
1099 return 1;
1100 }
1101
1102 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc,
1103 int *r_freq_changed,
1104 u64 *r_notified_in_pipe_mask,
1105 u64 *r_notified_out_pipe_mask)
1106 {
1107 int err;
1108 u32 stat[9]; /* answer from CMD_04_GET_EVENT */
1109
1110 /* On peut optimiser pour ne pas lire les evenements vides
1111 * les mots de réponse sont dans l'ordre suivant :
1112 * Stat[0] mot de status général
1113 * Stat[1] fin de buffer OUT pF
1114 * Stat[2] fin de buffer OUT pf
1115 * Stat[3] fin de buffer IN pF
1116 * Stat[4] fin de buffer IN pf
1117 * Stat[5] underrun poid fort
1118 * Stat[6] underrun poid faible
1119 * Stat[7] overrun poid fort
1120 * Stat[8] overrun poid faible
1121 * */
1122
1123 u64 orun_mask;
1124 u64 urun_mask;
1125 #if 0
1126 int has_underrun = (irqsrc & MASK_SYS_STATUS_URUN) ? 1 : 0;
1127 int has_overrun = (irqsrc & MASK_SYS_STATUS_ORUN) ? 1 : 0;
1128 #endif
1129 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0;
1130 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0;
1131
1132 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0;
1133
1134 err = lx_dsp_read_async_events(chip, stat);
1135 if (err < 0)
1136 return err;
1137
1138 if (eb_pending_in) {
1139 *r_notified_in_pipe_mask = ((u64)stat[3] << 32)
1140 + stat[4];
1141 snd_printdd(LXP "interrupt: EOBI pending %llx\n",
1142 *r_notified_in_pipe_mask);
1143 }
1144 if (eb_pending_out) {
1145 *r_notified_out_pipe_mask = ((u64)stat[1] << 32)
1146 + stat[2];
1147 snd_printdd(LXP "interrupt: EOBO pending %llx\n",
1148 *r_notified_out_pipe_mask);
1149 }
1150
1151 orun_mask = ((u64)stat[7] << 32) + stat[8];
1152 urun_mask = ((u64)stat[5] << 32) + stat[6];
1153
1154 /* todo: handle xrun notification */
1155
1156 return err;
1157 }
1158
1159 static int lx_interrupt_request_new_buffer(struct lx6464es *chip,
1160 struct lx_stream *lx_stream)
1161 {
1162 struct snd_pcm_substream *substream = lx_stream->stream;
1163 int is_capture = lx_stream->is_capture;
1164 int err;
1165 unsigned long flags;
1166
1167 const u32 channels = substream->runtime->channels;
1168 const u32 bytes_per_frame = channels * 3;
1169 const u32 period_size = substream->runtime->period_size;
1170 const u32 period_bytes = period_size * bytes_per_frame;
1171 const u32 pos = lx_stream->frame_pos;
1172 const u32 next_pos = ((pos+1) == substream->runtime->periods) ?
1173 0 : pos + 1;
1174
1175 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes;
1176 u32 buf_hi = 0;
1177 u32 buf_lo = 0;
1178 u32 buffer_index = 0;
1179
1180 u32 needed, freed;
1181 u32 size_array[MAX_STREAM_BUFFER];
1182
1183 snd_printdd("->lx_interrupt_request_new_buffer\n");
1184
1185 spin_lock_irqsave(&chip->lock, flags);
1186
1187 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array);
1188 snd_printdd(LXP "interrupt: needed %d, freed %d\n", needed, freed);
1189
1190 unpack_pointer(buf, &buf_lo, &buf_hi);
1191 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi,
1192 &buffer_index);
1193 snd_printdd(LXP "interrupt: gave buffer index %x on %p (%d bytes)\n",
1194 buffer_index, (void *)buf, period_bytes);
1195
1196 lx_stream->frame_pos = next_pos;
1197 spin_unlock_irqrestore(&chip->lock, flags);
1198
1199 return err;
1200 }
1201
1202 void lx_tasklet_playback(unsigned long data)
1203 {
1204 struct lx6464es *chip = (struct lx6464es *)data;
1205 struct lx_stream *lx_stream = &chip->playback_stream;
1206 int err;
1207
1208 snd_printdd("->lx_tasklet_playback\n");
1209
1210 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1211 if (err < 0)
1212 snd_printk(KERN_ERR LXP
1213 "cannot request new buffer for playback\n");
1214
1215 snd_pcm_period_elapsed(lx_stream->stream);
1216 }
1217
1218 void lx_tasklet_capture(unsigned long data)
1219 {
1220 struct lx6464es *chip = (struct lx6464es *)data;
1221 struct lx_stream *lx_stream = &chip->capture_stream;
1222 int err;
1223
1224 snd_printdd("->lx_tasklet_capture\n");
1225 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1226 if (err < 0)
1227 snd_printk(KERN_ERR LXP
1228 "cannot request new buffer for capture\n");
1229
1230 snd_pcm_period_elapsed(lx_stream->stream);
1231 }
1232
1233
1234
1235 static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip,
1236 u64 notified_in_pipe_mask,
1237 u64 notified_out_pipe_mask)
1238 {
1239 int err = 0;
1240
1241 if (notified_in_pipe_mask) {
1242 snd_printdd(LXP "requesting audio transfer for capture\n");
1243 tasklet_hi_schedule(&chip->tasklet_capture);
1244 }
1245
1246 if (notified_out_pipe_mask) {
1247 snd_printdd(LXP "requesting audio transfer for playback\n");
1248 tasklet_hi_schedule(&chip->tasklet_playback);
1249 }
1250
1251 return err;
1252 }
1253
1254
1255 irqreturn_t lx_interrupt(int irq, void *dev_id)
1256 {
1257 struct lx6464es *chip = dev_id;
1258 int async_pending, async_escmd;
1259 u32 irqsrc;
1260
1261 spin_lock(&chip->lock);
1262
1263 snd_printdd("**************************************************\n");
1264
1265 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) {
1266 spin_unlock(&chip->lock);
1267 snd_printdd("IRQ_NONE\n");
1268 return IRQ_NONE; /* this device did not cause the interrupt */
1269 }
1270
1271 if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1272 goto exit;
1273
1274 #if 0
1275 if (irqsrc & MASK_SYS_STATUS_EOBI)
1276 snd_printdd(LXP "interrupt: EOBI\n");
1277
1278 if (irqsrc & MASK_SYS_STATUS_EOBO)
1279 snd_printdd(LXP "interrupt: EOBO\n");
1280
1281 if (irqsrc & MASK_SYS_STATUS_URUN)
1282 snd_printdd(LXP "interrupt: URUN\n");
1283
1284 if (irqsrc & MASK_SYS_STATUS_ORUN)
1285 snd_printdd(LXP "interrupt: ORUN\n");
1286 #endif
1287
1288 if (async_pending) {
1289 u64 notified_in_pipe_mask = 0;
1290 u64 notified_out_pipe_mask = 0;
1291 int freq_changed;
1292 int err;
1293
1294 /* handle async events */
1295 err = lx_interrupt_handle_async_events(chip, irqsrc,
1296 &freq_changed,
1297 &notified_in_pipe_mask,
1298 &notified_out_pipe_mask);
1299 if (err)
1300 snd_printk(KERN_ERR LXP
1301 "error handling async events\n");
1302
1303 err = lx_interrupt_handle_audio_transfer(chip,
1304 notified_in_pipe_mask,
1305 notified_out_pipe_mask
1306 );
1307 if (err)
1308 snd_printk(KERN_ERR LXP
1309 "error during audio transfer\n");
1310 }
1311
1312 if (async_escmd) {
1313 #if 0
1314 /* backdoor for ethersound commands
1315 *
1316 * for now, we do not need this
1317 *
1318 * */
1319
1320 snd_printdd("lx6464es: interrupt requests escmd handling\n");
1321 #endif
1322 }
1323
1324 exit:
1325 spin_unlock(&chip->lock);
1326 return IRQ_HANDLED; /* this device caused the interrupt */
1327 }
1328
1329
1330 static void lx_irq_set(struct lx6464es *chip, int enable)
1331 {
1332 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS);
1333
1334 /* enable/disable interrupts
1335 *
1336 * Set the Doorbell and PCI interrupt enable bits
1337 *
1338 * */
1339 if (enable)
1340 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1341 else
1342 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1343 lx_plx_reg_write(chip, ePLX_IRQCS, reg);
1344 }
1345
1346 void lx_irq_enable(struct lx6464es *chip)
1347 {
1348 snd_printdd("->lx_irq_enable\n");
1349 lx_irq_set(chip, 1);
1350 }
1351
1352 void lx_irq_disable(struct lx6464es *chip)
1353 {
1354 snd_printdd("->lx_irq_disable\n");
1355 lx_irq_set(chip, 0);
1356 }
Linux MOXA ART SoC ARM port