[mascara-docs.git] / i386 / MIT / course / lectures / all / 6.828 / 2011 / readings / hardware / vgadoc / TRIDENT.TXT
| blob | 46f3a371bc186fcd73e5aafe6dc7cdf4d1d02563 |
1 Trident SuperVGA\r
2 \r
3 Trident TVGA8800BR 512k Only 128K banks.\r
4 TVGA8800CS 512k Has 64k banks and old/new mode\r
5 TVGA8900B 1MB\r
6 TVGA8900C 1MB\r
7 TVGA8900CL 2MB\r
8 TVGA8900D 2MB Same as 8900CL, but with a few bug corrected\r
9 (which?)\r
10 TVGA9000 Low component version\r
11 TVGA9000i Low component count. 15/16 bit DAC on chip\r
12 Clock generator on chip\r
13 9200CXr 2MB\r
14 TGUI9400CXi 2MB Clock & 24bit DAC onchip\r
15 TGUI9420DGi 2MB As 9400, but with Accelerator (BitBlt, Color Exp\r
16 Fills, Line draw and Linear Frame buffer)\r
17 TGUI9430 As 9420 + Hardware cursor\r
18 TGUI9440AGi 2MB As 9430, 16bit DAC interface and programmable\r
19 clock ??\r
20 TGUI9660XGi 64bit video memory path\r
21 TGUI9680 As 9660, but with video acc\r
22 \r
23 \r
24 LCD9100B Suppose these are LCD controllers, anyone seen them?\r
25 LCD9100\r
26 LX8200\r
27 \r
28 \r
29 Support chips:\r
30 \r
31 TCK9001 Clock chip for the 8900B.\r
32 Supplies: 25.175, 28.322, 44.9, 36, 57.272, 65, 50.35, 40 MHz\r
33 \r
34 TCK9002 Clock chip for the 8900C and later.\r
35 Supplies: 25.175, 28.322, 44.9, 36, 57.272, 65, 50.35, 40,\r
36 88, 98, 118.8, 108 MHz\r
37 \r
38 TCK9004 Clock chip for the 8900CL and later.\r
39 Supplies: 25.175, 28.322, 44.9, 36, 57.272, 65, 50.35, 40,\r
40 88, 98, 118.8, 108, 72, 77, 80, 75 MHz\r
41 \r
42 TKD8001 "ColorSync" truecolor RAMDAC\r
43 \r
44 \r
45 What are the specs for all the new chips?? (CX,CXi,CL,CXr,GUI...)\r
46 The Trident 8800 chips have a problem with 256 color modes,\r
47 as they always double the pixels output in 256 color mode.\r
48 Thus a 640x400 256 color mode (5Ch) actually uses a 1280x400\r
49 frame, requiring at least a multi sync monitor.\r
50 This problem is fixed on the 8900.\r
51 \r
52 Apparently Trident BIOS version 3.xx or later on a 8900C will support Sierra\r
53 HiColor DACs (SC11483 or SC11487). No check is made for the existence of such\r
54 a DAC, the mode is just set as if it was present, resulting in 1024x480,\r
55 1280x480 and 1600x600 256color modes if an ordinary DAC is installed.\r
56 \r
57 \r
58 100h W(R/W?): Microchannel ID low/high\r
59 bit 0-15 Card ID bit 0-15\r
60 \r
61 3C3h (R/W): Microchannel Video Subsystem Enable Register:\r
62 bit 0 Enable Microchannel VGA if set\r
63 \r
64 3C4h index 0Bh (R): Chip Version\r
65 bit 0-7 Chip ID\r
66 1 = TR 8800BR\r
67 2 = TR 8800CS\r
68 3 = TR 8900B\r
69 4 = TVGA8900C\r
70 13h = TVGA8900C\r
71 23h = TR 9000\r
72 33h = TVGA8900CL, TVGA8900D or TVGA 9000C\r
73 43h = TVGA9000i\r
74 53h = TR 9200CXr\r
75 63h = TLCD9100B\r
76 73h = TGUI9420\r
77 83h = TR LX8200\r
78 93h = TGUI9400CXi\r
79 A3h = TLCD9320\r
80 C3h = TGUI9420DGi\r
81 D3h = TGUI9660XGi\r
82 E3h = TGUI9440AGi\r
83 F3h = TGUI9430 One source says 9420 ??\r
84 The 63h, 73h, 83h, A3h and F3h entries are still in doubt.\r
85 \r
86 Note: Writing to index Bh selects old mode registers.\r
87 Reading from index Bh selects new mode registers.\r
88 Note: Writing to this register in order to force old mode registers\r
89 should be done with two 8bit writes, not one 16bit write.\r
90 \r
91 3C4h index 0Ch (R/W): Power Up Mode Register 1\r
92 bit 0 Fast Decode if set, Slow if clear\r
93 1 (9000 & LCD9100) If clear 0 Wait states,\r
94 if set bit 6 determines number of wait states.\r
95 4 If set enable post port at 3C3h, at 46E8h if clear\r
96 5 (8900C) If set enables access to upper 512KB in non-paged modes\r
97 Must be clear in text and CGA modes.\r
98 (9000 & LCD9100) If set uses 2 DRAMs, 4 if clear\r
99 6 (9000 & LCD9100) If bit 1 is clear this bit determines the number\r
100 of wait states. If set 2 Wait states, 1 if clear.\r
101 5-6 (88xx and 89xx) 0=256K chip, 1 = 2 DRAMs, 2 = 4 DRAMs, 3 = 8 DRAMs.\r
102 7 If set VRAM bus setting is 16, 8 if clear\r
103 Note: This register can only be changed if New Mode Control 1 (3C4h index 0Eh)\r
104 bit 7 is set\r
105 \r
106 3C4h index 0Dh (R/W): Old Mode Control 2\r
107 bit 0-2 Emulation mode\r
108 0=VGA, 3=EGA, 5=CGA,MDA,Hercules\r
109 4 Enable Paging mode if set. If set the CRTC offset (3d4h index 13h)\r
110 should be multiplied by 2, and the Display Start Address (3d4h index\r
111 0Ch & 0Dh + 1Eh bit 5 and 3C4h Old Mode index 0Eh bit 0) is in units\r
112 of 8 bytes rather than 4 (256 color modes only).\r
113 5 DRAM clock enabled if set.\r
114 \r
115 3C4h index 0Dh (R/W): New Mode Control 2 (not 8800BR)\r
116 bit 0 Clock Select bit 2. Bits 0-1 are in 3CCh bits 2-3.\r
117 Clock table:\r
118 0: 25.1 75 1: 28.322 2: 44.9 3: 36\r
119 4: 57.272 5: 65 6: 50.35 7: 40\r
120 8: 88 9: 98 10: 118.8 11: 108\r
121 12: 72 13: 77 14: 80 15: 75\r
122 For the 8800 and 8900B only the first 8 clocks are available.\r
123 For the 9000i line 3 is: 8: 25.175, 9: 28.322, 10: 62.3, 11: 44.9\r
124 1-2 Divide pixel clock by: 0=1, 1=2, 2=4, 3=1.5\r
125 6 (9xxx) Clock Select bit 3. See bit 0\r
126 Note: The old/new Mode Control 1/2 registers are selected by\r
127 reading and writing the Chip version register (index Bh).\r
128 \r
129 3C4h index 0Eh (R/W): Old Mode Control 1\r
130 bit 0 (8900 Only) CRTC Address bit 17. Apparently this determines in which\r
131 part of memory the display is, as the display can not cross this\r
132 line, but can be on either side. Note that in Paged Mode (3C4h Old\r
133 Mode index 0Dh bit 4 is set) this bit has no effect as 17 bits can\r
134 span the entire 1MB range.\r
135 1-2 128kb Bank number (0-3)\r
136 3 16 bit video interface if set\r
137 4 (8900C, CL, CXr, GUI9420) Clock Select bit 3.\r
138 See New mode 3C4h index Dh bit 0.\r
139 \r
140 3C4h index 0Eh (R/W): New Mode Control 1 (not 8800BR)\r
141 bit 0-3 64k Bank nbr. When writing to this field XOR with 02h, when reading\r
142 from this field no XOR is needed. This is used for Trident detection.\r
143 In planar modes bits 0 and 2 form a two bit field.\r
144 4-6 Reserved\r
145 7 Must be set to update index 0Ch ???\r
146 Note: The old/new Mode Control 1/2 registers are selected by\r
147 reading and writing the Chip version register (index Bh).\r
148 \r
149 3C4h index Fh (R/W): Power-up Mode 2\r
150 bit 0-3 Switch settings\r
151 4 Bus type\r
152 5 If set I/O address are at 3xxh, else at 2xxh.\r
153 6 Enable ON-Card ROM if set\r
154 7 16 bit ROM access enabled if set\r
155 \r
156 3CEh index 0Eh (R/W): New Source Address Register (8900CL/D,9200 +)\r
157 bit 0-3 Bank register. If 3CEh index Fh bit 2 is clear and bit 0 is set this\r
158 is the read bank and 3C4h index Eh the write register. Note that bit\r
159 1 is inverted like 3C4h index Eh bit 1.\r
160 \r
161 3CEh index 0Fh (R/W): Miscellaneous Extended Functions (8900CL/D,9200 +)\r
162 bit 0 DUAL. If set selects dual bank mode with separate read and write\r
163 bank registers. If bit 2 is set 3D9h is the read bank and 3D8h the\r
164 write bank, if bit 2 is clear 3CEh index Eh is the read bank and 3C4h\r
165 index Eh the write bank\r
166 3D8h is the combined read/write bank. Only active if bit 2 is set.\r
167 1 When set the packed pixel modes (256 or more colors) uses bits 0-1 of\r
168 the PEL panning register (3C0h index 13h) for single pixel horizontal\r
169 scrolling rather than bits 1-2 (as Standard VGA).\r
170 2 ENALTP. Set to use the alternative banking registers at 3D8h/3D9h,\r
171 clear to use the old banking registers.\r
172 ?? Must be set when 3C4h index Ch bit 5 is set ??\r
173 3 If set character clocks are 16pixels wide rather than 8\r
174 \r
175 3d4h index 1Eh (R/W): Module Testing Register\r
176 bit 2 Vertical interlace if set\r
177 In interlaced modes the CRTC offset (3d4h index 13h) is the number of\r
178 bytes in TWO scanlines (NOT true for the 9440AGi!).\r
179 Note that in interlaced modes the line doubling caused by index 9 bits\r
180 0-4,7 is unlikely to work, as the (even,odd) linepair is repeated\r
181 rather than each individual line causing stripes.\r
182 3 If set Load fonts from Bottom, from top if clear\r
183 4 If set the display wraps back to line 0 when the line counter reaches\r
184 512.\r
185 5 CRTC Display Start Address bit 16. Bits 0-15 are in 3d4h index Ch,Dh\r
186 7 (not 88xx) Host address bit 16. If clear bit 5 has no effect.\r
187 This does not affect 3C4h Old Mode index 0Eh bit 0.\r
188 \r
189 3d4h index 1Fh (R/W): Software Programming Register\r
190 bit 0-1 (8800, 8900, 9000) Memory size 0=256k, 1=512k, 2=768k, 3=1M.\r
191 0-2 (8900CL, 9200CXr, 94xx, 9660) Memory size 0=256k, 1=512k,\r
192 2=768k, 3=1M, 4=256k, 5=512k, 6=768k, 7=2M.\r
193 4-6 (9420DGi) Monitor Type.\r
194 (9430,9440,9660) Monitor Type.\r
195 Note: This register set by software\r
196 Everex 8800 based cards have different layout, see below\r
197 \r
198 \r
199 3d4h index 1Fh (R/W): Scratch Register (Everex 8800 Cards)\r
200 bit 0 Paged memory mode in effect\r
201 1 Memory size 0=256k, 1=512k\r
202 2 Analog monitor attached\r
203 3 44.9 MHz oscillator present\r
204 Note: This register is set by software.\r
205 \r
206 3d4h index 21h (R/W): Configurable Linear Addressing Register (94xx)\r
207 Bit 0-3 LAWB0-3. Bits 20-23 of the Linear Aperture address\r
208 4 LAWS. If set the aperture is 2Mbytes, if clear 1MB.\r
209 5 ENLA. Set to enable Linear aperture.\r
210 6-7 Linear Aperture Address bits 24-25\r
211 \r
212 3d4h index 22h (R): CPU Latch Read Back\r
213 bit 0-7 Data Latch value for current read plane.\r
214 \r
215 3d4h index 23h (R/W):\r
216 bit 0-5 ??\r
217 \r
218 3d4h index 24h (R): Attribute State Read Back\r
219 bit 0-6 Reserved\r
220 7 Attribute Controller State\r
221 If set the next write to 3C0h will go to the data\r
222 register, if clear to the index register.\r
223 \r
224 3d4h index 26h (R): Attribute Index Read Back\r
225 bit 0-7 Attribute Index Register value\r
226 \r
227 3d4h index 27h (R/W): (8900CL/D +)\r
228 bit 0-1 Display Start Address bit 17-18. Bit 16 is in index 1Eh bit 5.\r
229 \r
230 3d4h index 28h (R/W):\r
231 bit 0-7 ??\r
232 \r
233 3d4h index 29h (R/W): (8900CL/D +)\r
234 bit 0 Connected to the RS2 input on the DAC ?.\r
235 1 ??\r
236 4 CRTC offset bit 8 ??\r
237 \r
238 3d4h index 2Ah (R/W):\r
239 bit 6 ??\r
240 \r
241 3d4h index 2Fh\r
242 bit 0-2 ?\r
243 4 ?\r
244 5-6 ?\r
245 \r
246 3d4h index 36h\r
247 bit 1 ?\r
248 7 ?\r
249 \r
250 3d4h index 38h (9440)\r
251 bit 2-3 Pixel depth?. 1: 15/16 bit modes, 2: 24bit modes, 0: all other modes\r
252 \r
253 3d4h index 40h W(R/W): (9440)\r
254 bit 0- Hardware Cursor *tal Location\r
255 \r
256 3d4h index 42h W(R/W): (9440)\r
257 bit 0- Hardware Cursor *tal Location\r
258 \r
259 3d4h index 44h W(R/W): (9440)\r
260 bit 0- Location of hardware cursor map in video memory in units of 1Kb\r
261 The hardware cursor map appears to be a 32x32x2 or 64x64x2 bitmap\r
262 organised in lines of 8 or 16 bytes, each having first 4 bytes\r
263 (32pixels) of AND data and then 4bytes XOR data (windows style).\r
264 The cursor displayed also depends on the cursor style (3d4h index 50h\r
265 bit 6).\r
266 AND: XOR: Style: Resulting screen:\r
267 0 0 0 Palette index 0 ?\r
268 1 0 0 Screen data (Transparent cursor)\r
269 0 1 0 Palette index 255 ?\r
270 1 1 0 Inverted screen (XOR cursor)\r
271 0 0 1 Screen data (Transparent cursor)\r
272 1 0 1 Palette index 0 ?\r
273 0 1 1 Screen data (Transparent cursor)\r
274 1 1 1 Palette index 255 ?\r
275 \r
276 3d4h index 46h (R/W): (9440)\r
277 bit 0-5 Cursor Horizontal hotspot. The position (in pixels from the left) of\r
278 the cursor hotspot within the 32x32 or 64x64 map. The displayed cursor\r
279 starts at the hotspot and ends 32/64 pixels from the left edge (i.e.\r
280 it does not wrap to the next line).\r
281 \r
282 3d4h index 47h (R/W): (9440)\r
283 bit 0-5\r
284 \r
285 3d4h index 50h (R/W): (9440)\r
286 bit 0 Set for 64x64 cursor, clear for 32x32 cursor\r
287 6 Clear for Cursor Style 0 (Windows?), set for Cursor Style 1 (X11?)\r
288 7 Enable hardware cursor if set\r
289 \r
290 3D8h (R/W): Destination Segment Register (8900CL/D,9200 +)\r
291 bit 0-4 Bank number in 64k units. If 3CEh index Fh bit 0 is set this is the\r
292 write bank, if not the combined read/write bank.\r
293 This register is only active if 3CEh index Fh bit 2 is set.\r
294 \r
295 3D9h (R/W): Source Segment Register (8900CL/D,9200 +)\r
296 bit 0-4 If 3CEh index Fh bit 0 is set this is the read bank.\r
297 This register is only active if 3CEh index Fh bit 2 is set.\r
298 \r
299 \r
300 Note: Ferraro (in Programmer's Guide to... 3rd edition) documents the\r
301 accelerator registers at 21xAh for the later Tridents, however so far\r
302 I have been unable to verify this.\r
303 \r
304 \r
305 43C6h W(R/W): Memory Clock (9440)\r
306 bit 0-15 Selects the memory clock. 2C6h = 50MHz, 307h = 58MHz, 87h = 64MHz\r
307 8Eh = 75MHz\r
308 Note: 3C4h index Eh (new) bits 1 & 7 must be set to update this register\r
309 \r
310 43C8h W(R/W): Video Clock (9440)\r
311 bit 0-15 Selects the video clock when 3C2/Ch bits 2-3 = 2.\r
312 Note: 3C4h index Eh (new) bits 1 & 7 must be set to update this register\r
313 \r
314 \r
315 46E8h (R): Video Subsystem Enable Register\r
316 bit 3 Enable VGA if set\r
317 \r
318 \r
319 The memory mapped registers appears to be mapped at BFF00h (how to enable\r
320 them ?). Probably only exists on the 9440 and later (9420?)\r
321 \r
322 M+20h (R?)\r
323 bit 5 Set when the graphics engine is busy?\r
324 6 Set if ? Data transfers should wait for it to clear?\r
325 7 Set when ?\r
326 \r
327 M+22h (R/W):\r
328 bit 0-? 9 for non-8bit modes, 4 for 8bit modes (<=1024), 8 for other modes\r
329 \r
330 M+24h (R/W):\r
331 bit 0-2 Write 1 to start a Blit, 4 to start a line draw ?\r
332 \r
333 M+27h (R/W):\r
334 bit 0-7 Raster op (=Bits 16-23 of the Windows ROP3).\r
335 \r
336 M+28h W(R/W):\r
337 bit 2 Set when using pattern ??\r
338 5 Set when using pattern ??\r
339 6 ??\r
340 8 If set the Blit moves bottom-to-top (decreasing address), if clear\r
341 it is top-to-bottom (increasing address).\r
342 9 If set the Blit moves right-to-left (decreasing address), if clear\r
343 it is left-to-right (increasing address).\r
344 14 Set for solid fills ??\r
345 \r
346 M+2Bh (R/W):\r
347 bit 0-2 Offset into the pattern ?\r
348 \r
349 M+2Ch W(R/W):\r
350 bit 0- Background color\r
351 \r
352 M+30h W(R/W):\r
353 bit 0- Foreground color\r
354 \r
355 M+34h W(R/W):\r
356 bit 0-15 Address of ?pattern? in units of 64bytes\r
357 \r
358 M+38h W(R/W):\r
359 bit 0- Destination starting X-coordinate\r
360 \r
361 M+3Ah W(R/W):\r
362 bit 0- Destination starting Y-coordinate\r
363 \r
364 M+3Ch W(R/W):\r
365 bit 0- Source starting X-coordinate\r
366 \r
367 M+3Eh W(R/W):\r
368 bit 0- Source starting Y-coordinate\r
369 \r
370 M+40h W(R/W):\r
371 bit 0- Width of the Blit area in pixels\r
372 \r
373 M+42h W(R/W):\r
374 bit 0- Height of the Blit area in scanlines\r
375 \r
376 M+44h\r
377 \r
378 M+46h W(R/W):\r
379 \r
380 Bank selection:\r
381 \r
382 Trident VGAs (except 8800BR) can operate in 2 different modes:\r
383 \r
384 Old Mode, with a 128k window to display memory at A000h - BFFFh\r
385 and New Mode, with a 64k window to display memory at A000h - AFFFh.\r
386 Old/New mode is selected by reading/writing the Chip Version Register\r
387 (3C4h index 0Bh).\r
388 Each mode has its own registers at 3C4h index 0Dh and 0Eh.\r
389 \r
390 \r
391 ID Trident VGA:\r
392 \r
393 wrinx($3C4,$B,0); {Force old_mode_registers}\r
394 chp:=inp($3C5); {Read chip ID and switch to new_mode_registers}\r
395 old:=rdinx($3C4,$E);\r
396 outp($3C5,0);\r
397 value:=inp($3C5) and $F;\r
398 outp($3C5,old);\r
399 \r
400 if value=2 then\r
401 begin\r
402 outp($3C5,old xor 2);\r
403 case chp of\r
404 1:Trident TR8800BR;\r
405 2:Trident TR8800CS;\r
406 3:Trident TR8900;\r
407 4,$13:Trident TR8900C;\r
408 $23:Trident TR9000;\r
409 $33:Trident TR8900CL or D;\r
410 $43:Trident TR9000i;\r
411 $53:Trident TR8900CXr\r
412 $63:Trident LCD9100B;\r
413 $83:Trident LX8200;\r
414 $93:Trident TVGA9400CXi\r
415 $A3:Trident LCD9320;\r
416 $73,$F3:Trident GUI9420;\r
417 end;\r
418 end\r
419 else if (chp=1) and testinx2($3C4,$E,6) then\r
420 Trident TVGA 8800BR {Haven't tested this yet}\r
421 \r
422 Video Modes:\r
423 50h T 80 30 16 (8x16)\r
424 51h T 80 43 16 (8x11)\r
425 52h T 80 60 16 (8x8)\r
426 53h T 132 25 16 (8x14)\r
427 54h T 132 30 16 (8x16)\r
428 55h T 132 43 16 (8x11)\r
429 56h T 132 60 16 (8x8)\r
430 57h T 132 25 16 (9x14)\r
431 58h T 132 30 16 (9x16)\r
432 59h T 132 43 16 (9x11)\r
433 5Ah T 132 60 16 (9x8)\r
434 5Bh G 800 600 16 PL4\r
435 5Ch G 640 400 256 P8\r
436 5Dh G 640 480 256 P8\r
437 5Eh G 800 600 256 P8 (Undocumented on 8800)\r
438 5Fh G 1024 768 16 PL4\r
439 60h G 1024 768 4 8900 Only\r
440 61h G 768 1024 16 PL4\r
441 62h G 1024 768 256 P8 8900 Only\r
442 63h G 1280 1024 16 PL4 Which chip/BIOS rev ?\r
443 64h G 1280 1024 256 P8 8900CL only\r
444 6Ah G 800 600 16 PL4 Newer boards\r
445 6Bh G 320 200 16m P24 TVGA9000i+\r
446 6Ch G 640 480 16m P24 8900CL+\r
447 6Dh G 800 600 16m P24 8900CL+\r
448 \r
449 70h G 512 480 32K P15 89xx with Sierra DAC\r
450 71h G 512 480 64K P16 89xx with Sierra DAC\r
451 74h G 640 480 32K P15 89xx with Sierra DAC\r
452 75h G 640 480 64K P16 89xx with Sierra DAC\r
453 76h G 800 600 32K P15 89xx with Sierra DAC\r
454 77h G 800 600 64K P16 89xx with Sierra DAC\r
455 78h G 1024 768 32K P15 8900CL with Sierra DAC\r
456 79h G 1024 768 64K P16 8900CL with Sierra DAC\r
457 7Eh G 320 200 32K P15 TVGA9000i\r
458 7Fh G 320 200 64K P16 TVGA9000i\r
459 \r
460 ZyMOS POACH51 modes:\r
461 \r
462 60h G 960 720 16 PL4\r
463 61h G 1280 640 16 PL4\r
464 62h G 512 512 256 P8\r
465 63h G 720 540 16 PL4\r
466 64h G 720 540 256 P8\r
467 6Ah G 800 600 16 PL4\r
468 \r
469 \r
470 Everex Viewpoint use Everex modes.\r
471 \r
472 \r
473 Note: The TVGA9000i has an on-chip DAC with 32k/64k capability.\r
474 The BIOS on the card I have (BIOS version D3.51) doesn't\r
475 seem to handle the Hi/True color modes correctly.\r
476 I have managed to get the 320x200 32k/64k modes working by programming\r
477 the DAC command register directly, but the 512x480 modes and the 320x200\r
478 16m mode still doesn't work\r
479 \r
480 \r
481 \r
482 Bios extensions:\r
483 \r
484 ----------1000-------------------------------\r
485 INT 10 - VIDEO - SET VIDEO MODE\r
486 AH = 00h\r
487 AL = mode number\r
488 Return: AH = Status of call: (Trident Super VGA Chips)\r
489 \r
490 Trident 8800 Trident 8900\r
491 00h Successful do\r
492 80h Fail. Wrong switch do\r
493 81h Insufficient Video do\r
494 Memory.\r
495 82h The 36MHz crystal Mode not supported\r
496 cannot support the mode\r
497 83h The 40MHz crystal Mode not supported\r
498 cannot support the mode.\r
499 84h The 44.9MHz crystal Mode not supported\r
500 cannot support the mode.\r
501 85h Dead or no crystal\r
502 86h Wrong CRTC base for dual screen\r
503 87h Text mode not supported\r
504 Note: The return code appears to be unsupported on some newer Trident\r
505 card, i.e. 9440AGi\r
506 ----------1012-BL11------------------------------\r
507 INT 10 - VIDEO - Trident BIOS - Get BIOS Info\r
508 AH = 12h\r
509 BL = 11h\r
510 Return: AL = 12h if function supported\r
511 ES:BP -> BIOS info structure:\r
512 Offset: Size: Description:\r
513 00h BYTE ??? (=0)\r
514 01h BYTE OEM Code (00h for original Trident)\r
515 02h WORD ID ?? (1073h for 8800BR, 1074h for 8800CS,\r
516 1090h for 8900C or 9000i\r
517 04h 8 BYTEs BIOS date ('mm/dd/yy')\r
518 0Ch WORD ???\r
519 0Eh 8 BYTEs BIOS Version (' C3-128 ', ' C3-129 ',\r
520 ' D3.51 ').\r
521 ----------1012-BL12------------------------------\r
522 INT 10 - VIDEO - Trident BIOS - GET VIDEO RAM SIZE\r
523 AH = 12h\r
524 BL = 12h\r
525 Return: AL = 12h if function supported\r
526 AH = number of 256K banks of RAM installed\r
527 ----------101200-BL14----------------------------\r
528 INT 10 - VIDEO - Trident LOCKFIFO - Get FIFO state\r
529 AX = 1200h\r
530 BH = 14h\r
531 Return: CX = FIFO state\r
532 Note: Implemented by the LOCKFIFO.COM utility\r
533 ----------101201-BL14----------------------------\r
534 INT 10 - VIDEO - Trident LOCKFIFO - Get FIFO state\r
535 AX = 1201h\r
536 BH = 14h\r
537 CX = FIFO state (0..FFh, FFh = disabled)\r
538 Note: Implemented by the LOCKFIFO.COM utility\r