i386/MIT/course/src/git.lab/kern/lapic.c

   1 // The local APIC manages internal (non-I/O) interrupts.
   2 // See Chapter 8 & Appendix C of Intel processor manual volume 3.
   3
   4 #include <inc/types.h>
   5 #include <inc/memlayout.h>
   6 #include <inc/trap.h>
   7 #include <inc/mmu.h>
   8 #include <inc/stdio.h>
   9 #include <inc/x86.h>
  10 #include <kern/pmap.h>
  11 #include <kern/cpu.h>
  12
  13 // Local APIC registers, divided by 4 for use as uint32_t[] indices.
  14 #define ID      (0x0020/4)   // ID
  15 #define VER     (0x0030/4)   // Version
  16 #define TPR     (0x0080/4)   // Task Priority
  17 #define EOI     (0x00B0/4)   // EOI
  18 #define SVR     (0x00F0/4)   // Spurious Interrupt Vector
  19         #define ENABLE     0x00000100   // Unit Enable
  20 #define ESR     (0x0280/4)   // Error Status
  21 #define ICRLO   (0x0300/4)   // Interrupt Command
  22         #define INIT       0x00000500   // INIT/RESET
  23         #define STARTUP    0x00000600   // Startup IPI
  24         #define DELIVS     0x00001000   // Delivery status
  25         #define ASSERT     0x00004000   // Assert interrupt (vs deassert)
  26         #define DEASSERT   0x00000000
  27         #define LEVEL      0x00008000   // Level triggered
  28         #define BCAST      0x00080000   // Send to all APICs, including self.
  29         #define OTHERS     0x000C0000   // Send to all APICs, excluding self.
  30         #define BUSY       0x00001000
  31         #define FIXED      0x00000000
  32 #define ICRHI   (0x0310/4)   // Interrupt Command [63:32]
  33 #define TIMER   (0x0320/4)   // Local Vector Table 0 (TIMER)
  34         #define X1         0x0000000B   // divide counts by 1
  35         #define PERIODIC   0x00020000   // Periodic
  36 #define PCINT   (0x0340/4)   // Performance Counter LVT
  37 #define LINT0   (0x0350/4)   // Local Vector Table 1 (LINT0)
  38 #define LINT1   (0x0360/4)   // Local Vector Table 2 (LINT1)
  39 #define ERROR   (0x0370/4)   // Local Vector Table 3 (ERROR)
  40         #define MASKED     0x00010000   // Interrupt masked
  41 #define TICR    (0x0380/4)   // Timer Initial Count
  42 #define TCCR    (0x0390/4)   // Timer Current Count
  43 #define TDCR    (0x03E0/4)   // Timer Divide Configuration
  44
  45 volatile uint32_t *lapic;  // Initialized in mp.c
  46
  47 static void
  48 lapicw(int index, int value)
  49 {
  50         lapic[index] = value;
  51         lapic[ID];  // wait for write to finish, by reading
  52 }
  53
  54 void
  55 lapic_init(void)
  56 {
  57         if (!lapic)
  58                 return;
  59
  60         // Enable local APIC; set spurious interrupt vector.
  61         lapicw(SVR, ENABLE | (IRQ_OFFSET + IRQ_SPURIOUS));
  62
  63         // The timer repeatedly counts down at bus frequency
  64         // from lapic[TICR] and then issues an interrupt.
  65         // If we cared more about precise timekeeping,
  66         // TICR would be calibrated using an external time source.
  67         lapicw(TDCR, X1);
  68         lapicw(TIMER, PERIODIC | (IRQ_OFFSET + IRQ_TIMER));
  69         lapicw(TICR, 10000000);
  70
  71         // Leave LINT0 of the BSP enabled so that it can get
  72         // interrupts from the 8259A chip.
  73         //
  74         // According to Intel MP Specification, the BIOS should initialize
  75         // BSP's local APIC in Virtual Wire Mode, in which 8259A's
  76         // INTR is virtually connected to BSP's LINTIN0. In this mode,
  77         // we do not need to program the IOAPIC.
  78         if (thiscpu != bootcpu)
  79                 lapicw(LINT0, MASKED);
  80
  81         // Disable NMI (LINT1) on all CPUs
  82         lapicw(LINT1, MASKED);
  83
  84         // Disable performance counter overflow interrupts
  85         // on machines that provide that interrupt entry.
  86         if (((lapic[VER]>>16) & 0xFF) >= 4)
  87                 lapicw(PCINT, MASKED);
  88
  89         // Map error interrupt to IRQ_ERROR.
  90         lapicw(ERROR, IRQ_OFFSET + IRQ_ERROR);
  91
  92         // Clear error status register (requires back-to-back writes).
  93         lapicw(ESR, 0);
  94         lapicw(ESR, 0);
  95
  96         // Ack any outstanding interrupts.
  97         lapicw(EOI, 0);
  98
  99         // Send an Init Level De-Assert to synchronize arbitration ID's.
 100         lapicw(ICRHI, 0);
 101         lapicw(ICRLO, BCAST | INIT | LEVEL);
 102         while(lapic[ICRLO] & DELIVS)
 103                 ;
 104
 105         // Enable interrupts on the APIC (but not on the processor).
 106         lapicw(TPR, 0);
 107 }
 108
 109 int
 110 cpunum(void)
 111 {
 112         if (lapic)
 113                 return lapic[ID] >> 24;
 114         return 0;
 115 }
 116
 117 // Acknowledge interrupt.
 118 void
 119 lapic_eoi(void)
 120 {
 121         if (lapic)
 122                 lapicw(EOI, 0);
 123 }
 124
 125 // Spin for a given number of microseconds.
 126 // On real hardware would want to tune this dynamically.
 127 static void
 128 microdelay(int us)
 129 {
 130 }
 131
 132 #define IO_RTC  0x70
 133
 134 // Start additional processor running entry code at addr.
 135 // See Appendix B of MultiProcessor Specification.
 136 void
 137 lapic_startap(uint8_t apicid, uint32_t addr)
 138 {
 139         int i;
 140         uint16_t *wrv;
 141
 142         // "The BSP must initialize CMOS shutdown code to 0AH
 143         // and the warm reset vector (DWORD based at 40:67) to point at
 144         // the AP startup code prior to the [universal startup algorithm]."
 145         outb(IO_RTC, 0xF);  // offset 0xF is shutdown code
 146         outb(IO_RTC+1, 0x0A);
 147         wrv = (uint16_t *)KADDR((0x40 << 4 | 0x67));  // Warm reset vector
 148         wrv[0] = 0;
 149         wrv[1] = addr >> 4;
 150
 151         // "Universal startup algorithm."
 152         // Send INIT (level-triggered) interrupt to reset other CPU.
 153         lapicw(ICRHI, apicid << 24);
 154         lapicw(ICRLO, INIT | LEVEL | ASSERT);
 155         microdelay(200);
 156         lapicw(ICRLO, INIT | LEVEL);
 157         microdelay(100);    // should be 10ms, but too slow in Bochs!
 158
 159         // Send startup IPI (twice!) to enter code.
 160         // Regular hardware is supposed to only accept a STARTUP
 161         // when it is in the halted state due to an INIT.  So the second
 162         // should be ignored, but it is part of the official Intel algorithm.
 163         // Bochs complains about the second one.  Too bad for Bochs.
 164         for (i = 0; i < 2; i++) {
 165                 lapicw(ICRHI, apicid << 24);
 166                 lapicw(ICRLO, STARTUP | (addr >> 12));
 167                 microdelay(200);
 168         }
 169 }
 170
 171 void
 172 lapic_ipi(int vector)
 173 {
 174         lapicw(ICRLO, OTHERS | FIXED | vector);
 175         while (lapic[ICRLO] & DELIVS)
 176                 ;
 177 }