amd64/bareMetalOS-0.5.2/pure64.boot0/docs/pure64-manual.html

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  11 <h1><b>Pure64 v0.4.9 - Manual</b></h1>
  12 <p>
  13 Pure64 currently works with the FAT16 file system. This file system was chosen because it is the most compatible between other OS's (Windows, Mac, Linux, etc).<br />
  14 Pure64 loads your software (OS kernel, Demo, etc) to memory address 0x0000000000100000 (The start of the second megabyte of RAM). Once your software is loaded into memory Pure64 will start to run it. At this point Pure64 is done and your software is in full control of the computer.
  15 </p>
  16
  17 <h2>System Requirements:</h2>
  18 A computer with a 64-bit compatible CPU<p />
  19 A FAT16 formatted hard drive<p />
  20 At least 2 MiB of RAM<p />
  21
  22 <h2>How to load Pure64:</h2>
  23 An example boot sector is available with Pure64. The only requirement is that Pure64 is loaded to 32-bit memory address 0x00008000.<p />
  24
  25 <h2>Memory Map:</h2>
  26 This memory map shows how physical memory looks after Pure64 is finished.
  27 <table border="1" cellpadding="2" cellspacing="0">
  28 <tr><th>Start Address</th><th>End Address</th><th>Size</th><th>Description</th></tr>
  29 <tr><td>0x0000000000000000</td><td>0x0000000000000FFF</td><td>4 KiB</td><td>IDT - 256 descriptors (each descriptor is 16 bytes)</td></tr>
  30 <tr><td>0x0000000000001000</td><td>0x0000000000001FFF</td><td>4 KiB</td><td>GDT - 256 descriptors (each descriptor is 16 bytes)</td></tr>
  31 <tr><td>0x0000000000002000</td><td>0x0000000000002FFF</td><td>4 KiB</td><td>PML4 - 512 entries, first entry points to PDP at 0x3000</td></tr>
  32 <tr><td>0x0000000000003000</td><td>0x0000000000003FFF</td><td>4 KiB</td><td>PDP - 512 enties</td></tr>
  33 <tr><td>0x0000000000004000</td><td>0x0000000000007FFF</td><td>16 KiB</td><td>Pure64 Data</td></tr>
  34 <tr><td>0x0000000000008000</td><td>0x000000000000FFFF</td><td>32 KiB</td><td>Pure64 - After the OS is loaded and running this memory is free again</td></tr>
  35 <tr><td>0x0000000000010000</td><td>0x000000000004FFFF</td><td>256 KiB</td><td>PD - Room to map 64 GiB</td></tr>
  36 <tr><td>0x0000000000050000</td><td>0x000000000009FFFF</td><td>320 KiB</td><td>Free</td></tr>
  37 <tr><td>0x00000000000A0000</td><td>0x00000000000FFFFF</td><td>384 KiB</td><td>ROM Area</td></tr>
  38 <tr><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>VGA mem at 0xA0000 (128 KiB) Color text starts at 0xB8000</td></tr>
  39 <tr><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>Video BIOS at 0xC0000 (64 KiB)</td></tr>
  40 <tr><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>Motherboard BIOS at F0000 (64 KiB)</td></tr>
  41 <tr><td>0x0000000000100000</td><td>0xFFFFFFFFFFFFFFFF</td><td>1+ MiB</td><td>Your software is loaded here</td></tr>
  42 </table>
  43
  44 When creating your Operating System or Demo you can use the sections marked free, however it is the safest to use memory above 1 MiB.<p />
  45
  46 <h2>Information table:</h2>
  47
  48 Pure64 stores an information table in memory that contains various pieces of data about the computer before it passes control over to the software you want it to load.
  49 The Pure64 information table is located at 0x0000000000005000 and ends at 0x00000000000057FF (2048 bytes).
  50
  51 <table border="1" cellpadding="2" cellspacing="0">
  52 <tr><th>Memory Address</th><th>Variable Size</th><th>Name</th><th>Description</th></tr>
  53 <tr><td>0x5000</td><td>64-bit</td><td>LAPIC</td><td>Local APIC address</td></tr>
  54 <tr><td>0x5008</td><td>64-bit</td><td>IOAPIC</td><td>IO APIC address</td></tr>
  55 <tr><td>0x5010</td><td>16-bit</td><td>CPUSPEED</td><td>Speed of the CPUs in MegaHertz (<a href="http://en.wikipedia.org/wiki/Mhz#Computing">MHz</a>)</td></tr>
  56 <tr><td>0x5012</td><td>16-bit</td><td>CORES_ACTIVE</td><td>The number of CPU cores that were activated in the system</td></tr>
  57 <tr><td>0x5014</td><td>16-bit</td><td>CORES_DETECT</td><td>The number of CPU cores that were detected in the system</td></tr>
  58 <tr><td>0x5016 - 0x501F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
  59 <tr><td>0x5020</td><td>16-bit</td><td>RAMAMOUNT</td><td>Amount of system RAM in Mebibytes (<a href="http://en.wikipedia.org/wiki/Mebibyte">MiB</a>)</td></tr>
  60 <tr><td>0x5022 - 0x502F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
  61 <tr><td>0x5030</td><td>8-bit</td><td>MBR</td><td>MBR Boot Flag. Set to 1 if the disk uses MBR, 0 if not</td></tr>
  62 <tr><td>0x5031 - 0x503F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
  63 <tr><td>0x5040</td><td>64-bit</td><td>ACPITABLE</td><td>Root/Extended System Description Table Address</td></tr>
  64 <tr><td>0x5048 - 0x504F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
  65 <tr><td>0x5050</td><td>32-bit</td><td>VIDEOBASE</td><td>Base memory address for video display, 0 if not configured</td></tr>
  66 <tr><td>0x5054</td><td>16-bit</td><td>VIDEOX</td><td>Video display width in Pixels</td></tr>
  67 <tr><td>0x5056</td><td>16-bit</td><td>VIDEOY</td><td>Video display height in Pixels</td></tr>
  68 <tr><td>0x5058 - 0x56FF</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
  69 <tr><td>0x5700</td><td>8-bit</td><td>CPUFLAG0</td><td>Flags for CPU with APIC ID 0</td></tr>
  70 <tr><td>0x5701</td><td>8-bit</td><td>CPUFLAG1</td><td>Flags for CPU with APIC ID 1</td></tr>
  71 <tr><td>0x5702</td><td>8-bit</td><td>CPUFLAG2</td><td>Flags for CPU with APIC ID 2</td></tr>
  72 <tr><td>0x5703</td><td>8-bit</td><td>CPUFLAG3</td><td>Flags for CPU with APIC ID 3</td></tr>
  73 <tr><td>0x5704 - 0x57FB</td><td>&nbsp;</td><td>&nbsp;</td><td>Flags for CPU with APIC ID 4 thru to 251</td></tr>
  74 <tr><td>0x57FC</td><td>8-bit</td><td>CPUFLAG252</td><td>Flags for CPU with APIC ID 252</td></tr>
  75 <tr><td>0x57FD</td><td>8-bit</td><td>CPUFLAG253</td><td>Flags for CPU with APIC ID 253</td></tr>
  76 <tr><td>0x57FE</td><td>8-bit</td><td>CPUFLAG254</td><td>Flags for CPU with APIC ID 254</td></tr>
  77 <tr><td>0x57FF</td><td>8-bit</td><td>CPUFLAG255</td><td>Flags for CPU with APIC ID 255</td></tr>
  78 </table>
  79 For the CPU Flags: Bit 0 is set if the CPU is enabled, Bit 1 is set if the CPU is the BSP. If Bit 0 for a CPU is not set then do not attempt to make use of it.<p />
  80 A copy of the E820 System Memory Map is stored at memory address 0x0000000000004000. Each E820 record is 24 bytes in length and the memory map is terminated by a blank record.<p />
  81 <table border="1" cellpadding="2" cellspacing="0">
  82 <tr><th>Variable</th><th>Variable Size</th><th>Description</th></tr>
  83 <tr><td>Starting Address</td><td>64-bit</td><td>The starting address for this record</td></tr>
  84 <tr><td>Length</td><td>64-bit</td><td>The length of memory for this record</td></tr>
  85 <tr><td>Memory Type</td><td>32-bit</td><td>Type 1 is usable memory, Type 2 is not usable</td></tr>
  86 </table>
  87 For more information on the E820 Memory Map: <a href="http://wiki.osdev.org/Detecting_Memory_%28x86%29#BIOS_Function:_INT_0x15.2C_EAX_.3D_0xE820">OSDev wiki on E820</a><p />
  88 <p />
  89 A copy of the VESA SuperVGA Mode Information is stored at memory address 0x0000000000005C00. A description of what is stored in the structure is available <a href="http://www.ctyme.com/intr/rb-0274.htm">here</a>.<p />
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