hw/i386.reference/BTC.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Opcode BTC</TITLE>
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   7 <B>up:</B> <A HREF="c17.htm">
   8 Chapter 17 -- 80386 Instruction Set</A><BR>
   9 <B>prev:</B><A HREF="BT.htm"> BT Bit Test</A><BR>
  10 <B>next:</B><A HREF="BTR.htm"> BTR Bit Test and Reset</A>
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  13 <P>
  14 <H1>BTC -- Bit Test and Complement</H1>
  15
  16 <PRE>
  17 Opcode        Instruction     Clocks  Description
  18
  19 0F  BB        BTC r/m16,r16   6/13    Save bit in carry flag and complement
  20 0F  BB        BTC r/m32,r32   6/13    Save bit in carry flag and complement
  21 0F  BA /7 ib  BTC r/m16,imm8  6/8     Save bit in carry flag and complement
  22 0F  BA /7 ib  BTC r/m32,imm8  6/8     Save bit in carry flag and complement
  23 </PRE>
  24
  25 <H2>Operation</H2>
  26
  27 <PRE>
  28 CF := BIT[LeftSRC, RightSRC];
  29 BIT[LeftSRC, RightSRC] := NOT BIT[LeftSRC, RightSRC];
  30 </PRE>
  31
  32 <H2>Description</H2>
  33
  34 BTC saves the value of the bit indicated by the base (first operand) and the
  35 bit offset (second operand) into the carry flag and then complements the
  36 bit.
  37
  38 <H2>Flags Affected</H2>
  39
  40 CF as described above
  41
  42 <H2>Protected Mode Exceptions</H2>
  43
  44 #GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal
  45 memory operand effective address in the CS, DS, ES, FS, or GS segments;
  46 #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
  47 fault
  48
  49 <H2>Real Address Mode Exceptions</H2>
  50
  51 Interrupt 13 if any part of the operand would lie outside of the effective
  52 address space from 0 to 0FFFFH
  53
  54 <H2>Virtual 8086 Mode Exceptions</H2>
  55
  56 Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
  57
  58 <H2>Notes</H2>
  59
  60 The index of the selected bit can be given by the immediate constant in the
  61 instruction or by a value in a general register. Only an 8-bit immediate
  62 value is used in the instruction. This operand is taken modulo 32, so the
  63 range of immediate bit offsets is 0..31. This allows any bit within a
  64 register to be selected. For memory bit strings, this immediate field gives
  65 only the bit offset within a word or doubleword. Immediate bit offsets
  66 larger than 31 are supported by using the immediate bit offset field in
  67 combination with the displacement field of the memory operand. The low-order
  68 3 to 5 bits of the immediate bit offset are stored in the immediate bit
  69 offset field, and the high-order 27 to 29 bits are shifted and combined with
  70 the byte displacement in the addressing mode.
  71 <P>
  72 When accessing a bit in memory, the 80386 may access four bytes starting
  73 from the memory address given by:
  74 <PRE>
  75    Effective Address + (4 * (BitOffset DIV 32))
  76 </PRE>
  77 for a 32-bit operand size, or two bytes starting from the memory address
  78 given by:
  79 <PRE>
  80    Effective Address + (2 * (BitOffset DIV 16))
  81 </PRE>
  82 for a 16-bit operand size. It may do so even when only a single byte needs
  83 to be accessed in order to reach the given bit. You must therefore avoid
  84 referencing areas of memory close to address space holes. In particular,
  85 avoid references to memory-mapped I/O registers. Instead, use the
  86 <A HREF="MOV.htm">MOV</A>
  87 instructions to load from or store to these addresses, and use the register
  88 form of these instructions to manipulate the data.
  89
  90
  91 <P>
  92 <HR>
  93 <P>
  94 <B>up:</B> <A HREF="c17.htm">
  95 Chapter 17 -- 80386 Instruction Set</A><BR>
  96 <B>prev:</B><A HREF="BT.htm"> BT Bit Test</A><BR>
  97 <B>next:</B><A HREF="BTR.htm"> BTR Bit Test and Reset</A>
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