hw/i386.reference/SAL.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Opcode SAL</TITLE>
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   7 <B>up:</B> <A HREF="c17.htm">
   8 Chapter 17 -- 80386 Instruction Set</A><BR>
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  13 <P>
  14 <H1>SAL/SAR/SHL/SHR -- Shift Instructions</H1>
  15
  16
  17 <PRE>
  18 Opcode          Instruction       Clocks  Description
  19
  20 D0   /4         SAL r/m8,1        3/7     Multiply r/m byte by 2, once
  21 D2   /4         SAL r/m8,CL       3/7     Multiply r/m byte by 2, CL times
  22 C0   /4 ib      SAL r/m8,imm8     3/7     Multiply r/m byte by 2, imm8
  23                                           times
  24 D1   /4         SAL r/m16,1       3/7     Multiply r/m word by 2, once
  25 D3   /4         SAL r/m16,CL      3/7     Multiply r/m word by 2, CL times
  26 C1   /4 ib      SAL r/m16,imm8    3/7     Multiply r/m word by 2, imm8
  27                                           times
  28 D1   /4         SAL r/m32,1       3/7     Multiply r/m dword by 2, once
  29 D3   /4         SAL r/m32,CL      3/7     Multiply r/m dword by 2, CL
  30                                           times
  31 C1   /4 ib      SAL r/m32,imm8    3/7     Multiply r/m dword by 2, imm8
  32                                           times
  33 D0   /7         SAR r/m8,1        3/7     Signed divide^(1) r/m byte by 2,
  34                                           once
  35 D2   /7         SAR r/m8,CL       3/7     Signed divide^(1) r/m byte by 2,
  36                                           CL times
  37 C0   /7 ib      SAR r/m8,imm8     3/7     Signed divide^(1) r/m byte by 2,
  38                                           imm8 times
  39 D1   /7         SAR r/m16,1       3/7     Signed divide^(1) r/m word by 2,
  40                                           once
  41 D3   /7         SAR r/m16,CL      3/7     Signed divide^(1) r/m word by 2,
  42                                           CL times
  43 C1   /7 ib      SAR r/m16,imm8    3/7     Signed divide^(1) r/m word by 2,
  44                                           imm8 times
  45 D1   /7         SAR r/m32,1       3/7     Signed divide^(1) r/m dword by 2,
  46                                           once
  47 D3   /7         SAR r/m32,CL      3/7     Signed divide^(1) r/m dword by 2,
  48                                           CL times
  49 C1   /7 ib      SAR r/m32,imm8    3/7     Signed divide^(1) r/m dword by 2,
  50                                           imm8 times
  51 D0   /4         SHL r/m8,1        3/7     Multiply r/m byte by 2, once
  52 D2   /4         SHL r/m8,CL       3/7     Multiply r/m byte by 2, CL times
  53 C0   /4 ib      SHL r/m8,imm8     3/7     Multiply r/m byte by 2, imm8
  54                                           times
  55 D1   /4         SHL r/m16,1       3/7     Multiply r/m word by 2, once
  56 D3   /4         SHL r/m16,CL      3/7     Multiply r/m word by 2, CL times
  57 C1   /4 ib      SHL r/m16,imm8    3/7     Multiply r/m word by 2, imm8
  58                                           times
  59 D1   /4         SHL r/m32,1       3/7     Multiply r/m dword by 2, once
  60 D3   /4         SHL r/m32,CL      3/7     Multiply r/m dword by 2, CL
  61                                           times
  62 C1   /4 ib      SHL r/m32,imm8    3/7     Multiply r/m dword by 2, imm8
  63                                           times
  64 D0   /5         SHR r/m8,1        3/7     Unsigned divide r/m byte by 2,
  65                                           once
  66 D2   /5         SHR r/m8,CL       3/7     Unsigned divide r/m byte by 2,
  67                                           CL times
  68 C0   /5 ib      SHR r/m8,imm8     3/7     Unsigned divide r/m byte by 2,
  69                                           imm8 times
  70 D1   /5         SHR r/m16,1       3/7     Unsigned divide r/m word by 2,
  71                                           once
  72 D3   /5         SHR r/m16,CL      3/7     Unsigned divide r/m word by 2,
  73                                           CL times
  74 C1   /5 ib      SHR r/m16,imm8    3/7     Unsigned divide r/m word by 2,
  75                                           imm8 times
  76 D1   /5         SHR r/m32,1       3/7     Unsigned divide r/m dword by 2,
  77                                           once
  78 D3   /5         SHR r/m32,CL      3/7     Unsigned divide r/m dword by 2,
  79                                           CL times
  80 C1   /5 ib      SHR r/m32,imm8    3/7     Unsigned divide r/m dword by 2,
  81                                           imm8 times
  82 </PRE>
  83
  84 Not the same division as
  85 <A HREF="IDIV.htm">IDIV</A>; rounding is toward negative infinity.
  86
  87 <H2>Operation</H2>
  88
  89 <PRE>
  90 (* COUNT is the second parameter *)
  91 (temp) := COUNT;
  92 WHILE (temp <> 0)
  93 DO
  94    IF instruction is SAL or SHL
  95    THEN CF := high-order bit of r/m;
  96    FI;
  97    IF instruction is SAR or SHR
  98    THEN CF := low-order bit of r/m;
  99    FI;
 100    IF instruction = SAL or SHL
 101    THEN r/m := r/m * 2;
 102    FI;
 103    IF instruction = SAR
 104    THEN r/m := r/m /2 (*Signed divide, rounding toward negative infinity*);
 105    FI;
 106    IF instruction = SHR
 107    THEN r/m := r/m / 2; (* Unsigned divide *);
 108    FI;
 109    temp := temp - 1;
 110 OD;
 111 (* Determine overflow for the various instructions *)
 112 IF COUNT = 1
 113 THEN
 114    IF instruction is SAL or SHL
 115    THEN OF := high-order bit of r/m <> (CF);
 116    FI;
 117    IF instruction is SAR
 118    THEN OF := 0;
 119    FI;
 120    IF instruction is SHR
 121    THEN OF := high-order bit of operand;
 122    FI;
 123 ELSE OF := undefined;
 124 FI;
 125 </PRE>
 126
 127 <H2>Description</H2>
 128
 129 SAL (or its synonym, SHL) shifts the bits of the operand upward. The
 130 high-order bit is shifted into the carry flag, and the low-order bit is set
 131 to 0.
 132 <P>
 133 SAR and SHR shift the bits of the operand downward. The low-order
 134 bit is shifted into the carry flag. The effect is to divide the operand by
 135 2. SAR performs a signed divide with rounding toward negative infinity (not
 136 the same as
 137 <A HREF="IDIV.htm">IDIV</A>);
 138 the high-order bit remains the same. SHR performs an
 139 unsigned divide; the high-order bit is set to 0.
 140 <P>
 141 The shift is repeated the number of times indicated by the second
 142 operand, which is either an immediate number or the contents of the CL
 143 register. To reduce the maximum execution time, the 80386 does not
 144 allow shift counts greater than 31. If a shift count greater than 31 is
 145 attempted, only the bottom five bits of the shift count are used. (The
 146 8086 uses all eight bits of the shift count.)
 147 <P>
 148 The overflow flag is set only if the single-shift forms of the instructions
 149 are used. For left shifts, OF is set to 0 if the high bit of the answer is
 150 the same as the result of the carry flag (i.e., the top two bits of the
 151 original operand were the same); OF is set to 1 if they are different. For
 152 SAR, OF is set to 0 for all single shifts. For SHR, OF is set to the
 153 high-order bit of the original operand.
 154
 155 <H2>Flags Affected</H2>
 156
 157 OF for single shifts; OF is undefined for multiple shifts; CF, ZF, PF,
 158 and SF as described in <A HREF="appc.htm">Appendix C</A>
 159
 160 <H2>Protected Mode Exceptions</H2>
 161
 162 #GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal
 163 memory operand effective address in the CS, DS, ES, FS, or GS
 164 segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code)
 165 for a page fault
 166
 167 <H2>Real Address Mode Exceptions</H2>
 168
 169 Interrupt 13 if any part of the operand would lie outside of the effective
 170 address space from 0 to 0FFFFH
 171
 172 <H2>Virtual 8086 Mode Exceptions</H2>
 173
 174 Same exceptions as in Real Address Mode; #PF(fault-code) for a page
 175 fault
 176
 177
 178 <P>
 179 <HR>
 180 <P>
 181 <B>up:</B> <A HREF="c17.htm">
 182 Chapter 17 -- 80386 Instruction Set</A><BR>
 183 <B>prev:</B><A HREF="SAHF.htm"> SAHF Store AH into Flags</A><BR>
 184 <B>next:</B><A HREF="SBB.htm"> SBB Integer Subtraction with Borrow</A>
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