hw/i386.reference/SHLD.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Opcode SHLD</TITLE>
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   8 Chapter 17 -- 80386 Instruction Set</A><BR>
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  13 <P>
  14 <H1>SHLD -- Double Precision Shift Left</H1>
  15
  16 <PRE>
  17 Opcode   Instruction          Clocks   Description
  18
  19 0F  A4   SHLD r/m16,r16,imm8  3/7      r/m16 gets SHL of r/m16 concatenated
  20                                        with r16
  21 0F  A4   SHLD r/m32,r32,imm8  3/7      r/m32 gets SHL of r/m32 concatenated
  22                                        with r32
  23 0F  A5   SHLD r/m16,r16,CL    3/7      r/m16 gets SHL of r/m16 concatenated
  24                                        with r16
  25 0F  A5   SHLD r/m32,r32,CL    3/7      r/m32 gets SHL of r/m32 concatenated
  26                                        with r32
  27 </PRE>
  28
  29
  30 <H2>Operation</H2>
  31
  32 <PRE>
  33 (* count is an unsigned integer corresponding to the last operand of the
  34 instruction, either an immediate byte or the byte in register CL *)
  35 ShiftAmt := count MOD 32;
  36 inBits := register; (* Allow overlapped operands *)
  37 IF ShiftAmt = 0
  38 THEN no operation
  39 ELSE
  40    IF ShiftAmt >= OperandSize
  41    THEN (* Bad parameters *)
  42       r/m := UNDEFINED;
  43       CF, OF, SF, ZF, AF, PF := UNDEFINED;
  44    ELSE (* Perform the shift *)
  45       CF := BIT[Base, OperandSize - ShiftAmt];
  46          (* Last bit shifted out on exit *)
  47    FOR i := OperandSize - 1 DOWNTO ShiftAmt
  48    DO
  49       BIT[Base, i] := BIT[Base, i - ShiftAmt];
  50    OF;
  51    FOR i := ShiftAmt - 1 DOWNTO 0
  52    DO
  53       BIT[Base, i] := BIT[inBits, i - ShiftAmt + OperandSize];
  54    OD;
  55    Set SF, ZF, PF (r/m);
  56       (* SF, ZF, PF are set according to the value of the result *)
  57    AF := UNDEFINED;
  58    FI;
  59 FI;
  60 </PRE>
  61
  62 <H2>Description</H2>
  63
  64 SHLD shifts the first operand provided by the r/m field to the left as
  65 many bits as specified by the count operand. The second operand (r16 or r32)
  66 provides the bits to shift in from the right (starting with bit 0). The
  67 result is stored back into the r/m operand. The register remains unaltered.
  68 <P>
  69 The count operand is provided by either an immediate byte or the contents
  70 of the CL register. These operands are taken MODULO 32 to provide a number
  71 between 0 and 31 by which to shift. Because the bits to shift are provided
  72 by the specified registers, the operation is useful for multiprecision
  73 shifts (64 bits or more). The SF, ZF and PF flags are set according to the
  74 value of the result. CS is set to the value of the last bit shifted out. OF
  75 and AF are left undefined.
  76
  77 <H2>Flags Affected</H2>
  78
  79 OF, SF, ZF, PF, and CF as described above; AF and OF are undefined
  80
  81 <H2>Protected Mode Exceptions</H2>
  82
  83 #GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal
  84 memory operand effective address in the CS, DS, ES, FS, or GS segments;
  85 #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
  86 fault
  87
  88 <H2>Real Address Mode Exceptions</H2>
  89
  90 Interrupt 13 if any part of the operand would lie outside of the effective
  91 address space from 0 to 0FFFFH
  92
  93 <H2>Virtual 8086 Mode Exceptions</H2>
  94
  95 Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
  96
  97
  98 <P>
  99 <HR>
 100 <P>
 101 <B>up:</B> <A HREF="c17.htm">
 102 Chapter 17 -- 80386 Instruction Set</A><BR>
 103 <B>prev:</B><A HREF="SGDT.htm"> SGDT/SIDT Store Global/Interrupt Descriptor Table Register</A><BR>
 104 <B>next:</B><A HREF="SHRD.htm"> SHRD Double Precision Shift Right</A>
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