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[mascara-docs.git] / i386 / linux-2.3.21 / arch / alpha / kernel / sys_dp264.c
blob9959aad332c5d760b3f6ac04f80ed4858b01aa6c
1 /*
2 * linux/arch/alpha/kernel/sys_dp264.c
3 *
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996, 1999 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 *
8 * Code supporting the DP264 (EV6+TSUNAMI).
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/mm.h>
14 #include <linux/sched.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
17
18 #include <asm/ptrace.h>
19 #include <asm/system.h>
20 #include <asm/dma.h>
21 #include <asm/irq.h>
22 #include <asm/bitops.h>
23 #include <asm/mmu_context.h>
24 #include <asm/io.h>
25 #include <asm/pgtable.h>
26 #include <asm/core_tsunami.h>
27 #include <asm/hwrpb.h>
28
29 #include "proto.h"
30 #include "irq_impl.h"
31 #include "pci_impl.h"
32 #include "machvec_impl.h"
33
34
35 /*
36 * HACK ALERT! only the boot cpu is used for interrupts.
37 */
38
39 static void
40 dp264_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
41 {
42 if (irq >= 16) {
43 volatile unsigned long *csr;
44
45 if (TSUNAMI_bootcpu < 2)
46 if (!TSUNAMI_bootcpu)
47 csr = &TSUNAMI_cchip->dim0.csr;
48 else
49 csr = &TSUNAMI_cchip->dim1.csr;
50 else
51 if (TSUNAMI_bootcpu == 2)
52 csr = &TSUNAMI_cchip->dim2.csr;
53 else
54 csr = &TSUNAMI_cchip->dim3.csr;
55
56 *csr = ~mask;
57 mb();
58 *csr;
59 }
60 else if (irq >= 8)
61 outb(mask >> 8, 0xA1); /* ISA PIC2 */
62 else
63 outb(mask, 0x21); /* ISA PIC1 */
64 }
65
66 static void
67 clipper_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
68 {
69 if (irq >= 16) {
70 volatile unsigned long *csr;
71
72 if (TSUNAMI_bootcpu < 2)
73 if (!TSUNAMI_bootcpu)
74 csr = &TSUNAMI_cchip->dim0.csr;
75 else
76 csr = &TSUNAMI_cchip->dim1.csr;
77 else
78 if (TSUNAMI_bootcpu == 2)
79 csr = &TSUNAMI_cchip->dim2.csr;
80 else
81 csr = &TSUNAMI_cchip->dim3.csr;
82
83 *csr = (~mask >> 16) | (1UL << 55); /* master ISA enable */
84 mb();
85 *csr;
86 }
87 else if (irq >= 8)
88 outb(mask >> 8, 0xA1); /* ISA PIC2 */
89 else
90 outb(mask, 0x21); /* ISA PIC1 */
91 }
92
93 static void
94 dp264_device_interrupt(unsigned long vector, struct pt_regs * regs)
95 {
96 #if 1
97 printk("dp264_device_interrupt: NOT IMPLEMENTED YET!! \n");
98 #else
99 unsigned long pld;
100 unsigned int i;
101
102 /* Read the interrupt summary register of TSUNAMI */
103 pld = TSUNAMI_cchip->dir0.csr;
104
105 /*
106 * Now for every possible bit set, work through them and call
107 * the appropriate interrupt handler.
108 */
109 while (pld) {
110 i = ffz(~pld);
111 pld &= pld - 1; /* clear least bit set */
112 if (i == 55)
113 isa_device_interrupt(vector, regs);
114 else
115 handle_irq(16 + i, 16 + i, regs);
116 #if 0
117 TSUNAMI_cchip->dir0.csr = 1UL << i; mb();
118 tmp = TSUNAMI_cchip->dir0.csr;
119 #endif
120 }
121 #endif
122 }
123
124 static void
125 dp264_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
126 {
127 int irq, ack;
128
129 ack = irq = (vector - 0x800) >> 4;
130
131 /*
132 * The SRM console reports PCI interrupts with a vector calculated by:
133 *
134 * 0x900 + (0x10 * DRIR-bit)
135 *
136 * So bit 16 shows up as IRQ 32, etc.
137 *
138 * On DP264/BRICK/MONET, we adjust it down by 16 because at least
139 * that many of the low order bits of the DRIR are not used, and
140 * so we don't count them.
141 */
142 if (irq >= 32)
143 ack = irq = irq - 16;
144
145 handle_irq(irq, ack, regs);
146 }
147
148 static void
149 clipper_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
150 {
151 int irq, ack;
152
153 ack = irq = (vector - 0x800) >> 4;
154
155 /*
156 * The SRM console reports PCI interrupts with a vector calculated by:
157 *
158 * 0x900 + (0x10 * DRIR-bit)
159 *
160 * So bit 16 shows up as IRQ 32, etc.
161 *
162 * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
163 * to scale down the vector reported, we just use it.
164 *
165 * Eg IRQ 24 is DRIR bit 8, etc, etc
166 */
167 handle_irq(irq, ack, regs);
168 }
169
170 static void __init
171 dp264_init_irq(void)
172 {
173 outb(0, DMA1_RESET_REG);
174 outb(0, DMA2_RESET_REG);
175 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
176 outb(0, DMA2_MASK_REG);
177
178 if (alpha_using_srm)
179 alpha_mv.device_interrupt = dp264_srm_device_interrupt;
180
181 dp264_update_irq_hw(16, alpha_irq_mask, 0);
182
183 enable_irq(55); /* Enable ISA interrupt controller. */
184 enable_irq(2);
185 }
186
187 static void __init
188 clipper_init_irq(void)
189 {
190 outb(0, DMA1_RESET_REG);
191 outb(0, DMA2_RESET_REG);
192 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
193 outb(0, DMA2_MASK_REG);
194
195 if (alpha_using_srm)
196 alpha_mv.device_interrupt = clipper_srm_device_interrupt;
197
198 clipper_update_irq_hw(16, alpha_irq_mask, 0);
199
200 enable_irq(55); /* Enable ISA interrupt controller. */
201 enable_irq(2);
202 }
203
204
205 /*
206 * PCI Fixup configuration.
207 *
208 * Summary @ TSUNAMI_CSR_DIM0:
209 * Bit Meaning
210 * 0-17 Unused
211 *18 Interrupt SCSI B (Adaptec 7895 builtin)
212 *19 Interrupt SCSI A (Adaptec 7895 builtin)
213 *20 Interrupt Line D from slot 2 PCI0
214 *21 Interrupt Line C from slot 2 PCI0
215 *22 Interrupt Line B from slot 2 PCI0
216 *23 Interrupt Line A from slot 2 PCI0
217 *24 Interrupt Line D from slot 1 PCI0
218 *25 Interrupt Line C from slot 1 PCI0
219 *26 Interrupt Line B from slot 1 PCI0
220 *27 Interrupt Line A from slot 1 PCI0
221 *28 Interrupt Line D from slot 0 PCI0
222 *29 Interrupt Line C from slot 0 PCI0
223 *30 Interrupt Line B from slot 0 PCI0
224 *31 Interrupt Line A from slot 0 PCI0
225 *
226 *32 Interrupt Line D from slot 3 PCI1
227 *33 Interrupt Line C from slot 3 PCI1
228 *34 Interrupt Line B from slot 3 PCI1
229 *35 Interrupt Line A from slot 3 PCI1
230 *36 Interrupt Line D from slot 2 PCI1
231 *37 Interrupt Line C from slot 2 PCI1
232 *38 Interrupt Line B from slot 2 PCI1
233 *39 Interrupt Line A from slot 2 PCI1
234 *40 Interrupt Line D from slot 1 PCI1
235 *41 Interrupt Line C from slot 1 PCI1
236 *42 Interrupt Line B from slot 1 PCI1
237 *43 Interrupt Line A from slot 1 PCI1
238 *44 Interrupt Line D from slot 0 PCI1
239 *45 Interrupt Line C from slot 0 PCI1
240 *46 Interrupt Line B from slot 0 PCI1
241 *47 Interrupt Line A from slot 0 PCI1
242 *48-52 Unused
243 *53 PCI0 NMI (from Cypress)
244 *54 PCI0 SMI INT (from Cypress)
245 *55 PCI0 ISA Interrupt (from Cypress)
246 *56-60 Unused
247 *61 PCI1 Bus Error
248 *62 PCI0 Bus Error
249 *63 Reserved
250 *
251 * IdSel
252 * 5 Cypress Bridge I/O
253 * 6 SCSI Adaptec builtin
254 * 7 64 bit PCI option slot 0 (all busses)
255 * 8 64 bit PCI option slot 1 (all busses)
256 * 9 64 bit PCI option slot 2 (all busses)
257 * 10 64 bit PCI option slot 3 (not bus 0)
258 */
259
260 static int __init
261 dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
262 {
263 static char irq_tab[6][5] __initlocaldata = {
264 /*INT INTA INTB INTC INTD */
265 { -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */
266 { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
267 { 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
268 { 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
269 { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
270 { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
271 };
272 const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
273
274 struct pci_controler *hose = dev->sysdata;
275 int irq = COMMON_TABLE_LOOKUP;
276
277 if (irq > 0)
278 irq += 16 * hose->index;
279
280 return irq;
281 }
282
283 static int __init
284 monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
285 {
286 static char irq_tab[13][5] __initlocaldata = {
287 /*INT INTA INTB INTC INTD */
288 { 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */
289 { -1, -1, -1, -1, -1}, /* IdSel 4 unused */
290 { -1, -1, -1, -1, -1}, /* IdSel 5 unused */
291 { 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */
292 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
293 { -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */
294 #if 1
295 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
296 { 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/
297 #else
298 { -1, -1, -1, -1, -1}, /* IdSel 9 unused */
299 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
300 #endif
301 { 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/
302 { 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/
303 { 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/
304 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
305 { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
306 };
307 const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
308 return COMMON_TABLE_LOOKUP;
309 }
310
311 static u8 __init
312 monet_swizzle(struct pci_dev *dev, u8 *pinp)
313 {
314 struct pci_controler *hose = dev->sysdata;
315 int slot, pin = *pinp;
316
317 if (hose->first_busno == dev->bus->number) {
318 slot = PCI_SLOT(dev->devfn);
319 }
320 /* Check for the built-in bridge on hose 1. */
321 else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
322 slot = PCI_SLOT(dev->devfn);
323 } else {
324 /* Must be a card-based bridge. */
325 do {
326 /* Check for built-in bridge on hose 1. */
327 if (hose->index == 1 &&
328 PCI_SLOT(dev->bus->self->devfn) == 8) {
329 slot = PCI_SLOT(dev->devfn);
330 break;
331 }
332 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)) ;
333
334 /* Move up the chain of bridges. */
335 dev = dev->bus->self;
336 /* Slot of the next bridge. */
337 slot = PCI_SLOT(dev->devfn);
338 } while (dev->bus->self);
339 }
340 *pinp = pin;
341 return slot;
342 }
343
344 static int __init
345 webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
346 {
347 static char irq_tab[13][5] __initlocaldata = {
348 /*INT INTA INTB INTC INTD */
349 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
350 { -1, -1, -1, -1, -1}, /* IdSel 8 unused */
351 { 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */
352 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
353 { 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */
354 { -1, -1, -1, -1, -1}, /* IdSel 12 unused */
355 { -1, -1, -1, -1, -1}, /* IdSel 13 unused */
356 { 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */
357 { 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */
358 { 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */
359 { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
360 };
361 const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
362 return COMMON_TABLE_LOOKUP;
363 }
364
365 static int __init
366 clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
367 {
368 static char irq_tab[7][5] __initlocaldata = {
369 /*INT INTA INTB INTC INTD */
370 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
371 { 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
372 { 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
373 { 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
374 { 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
375 { 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
376 { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
377 };
378 const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
379
380 struct pci_controler *hose = dev->sysdata;
381 int irq = COMMON_TABLE_LOOKUP;
382
383 if (irq > 0)
384 irq += 16 * hose->index;
385
386 return irq;
387 }
388
389 static void __init
390 dp264_init_pci(void)
391 {
392 common_init_pci();
393 SMC669_Init(0);
394 }
395
396 static void __init
397 monet_init_pci(void)
398 {
399 common_init_pci();
400 SMC669_Init(1);
401 es1888_init();
402 }
403
404
405 /*
406 * The System Vectors
407 */
408
409 struct alpha_machine_vector dp264_mv __initmv = {
410 vector_name: "DP264",
411 DO_EV6_MMU,
412 DO_DEFAULT_RTC,
413 DO_TSUNAMI_IO,
414 DO_TSUNAMI_BUS,
415 machine_check: tsunami_machine_check,
416 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
417 min_io_address: DEFAULT_IO_BASE,
418 min_mem_address: DEFAULT_MEM_BASE,
419
420 nr_irqs: 64,
421 irq_probe_mask: _PROBE_MASK(64),
422 update_irq_hw: dp264_update_irq_hw,
423 ack_irq: common_ack_irq,
424 device_interrupt: dp264_device_interrupt,
425
426 init_arch: tsunami_init_arch,
427 init_irq: dp264_init_irq,
428 init_pit: common_init_pit,
429 init_pci: dp264_init_pci,
430 kill_arch: common_kill_arch,
431 pci_map_irq: dp264_map_irq,
432 pci_swizzle: common_swizzle,
433 };
434 ALIAS_MV(dp264)
435
436 struct alpha_machine_vector monet_mv __initmv = {
437 vector_name: "Monet",
438 DO_EV6_MMU,
439 DO_DEFAULT_RTC,
440 DO_TSUNAMI_IO,
441 DO_TSUNAMI_BUS,
442 machine_check: tsunami_machine_check,
443 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
444 min_io_address: DEFAULT_IO_BASE,
445 min_mem_address: DEFAULT_MEM_BASE,
446
447 nr_irqs: 64,
448 irq_probe_mask: _PROBE_MASK(64),
449 update_irq_hw: dp264_update_irq_hw,
450 ack_irq: common_ack_irq,
451 device_interrupt: dp264_device_interrupt,
452
453 init_arch: tsunami_init_arch,
454 init_irq: dp264_init_irq,
455 init_pit: common_init_pit,
456 init_pci: monet_init_pci,
457 kill_arch: common_kill_arch,
458 pci_map_irq: monet_map_irq,
459 pci_swizzle: monet_swizzle,
460 };
461
462 struct alpha_machine_vector webbrick_mv __initmv = {
463 vector_name: "Webbrick",
464 DO_EV6_MMU,
465 DO_DEFAULT_RTC,
466 DO_TSUNAMI_IO,
467 DO_TSUNAMI_BUS,
468 machine_check: tsunami_machine_check,
469 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
470 min_io_address: DEFAULT_IO_BASE,
471 min_mem_address: DEFAULT_MEM_BASE,
472
473 nr_irqs: 64,
474 irq_probe_mask: _PROBE_MASK(64),
475 update_irq_hw: dp264_update_irq_hw,
476 ack_irq: common_ack_irq,
477 device_interrupt: dp264_device_interrupt,
478
479 init_arch: tsunami_init_arch,
480 init_irq: dp264_init_irq,
481 init_pit: common_init_pit,
482 init_pci: dp264_init_pci,
483 kill_arch: common_kill_arch,
484 pci_map_irq: webbrick_map_irq,
485 pci_swizzle: common_swizzle,
486 };
487
488 struct alpha_machine_vector clipper_mv __initmv = {
489 vector_name: "Clipper",
490 DO_EV6_MMU,
491 DO_DEFAULT_RTC,
492 DO_TSUNAMI_IO,
493 DO_TSUNAMI_BUS,
494 machine_check: tsunami_machine_check,
495 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
496 min_io_address: DEFAULT_IO_BASE,
497 min_mem_address: DEFAULT_MEM_BASE,
498
499 nr_irqs: 64,
500 irq_probe_mask: _PROBE_MASK(64),
501 update_irq_hw: clipper_update_irq_hw,
502 ack_irq: common_ack_irq,
503 device_interrupt: dp264_device_interrupt,
504
505 init_arch: tsunami_init_arch,
506 init_irq: clipper_init_irq,
507 init_pit: common_init_pit,
508 init_pci: common_init_pci,
509 kill_arch: common_kill_arch,
510 pci_map_irq: clipper_map_irq,
511 pci_swizzle: common_swizzle,
512 };
513
514 /* No alpha_mv alias for webbrick/monet/clipper, since we compile them
515 in unconditionally with DP264; setup_arch knows how to cope. */