i386/linux-2.3.21/arch/alpha/kernel/sys_noritake.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_noritake.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code supporting the NORITAKE (AlphaServer 1000A),
   9  * CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A).
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/mm.h>
  16 #include <linux/sched.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19
  20 #include <asm/ptrace.h>
  21 #include <asm/system.h>
  22 #include <asm/dma.h>
  23 #include <asm/irq.h>
  24 #include <asm/bitops.h>
  25 #include <asm/mmu_context.h>
  26 #include <asm/io.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/core_apecs.h>
  29 #include <asm/core_cia.h>
  30
  31 #include "proto.h"
  32 #include "irq_impl.h"
  33 #include "pci_impl.h"
  34 #include "machvec_impl.h"
  35
  36
  37 static void
  38 noritake_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
  39 {
  40         if (irq <= 15)
  41                 if (irq <= 7)
  42                         outb(mask, 0x21);       /* ISA PIC1 */
  43                 else
  44                         outb(mask >> 8, 0xA1);  /* ISA PIC2 */
  45         else if (irq <= 31)
  46                 outw(~(mask >> 16), 0x54a);
  47         else
  48                 outw(~(mask >> 32), 0x54c);
  49 }
  50
  51 static void
  52 noritake_device_interrupt(unsigned long vector, struct pt_regs *regs)
  53 {
  54         unsigned long pld;
  55         unsigned int i;
  56
  57         /* Read the interrupt summary registers of NORITAKE */
  58         pld = ((unsigned long) inw(0x54c) << 32) |
  59                 ((unsigned long) inw(0x54a) << 16) |
  60                 ((unsigned long) inb(0xa0)  <<  8) |
  61                 ((unsigned long) inb(0x20));
  62
  63         /*
  64          * Now for every possible bit set, work through them and call
  65          * the appropriate interrupt handler.
  66          */
  67         while (pld) {
  68                 i = ffz(~pld);
  69                 pld &= pld - 1; /* clear least bit set */
  70                 if (i < 16) {
  71                         isa_device_interrupt(vector, regs);
  72                 } else {
  73                         handle_irq(i, i, regs);
  74                 }
  75         }
  76 }
  77
  78 static void
  79 noritake_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
  80 {
  81         int irq, ack;
  82
  83         ack = irq = (vector - 0x800) >> 4;
  84
  85         /*
  86          * I really hate to do this, too, but the NORITAKE SRM console also
  87          *  reports PCI vectors *lower* than I expected from the bit numbers
  88          *  in the documentation.
  89          * But I really don't want to change the fixup code for allocation
  90          *  of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
  91          *  look nice and clean now.
  92          * So, here's this additional grotty hack... :-(
  93          */
  94         if (irq >= 16)
  95                 ack = irq = irq + 1;
  96
  97         handle_irq(irq, ack, regs);
  98 }
  99
 100 static void __init
 101 noritake_init_irq(void)
 102 {
 103         STANDARD_INIT_IRQ_PROLOG;
 104
 105         if (alpha_using_srm)
 106                 alpha_mv.device_interrupt = noritake_srm_device_interrupt;
 107
 108         outw(~(alpha_irq_mask >> 16), 0x54a); /* note invert */
 109         outw(~(alpha_irq_mask >> 32), 0x54c); /* note invert */
 110         enable_irq(2);                  /* enable cascade */
 111 }
 112
 113
 114 /*
 115  * PCI Fixup configuration.
 116  *
 117  * Summary @ 0x542, summary register #1:
 118  * Bit      Meaning
 119  * 0        All valid ints from summary regs 2 & 3
 120  * 1        QLOGIC ISP1020A SCSI
 121  * 2        Interrupt Line A from slot 0
 122  * 3        Interrupt Line B from slot 0
 123  * 4        Interrupt Line A from slot 1
 124  * 5        Interrupt line B from slot 1
 125  * 6        Interrupt Line A from slot 2
 126  * 7        Interrupt Line B from slot 2
 127  * 8        Interrupt Line A from slot 3
 128  * 9        Interrupt Line B from slot 3
 129  *10        Interrupt Line A from slot 4
 130  *11        Interrupt Line B from slot 4
 131  *12        Interrupt Line A from slot 5
 132  *13        Interrupt Line B from slot 5
 133  *14        Interrupt Line A from slot 6
 134  *15        Interrupt Line B from slot 6
 135  *
 136  * Summary @ 0x544, summary register #2:
 137  * Bit      Meaning
 138  * 0        OR of all unmasked ints in SR #2
 139  * 1        OR of secondary bus ints
 140  * 2        Interrupt Line C from slot 0
 141  * 3        Interrupt Line D from slot 0
 142  * 4        Interrupt Line C from slot 1
 143  * 5        Interrupt line D from slot 1
 144  * 6        Interrupt Line C from slot 2
 145  * 7        Interrupt Line D from slot 2
 146  * 8        Interrupt Line C from slot 3
 147  * 9        Interrupt Line D from slot 3
 148  *10        Interrupt Line C from slot 4
 149  *11        Interrupt Line D from slot 4
 150  *12        Interrupt Line C from slot 5
 151  *13        Interrupt Line D from slot 5
 152  *14        Interrupt Line C from slot 6
 153  *15        Interrupt Line D from slot 6
 154  *
 155  * The device to slot mapping looks like:
 156  *
 157  * Slot     Device
 158  *  7       Intel PCI-EISA bridge chip
 159  *  8       DEC PCI-PCI bridge chip
 160  * 11       PCI on board slot 0
 161  * 12       PCI on board slot 1
 162  * 13       PCI on board slot 2
 163  *
 164  *
 165  * This two layered interrupt approach means that we allocate IRQ 16 and
 166  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 167  * comes in on.  This makes interrupt processing much easier.
 168  */
 169
 170 static int __init
 171 noritake_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 172 {
 173         static char irq_tab[15][5] __initlocaldata = {
 174                 /*INT    INTA   INTB   INTC   INTD */
 175                 /* note: IDSELs 16, 17, and 25 are CORELLE only */
 176                 { 16+1,  16+1,  16+1,  16+1,  16+1},  /* IdSel 16,  QLOGIC */
 177                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 17, S3 Trio64 */
 178                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 18,  PCEB */
 179                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 19,  PPB  */
 180                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 20,  ???? */
 181                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 21,  ???? */
 182                 { 16+2,  16+2,  16+3,  32+2,  32+3},  /* IdSel 22,  slot 0 */
 183                 { 16+4,  16+4,  16+5,  32+4,  32+5},  /* IdSel 23,  slot 1 */
 184                 { 16+6,  16+6,  16+7,  32+6,  32+7},  /* IdSel 24,  slot 2 */
 185                 { 16+8,  16+8,  16+9,  32+8,  32+9},    /* IdSel 25,  slot 3 */
 186                 /* The following 5 are actually on PCI bus 1, which is
 187                    across the built-in bridge of the NORITAKE only.  */
 188                 { 16+1,  16+1,  16+1,  16+1,  16+1},  /* IdSel 16,  QLOGIC */
 189                 { 16+8,  16+8,  16+9,  32+8,  32+9},  /* IdSel 17,  slot 3 */
 190                 {16+10, 16+10, 16+11, 32+10, 32+11},  /* IdSel 18,  slot 4 */
 191                 {16+12, 16+12, 16+13, 32+12, 32+13},  /* IdSel 19,  slot 5 */
 192                 {16+14, 16+14, 16+15, 32+14, 32+15},  /* IdSel 20,  slot 6 */
 193         };
 194         const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5;
 195         return COMMON_TABLE_LOOKUP;
 196 }
 197
 198 static u8 __init
 199 noritake_swizzle(struct pci_dev *dev, u8 *pinp)
 200 {
 201         int slot, pin = *pinp;
 202
 203         if (dev->bus->number == 0) {
 204                 slot = PCI_SLOT(dev->devfn);
 205         }
 206         /* Check for the built-in bridge */
 207         else if (PCI_SLOT(dev->bus->self->devfn) == 8) {
 208                 slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */
 209         }
 210         else
 211         {
 212                 /* Must be a card-based bridge.  */
 213                 do {
 214                         if (PCI_SLOT(dev->bus->self->devfn) == 8) {
 215                                 slot = PCI_SLOT(dev->devfn) + 15;
 216                                 break;
 217                         }
 218                         pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)) ;
 219
 220                         /* Move up the chain of bridges.  */
 221                         dev = dev->bus->self;
 222                         /* Slot of the next bridge.  */
 223                         slot = PCI_SLOT(dev->devfn);
 224                 } while (dev->bus->self);
 225         }
 226         *pinp = pin;
 227         return slot;
 228 }
 229
 230
 231 /*
 232  * The System Vectors
 233  */
 234
 235 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
 236 struct alpha_machine_vector noritake_mv __initmv = {
 237         vector_name:            "Noritake",
 238         DO_EV4_MMU,
 239         DO_DEFAULT_RTC,
 240         DO_APECS_IO,
 241         DO_APECS_BUS,
 242         machine_check:          apecs_machine_check,
 243         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 244         min_io_address:         EISA_DEFAULT_IO_BASE,
 245         min_mem_address:        APECS_AND_LCA_DEFAULT_MEM_BASE,
 246
 247         nr_irqs:                48,
 248         irq_probe_mask:         _PROBE_MASK(48),
 249         update_irq_hw:          noritake_update_irq_hw,
 250         ack_irq:                common_ack_irq,
 251         device_interrupt:       noritake_device_interrupt,
 252
 253         init_arch:              apecs_init_arch,
 254         init_irq:               noritake_init_irq,
 255         init_pit:               common_init_pit,
 256         init_pci:               common_init_pci,
 257         kill_arch:              common_kill_arch,
 258         pci_map_irq:            noritake_map_irq,
 259         pci_swizzle:            noritake_swizzle,
 260 };
 261 ALIAS_MV(noritake)
 262 #endif
 263
 264 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
 265 struct alpha_machine_vector noritake_primo_mv __initmv = {
 266         vector_name:            "Noritake-Primo",
 267         DO_EV5_MMU,
 268         DO_DEFAULT_RTC,
 269         DO_CIA_IO,
 270         DO_CIA_BUS,
 271         machine_check:          cia_machine_check,
 272         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 273         min_io_address:         EISA_DEFAULT_IO_BASE,
 274         min_mem_address:        CIA_DEFAULT_MEM_BASE,
 275
 276         nr_irqs:                48,
 277         irq_probe_mask:         _PROBE_MASK(48),
 278         update_irq_hw:          noritake_update_irq_hw,
 279         ack_irq:                common_ack_irq,
 280         device_interrupt:       noritake_device_interrupt,
 281
 282         init_arch:              cia_init_arch,
 283         init_irq:               noritake_init_irq,
 284         init_pit:               common_init_pit,
 285         init_pci:               common_init_pci,
 286         kill_arch:              common_kill_arch,
 287         pci_map_irq:            noritake_map_irq,
 288         pci_swizzle:            noritake_swizzle,
 289 };
 290 ALIAS_MV(noritake_primo)
 291 #endif