i386/linux-2.3.21/arch/arm/lib/io-ebsa110.S

   1 /*
   2  * linux/arch/arm/lib/io-ebsa.S
   3  *
   4  * Copyright (C) 1995, 1996 Russell King
   5  */
   6 #include <linux/linkage.h>
   7 #include <asm/assembler.h>
   8                 .text
   9                 .align
  10
  11 #define OUT(reg)                                        \
  12                 mov     r8, reg, lsl $16                ;\
  13                 orr     r8, r8, r8, lsr $16             ;\
  14                 str     r8, [r3, r0, lsl $2]            ;\
  15                 mov     r8, reg, lsr $16                ;\
  16                 orr     r8, r8, r8, lsl $16             ;\
  17                 str     r8, [r3, r0, lsl $2]
  18
  19 #define IN(reg)                                         \
  20                 ldr     reg, [r0]                       ;\
  21                 and     reg, reg, ip                    ;\
  22                 ldr     lr, [r0]                        ;\
  23                 orr     reg, reg, lr, lsl $16
  24
  25 /*
  26  * These make no sense on these machines.
  27  * Print a warning message.
  28  */
  29 ENTRY(insl)
  30 ENTRY(outsl)
  31 ENTRY(insb)
  32 ENTRY(outsb)
  33                 adr     r0, io_long_warning
  34                 mov     r1, lr
  35                 b       SYMBOL_NAME(printk)
  36
  37 io_long_warning:
  38                 .ascii  "<4>ins?/outs? not implemented on this architecture\0"
  39                 .align
  40
  41 @ Purpose: read a block of data from a hardware register to memory.
  42 @ Proto  : insw(int from_port, void *to, int len_in_words);
  43 @ Proto  : inswb(int from_port, void *to, int len_in_bytes);
  44 @ Notes  : increment to
  45
  46 ENTRY(insw)
  47                 mov     r2, r2, lsl#1
  48 ENTRY(inswb)
  49                 mov     ip, sp
  50                 stmfd   sp!, {r4 - r10 ,fp ,ip ,lr ,pc}
  51                 sub     fp, ip, #4
  52                 cmp     r0, #0x00c00000
  53                 movge   r3, #0
  54                 movlt   r3, #0xf0000000
  55                 add     r0, r3, r0, lsl #2
  56                 tst     r1, #3
  57                 beq     Linswok
  58                 tst     r1, #1
  59                 bne     Linsw_notaligned
  60                 cmp     r2, #1
  61                 ldrge   r4, [r0]
  62                 strgeb  r4, [r1], #1
  63                 movgt   r4, r4, LSR#8
  64                 strgtb  r4, [r1], #1
  65                 ldmleea fp, {r4 - r10, fp, sp, pc}^
  66                 sub     r2, r2, #2
  67 Linswok:        mov     ip, #0xFF
  68                 orr     ip, ip, ip, lsl #8
  69 Linswlp:        subs    r2, r2, #64
  70                 bmi     Linsw_toosmall
  71                 IN(r3)
  72                 IN(r4)
  73                 IN(r5)
  74                 IN(r6)
  75                 IN(r7)
  76                 IN(r8)
  77                 IN(r9)
  78                 IN(r10)
  79                 stmia   r1!, {r3 - r10}
  80                 IN(r3)
  81                 IN(r4)
  82                 IN(r5)
  83                 IN(r6)
  84                 IN(r7)
  85                 IN(r8)
  86                 IN(r9)
  87                 IN(r10)
  88                 stmia   r1!, {r3 - r10}
  89                 bne     Linswlp
  90                 LOADREGS(ea, fp, {r4 - r10, fp, sp, pc})
  91 Linsw_toosmall:
  92                 add     r2, r2, #32
  93                 bmi     Linsw_toosmall2
  94 Linsw2lp:       IN(r3)
  95                 IN(r4)
  96                 IN(r5)
  97                 IN(r6)
  98                 IN(r7)
  99                 IN(r8)
 100                 IN(r9)
 101                 IN(r10)
 102                 stmia   r1!, {r3 - r10}
 103                 LOADREGS(eqea, fp, {r4 - r10, fp, sp, pc})
 104                 b       Linsw_notaligned
 105 Linsw_toosmall2:
 106                 add     r2, r2, #32
 107 Linsw_notaligned:
 108                 cmp     r2, #1
 109                 LOADREGS(ltea, fp, {r4 - r10, fp, sp, pc})
 110                 ldr     r4, [r0]
 111                 strb    r4, [r1], #1
 112                 movgt   r4, r4, LSR#8
 113                 strgtb  r4, [r1], #1
 114                 subs    r2, r2, #2
 115                 bgt     Linsw_notaligned
 116                 LOADREGS(ea, fp, {r4 - r10, fp, sp, pc})
 117
 118 @ Purpose: write a block of data from memory to a hardware register.
 119 @ Proto  : outsw(int to_reg, void *from, int len_in_words);
 120 @ Proto  : outswb(int to_reg, void *from, int len_in_bytes);
 121 @ Notes  : increments from
 122
 123 ENTRY(outsw)
 124                 mov     r2, r2, LSL#1
 125 ENTRY(outswb)
 126                 mov     ip, sp
 127                 stmfd   sp!, {r4 - r8, fp, ip, lr, pc}
 128                 sub     fp, ip, #4
 129                 cmp     r0, #0x00c00000
 130                 movge   r3, #0
 131                 movlt   r3, #0xf0000000
 132                 tst     r1, #2
 133                 beq     Loutsw32lp
 134                 ldr     r4, [r1], #2
 135                 mov     r4, r4, lsl #16
 136                 orr     r4, r4, r4, lsr #16
 137                 str     r4, [r3, r0, lsl #2]
 138                 sub     r2, r2, #2
 139                 teq     r2, #0
 140                 LOADREGS(eqea, fp, {r4 - r8, fp, sp, pc})
 141 Loutsw32lp:     subs    r2,r2,#32
 142                 blt     Loutsw_toosmall
 143                 ldmia   r1!,{r4,r5,r6,r7}
 144                 OUT(r4)
 145                 OUT(r5)
 146                 OUT(r6)
 147                 OUT(r7)
 148                 ldmia   r1!,{r4,r5,r6,r7}
 149                 OUT(r4)
 150                 OUT(r5)
 151                 OUT(r6)
 152                 OUT(r7)
 153                 LOADREGS(eqea, fp, {r4 - r8, fp, sp, pc})
 154                 b       Loutsw32lp
 155 Loutsw_toosmall:
 156                 adds    r2,r2,#32
 157                 LOADREGS(eqea, fp, {r4 - r8, fp, sp, pc})
 158 Llpx:           ldr     r4,[r1],#2
 159                 mov     r4,r4,LSL#16
 160                 orr     r4,r4,r4,LSR#16
 161                 str     r4,[r3,r0,LSL#2]
 162                 subs    r2,r2,#2
 163                 bgt     Llpx
 164                 LOADREGS(ea, fp, {r4 - r8, fp, sp, pc})
 165