i386/linux-2.3.21/drivers/acorn/net/ether3.h

   1 /*
   2  * linux/drivers/net/ether3.h
   3  *
   4  * network driver for Acorn/ANT Ether3 cards
   5  */
   6
   7 #ifndef _LINUX_ether3_H
   8 #define _LINUX_ether3_H
   9
  10 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
  11 #define DEBUG_TX         2
  12 #define DEBUG_RX         4
  13 #define DEBUG_INT        8
  14 #define DEBUG_IC        16
  15 #ifndef NET_DEBUG
  16 #define NET_DEBUG       0
  17 #endif
  18
  19 /* Command register definitions & bits */
  20 #define REG_COMMAND             (dev->base_addr + 0x00)
  21 #define CMD_ENINTDMA            0x0001
  22 #define CMD_ENINTRX             0x0002
  23 #define CMD_ENINTTX             0x0004
  24 #define CMD_ENINTBUFWIN         0x0008
  25 #define CMD_ACKINTDMA           0x0010
  26 #define CMD_ACKINTRX            0x0020
  27 #define CMD_ACKINTTX            0x0040
  28 #define CMD_ACKINTBUFWIN        0x0080
  29 #define CMD_DMAON               0x0100
  30 #define CMD_RXON                0x0200
  31 #define CMD_TXON                0x0400
  32 #define CMD_DMAOFF              0x0800
  33 #define CMD_RXOFF               0x1000
  34 #define CMD_TXOFF               0x2000
  35 #define CMD_FIFOREAD            0x4000
  36 #define CMD_FIFOWRITE           0x8000
  37
  38 /* status register */
  39 #define REG_STATUS              (dev->base_addr + 0x00)
  40 #define STAT_ENINTSTAT          0x0001
  41 #define STAT_ENINTRX            0x0002
  42 #define STAT_ENINTTX            0x0004
  43 #define STAT_ENINTBUFWIN        0x0008
  44 #define STAT_INTDMA             0x0010
  45 #define STAT_INTRX              0x0020
  46 #define STAT_INTTX              0x0040
  47 #define STAT_INTBUFWIN          0x0080
  48 #define STAT_DMAON              0x0100
  49 #define STAT_RXON               0x0200
  50 #define STAT_TXON               0x0400
  51 #define STAT_FIFOFULL           0x2000
  52 #define STAT_FIFOEMPTY          0x4000
  53 #define STAT_FIFODIR            0x8000
  54
  55 /* configuration register 1 */
  56 #define REG_CONFIG1             (dev->base_addr + 0x10)
  57 #define CFG1_BUFSELSTAT0        0x0000
  58 #define CFG1_BUFSELSTAT1        0x0001
  59 #define CFG1_BUFSELSTAT2        0x0002
  60 #define CFG1_BUFSELSTAT3        0x0003
  61 #define CFG1_BUFSELSTAT4        0x0004
  62 #define CFG1_BUFSELSTAT5        0x0005
  63 #define CFG1_ADDRPROM           0x0006
  64 #define CFG1_TRANSEND           0x0007
  65 #define CFG1_LOCBUFMEM          0x0008
  66 #define CFG1_INTVECTOR          0x0009
  67 #define CFG1_RECVSPECONLY       0x0000
  68 #define CFG1_RECVSPECBROAD      0x4000
  69 #define CFG1_RECVSPECBRMULTI    0x8000
  70 #define CFG1_RECVPROMISC        0xC000
  71
  72 /* The following aren't in 8004 */
  73 #define CFG1_DMABURSTCONT       0x0000
  74 #define CFG1_DMABURST800NS      0x0010
  75 #define CFG1_DMABURST1600NS     0x0020
  76 #define CFG1_DMABURST3200NS     0x0030
  77 #define CFG1_DMABURST1          0x0000
  78 #define CFG1_DMABURST4          0x0040
  79 #define CFG1_DMABURST8          0x0080
  80 #define CFG1_DMABURST16         0x00C0
  81 #define CFG1_RECVCOMPSTAT0      0x0100
  82 #define CFG1_RECVCOMPSTAT1      0x0200
  83 #define CFG1_RECVCOMPSTAT2      0x0400
  84 #define CFG1_RECVCOMPSTAT3      0x0800
  85 #define CFG1_RECVCOMPSTAT4      0x1000
  86 #define CFG1_RECVCOMPSTAT5      0x2000
  87
  88 /* configuration register 2 */
  89 #define REG_CONFIG2             (dev->base_addr + 0x20)
  90 #define CFG2_BYTESWAP           0x0001
  91 #define CFG2_ERRENCRC           0x0008
  92 #define CFG2_ERRENDRIBBLE       0x0010
  93 #define CFG2_ERRSHORTFRAME      0x0020
  94 #define CFG2_SLOTSELECT         0x0040
  95 #define CFG2_PREAMSELECT        0x0080
  96 #define CFG2_ADDRLENGTH         0x0100
  97 #define CFG2_RECVCRC            0x0200
  98 #define CFG2_XMITNOCRC          0x0400
  99 #define CFG2_LOOPBACK           0x0800
 100 #define CFG2_CTRLO              0x1000
 101 #define CFG2_RESET              0x8000
 102
 103 #define REG_RECVEND             (dev->base_addr + 0x30)
 104
 105 #define REG_BUFWIN              (dev->base_addr + 0x40)
 106
 107 #define REG_RECVPTR             (dev->base_addr + 0x50)
 108
 109 #define REG_TRANSMITPTR         (dev->base_addr + 0x60)
 110
 111 #define REG_DMAADDR             (dev->base_addr + 0x70)
 112
 113 /*
 114  * Cards transmit/receive headers
 115  */
 116 #define TX_NEXT                 (0xffff)
 117 #define TXHDR_ENBABBLEINT       (1 << 16)
 118 #define TXHDR_ENCOLLISIONINT    (1 << 17)
 119 #define TXHDR_EN16COLLISION     (1 << 18)
 120 #define TXHDR_ENSUCCESS         (1 << 19)
 121 #define TXHDR_DATAFOLLOWS       (1 << 21)
 122 #define TXHDR_CHAINCONTINUE     (1 << 22)
 123 #define TXHDR_TRANSMIT          (1 << 23)
 124 #define TXSTAT_BABBLED          (1 << 24)
 125 #define TXSTAT_COLLISION        (1 << 25)
 126 #define TXSTAT_16COLLISIONS     (1 << 26)
 127 #define TXSTAT_DONE             (1 << 31)
 128
 129 #define RX_NEXT                 (0xffff)
 130 #define RXHDR_CHAINCONTINUE     (1 << 6)
 131 #define RXHDR_RECEIVE           (1 << 7)
 132 #define RXSTAT_OVERSIZE         (1 << 8)
 133 #define RXSTAT_CRCERROR         (1 << 9)
 134 #define RXSTAT_DRIBBLEERROR     (1 << 10)
 135 #define RXSTAT_SHORTPACKET      (1 << 11)
 136 #define RXSTAT_DONE             (1 << 15)
 137
 138
 139 #define TX_START        0x0000
 140 #define TX_END          0x6000
 141 #define RX_START        0x6000
 142 #define RX_LEN          0xA000
 143 #define RX_END          0x10000
 144 /* must be a power of 2 and greater than MAX_TX_BUFFERED */
 145 #define MAX_TXED        16
 146 #define MAX_TX_BUFFERED 10
 147
 148 struct dev_priv {
 149     struct {
 150         unsigned int command;
 151         unsigned int config1;
 152         unsigned int config2;
 153     } regs;
 154     unsigned char tx_head;              /* buffer nr to insert next packet       */
 155     unsigned char tx_tail;              /* buffer nr of transmitting packet      */
 156     unsigned int rx_head;               /* address to fetch next packet from     */
 157     struct enet_statistics stats;
 158     struct timer_list timer;
 159     int broken;                         /* 0 = ok, 1 = something went wrong      */
 160 };
 161
 162 extern int      ether3_probe (struct net_device *dev);
 163 static int      ether3_probe1 (struct net_device *dev);
 164 static int      ether3_open (struct net_device *dev);
 165 static int      ether3_sendpacket (struct sk_buff *skb, struct net_device *dev);
 166 static void     ether3_interrupt (int irq, void *dev_id, struct pt_regs *regs);
 167 static int      ether3_close (struct net_device *dev);
 168 static struct enet_statistics *ether3_getstats (struct net_device *dev);
 169 static void     ether3_setmulticastlist (struct net_device *dev);
 170
 171 #endif